xml/p10/node_pau_fir_0.xml

<?xml version="1.0" encoding="UTF-8"?>
<attn_node model_ec="P10_10,P10_20" name="PAU_FIR_0" reg_type="SCOM">
    <local_fir config="" name="PAU_FIR_0">
        <instance addr="0x10010C00" reg_inst="0"/>
        <instance addr="0x11010C00" reg_inst="3"/>
        <instance addr="0x12010C00" reg_inst="4"/>
        <instance addr="0x12011400" reg_inst="5"/>
        <instance addr="0x13010C00" reg_inst="6"/>
        <instance addr="0x13011400" reg_inst="7"/>
        <action attn_type="CS" config="00"/>
        <action attn_type="RE" config="01"/>
        <action attn_type="UCS" config="11"/>
    </local_fir>
    <bit pos="0">NTL array CE</bit>
    <bit pos="1">NTL header array UE</bit>
    <bit pos="2">NTL data array UE</bit>
    <bit pos="3">NTL NVLInk Control/Header/AE Parity error</bit>
    <bit pos="4">NTL NVLink Data Parity error</bit>
    <bit pos="5">NTL NVLink Malformed Packet</bit>
    <bit pos="6">NTL NVLink Unsupported Packet</bit>
    <bit pos="7">NTL NVLink Config errors</bit>
    <bit pos="8">NTL NVLink CRC errors or LMD=Stomp</bit>
    <bit pos="9">NTL PRI errors</bit>
    <bit pos="10">NTL logic error</bit>
    <bit pos="11">NTL LMD=Data Poison</bit>
    <bit pos="12">NTL data array SUE</bit>
    <bit pos="13">CQ CTL/SM ASBE Array single-bit correctable error</bit>
    <bit pos="14">CQ CTL/SM PBR PowerBus Recoverable</bit>
    <bit pos="15">CQ CTL/SM REG Register ring error</bit>
    <bit pos="16">CQ CTL/SM DUE Data Uncorrectable error for MMIO store data</bit>
    <bit pos="17">CQ CTL/SM UT=1 to frozen PE</bit>
    <bit pos="18">CQ CTL/SM NCF NVLink configuration error</bit>
    <bit pos="19">CQ CTL/SM NVF NVLink fatal</bit>
    <bit pos="20">CQ CTL/SM OCR OpenCAPI Recoverable, Command failed, and brick not fenced.</bit>
    <bit pos="21">CQ CTL/SM AUE Array uncorrectable error</bit>
    <bit pos="22">CQ CTL/SM PBP PowerBus parity error</bit>
    <bit pos="23">CQ CTL/SM PBF PowerBus Fatal</bit>
    <bit pos="24">CQ CTL/SM PBC PowerBus configuration error</bit>
    <bit pos="25">CQ CTL/SM FWD Forward-Progress</bit>
    <bit pos="26">CQ CTL/SM NLG PAU Logic error</bit>
    <bit pos="27">Cresp=Addr_Error received for a load command</bit>
    <bit pos="28">Cresp=Addr_Error received for a store command</bit>
    <bit pos="29">CQ DAT ECC UE on data/BE arrays</bit>
    <bit pos="30">CQ DAT ECC CE on data/BE arrays</bit>
    <bit pos="31">CQ DAT parity error on data/BE latches</bit>
    <bit pos="32">CQ DAT parity errors on configuration registers</bit>
    <bit pos="33">CQ DAT parity errors on received PowerBus rtag</bit>
    <bit pos="34">CQ DAT parity errors on internal state latches</bit>
    <bit pos="35">CQ DAT logic error</bit>
    <bit pos="36">CQ DAT ECC SUE on data/BE arrays</bit>
    <bit pos="37">CQ DAT ECC SUE on PB receive data</bit>
    <bit pos="38">CQ DAT Reserved, macro bit 9</bit>
    <bit pos="39">CQ DAT Reserved, macro bit 10</bit>
    <bit pos="40">XTS internal logic error</bit>
    <bit pos="41">XTS correctable errors in XTS internal SRAM</bit>
    <bit pos="42">XTS uncorrectable errors in XTS internal SRAM</bit>
    <bit pos="43">XTS correctable error on incoming stack transactions</bit>
    <bit pos="44">XTS uncorrectable/protocol errors on incoming stack transaction</bit>
    <bit pos="45">XTS protocol errors on incoming PBUS transaction</bit>
    <bit pos="46">XTS Translate Request Fail</bit>
    <bit pos="47">XTS informational fir that is set when the snooper retries a rpt_hang.check or rpt_hang.poll command.</bit>
    <bit pos="48">XTS Reserved, macro bit 8</bit>
    <bit pos="49">XTS Reserved, macro bit 9</bit>
    <bit pos="50">XTS Reserved, macro bit 10</bit>
    <bit pos="51">XTS Reserved, macro bit 11</bit>
    <bit pos="52">XTS Reserved, macro bit 12</bit>
    <bit pos="53">XTS Reserved, macro bit 13</bit>
    <bit pos="54">XTS Reserved, macro bit 14</bit>
    <bit pos="55">XTS Reserved, macro bit 15</bit>
    <bit pos="56">XTS Reserved, macro bit 16</bit>
    <bit pos="57">XTS Reserved, macro bit 17</bit>
    <bit pos="58">XTS Reserved, macro bit 18</bit>
    <bit pos="59">AME Reserved, interrupt</bit>
    <bit pos="60">AME data ECC UE</bit>
    <bit pos="61">AME data SUE</bit>
    <bit pos="62">Unused FIR</bit>
    <bit pos="63">Unused FIR</bit>
</attn_node>