| Zane Shelley | b9ea93c | 2023-03-10 10:41:41 -0600 | [diff] [blame] | 1 | { |
| 2 | "version": 1, |
| 3 | "model_ec": ["P10_10"], |
| 4 | "registers": { |
| 5 | "MC_OMI_DL_FIR": { |
| 6 | "instances": { |
| 7 | "0": "0x0C011400", |
| 8 | "1": "0x0C011800", |
| 9 | "2": "0x0D011400", |
| 10 | "3": "0x0D011800", |
| 11 | "4": "0x0E011400", |
| 12 | "5": "0x0E011800", |
| 13 | "6": "0x0F011400", |
| 14 | "7": "0x0F011800" |
| 15 | } |
| 16 | }, |
| 17 | "MC_OMI_DL_FIR_MASK": { |
| 18 | "instances": { |
| 19 | "0": "0x0C011403", |
| 20 | "1": "0x0C011803", |
| 21 | "2": "0x0D011403", |
| 22 | "3": "0x0D011803", |
| 23 | "4": "0x0E011403", |
| 24 | "5": "0x0E011803", |
| 25 | "6": "0x0F011403", |
| 26 | "7": "0x0F011803" |
| 27 | } |
| 28 | }, |
| 29 | "MC_OMI_DL_FIR_ACT0": { |
| 30 | "instances": { |
| 31 | "0": "0x0C011406", |
| 32 | "1": "0x0C011806", |
| 33 | "2": "0x0D011406", |
| 34 | "3": "0x0D011806", |
| 35 | "4": "0x0E011406", |
| 36 | "5": "0x0E011806", |
| 37 | "6": "0x0F011406", |
| 38 | "7": "0x0F011806" |
| 39 | } |
| 40 | }, |
| 41 | "MC_OMI_DL_FIR_ACT1": { |
| 42 | "instances": { |
| 43 | "0": "0x0C011407", |
| 44 | "1": "0x0C011807", |
| 45 | "2": "0x0D011407", |
| 46 | "3": "0x0D011807", |
| 47 | "4": "0x0E011407", |
| 48 | "5": "0x0E011807", |
| 49 | "6": "0x0F011407", |
| 50 | "7": "0x0F011807" |
| 51 | } |
| 52 | }, |
| 53 | "MC_OMI_DL_FIR_WOF": { |
| 54 | "instances": { |
| 55 | "0": "0x0C011408", |
| 56 | "1": "0x0C011808", |
| 57 | "2": "0x0D011408", |
| 58 | "3": "0x0D011808", |
| 59 | "4": "0x0E011408", |
| 60 | "5": "0x0E011808", |
| 61 | "6": "0x0F011408", |
| 62 | "7": "0x0F011808" |
| 63 | } |
| 64 | } |
| 65 | }, |
| 66 | "isolation_nodes": { |
| 67 | "MC_OMI_DL_FIR": { |
| 68 | "instances": [0, 1, 2, 3, 4, 5, 6, 7], |
| 69 | "rules": [ |
| 70 | { |
| 71 | "attn_type": ["CS"], |
| 72 | "node_inst": [0, 1, 2, 3, 4, 5, 6, 7], |
| 73 | "expr": { |
| 74 | "expr_type": "and", |
| 75 | "exprs": [ |
| 76 | { |
| 77 | "expr_type": "reg", |
| 78 | "reg_name": "MC_OMI_DL_FIR" |
| 79 | }, |
| 80 | { |
| 81 | "expr_type": "not", |
| 82 | "expr": { |
| 83 | "expr_type": "reg", |
| 84 | "reg_name": "MC_OMI_DL_FIR_MASK" |
| 85 | } |
| 86 | }, |
| 87 | { |
| 88 | "expr_type": "not", |
| 89 | "expr": { |
| 90 | "expr_type": "reg", |
| 91 | "reg_name": "MC_OMI_DL_FIR_ACT0" |
| 92 | } |
| 93 | }, |
| 94 | { |
| 95 | "expr_type": "not", |
| 96 | "expr": { |
| 97 | "expr_type": "reg", |
| 98 | "reg_name": "MC_OMI_DL_FIR_ACT1" |
| 99 | } |
| 100 | } |
| 101 | ] |
| 102 | } |
| 103 | }, |
| 104 | { |
| 105 | "attn_type": ["RE"], |
| 106 | "node_inst": [0, 1, 2, 3, 4, 5, 6, 7], |
| 107 | "expr": { |
| 108 | "expr_type": "and", |
| 109 | "exprs": [ |
| 110 | { |
| 111 | "expr_type": "reg", |
| 112 | "reg_name": "MC_OMI_DL_FIR" |
| 113 | }, |
| 114 | { |
| 115 | "expr_type": "not", |
| 116 | "expr": { |
| 117 | "expr_type": "reg", |
| 118 | "reg_name": "MC_OMI_DL_FIR_MASK" |
| 119 | } |
| 120 | }, |
| 121 | { |
| 122 | "expr_type": "not", |
| 123 | "expr": { |
| 124 | "expr_type": "reg", |
| 125 | "reg_name": "MC_OMI_DL_FIR_ACT0" |
| 126 | } |
| 127 | }, |
| 128 | { |
| 129 | "expr_type": "reg", |
| 130 | "reg_name": "MC_OMI_DL_FIR_ACT1" |
| 131 | } |
| 132 | ] |
| 133 | } |
| 134 | }, |
| 135 | { |
| 136 | "attn_type": ["SPA"], |
| 137 | "node_inst": [0, 1, 2, 3, 4, 5, 6, 7], |
| 138 | "expr": { |
| 139 | "expr_type": "and", |
| 140 | "exprs": [ |
| 141 | { |
| 142 | "expr_type": "reg", |
| 143 | "reg_name": "MC_OMI_DL_FIR" |
| 144 | }, |
| 145 | { |
| 146 | "expr_type": "not", |
| 147 | "expr": { |
| 148 | "expr_type": "reg", |
| 149 | "reg_name": "MC_OMI_DL_FIR_MASK" |
| 150 | } |
| 151 | }, |
| 152 | { |
| 153 | "expr_type": "reg", |
| 154 | "reg_name": "MC_OMI_DL_FIR_ACT0" |
| 155 | }, |
| 156 | { |
| 157 | "expr_type": "not", |
| 158 | "expr": { |
| 159 | "expr_type": "reg", |
| 160 | "reg_name": "MC_OMI_DL_FIR_ACT1" |
| 161 | } |
| 162 | } |
| 163 | ] |
| 164 | } |
| 165 | } |
| 166 | ], |
| 167 | "bits": { |
| 168 | "0": { |
| 169 | "desc": "OMI-DL0 fatal error", |
| 170 | "child_node": { |
| 171 | "name": "MC_OMI_DL_ERR_RPT", |
| 172 | "inst": { |
| 173 | "0": 0, |
| 174 | "1": 2, |
| 175 | "2": 4, |
| 176 | "3": 6, |
| 177 | "4": 8, |
| 178 | "5": 10, |
| 179 | "6": 12, |
| 180 | "7": 14 |
| 181 | } |
| 182 | } |
| 183 | }, |
| 184 | "1": { |
| 185 | "desc": "OMI-DL0 UE on data flit" |
| 186 | }, |
| 187 | "2": { |
| 188 | "desc": "OMI-DL0 CE on TL flit" |
| 189 | }, |
| 190 | "3": { |
| 191 | "desc": "OMI-DL0 detected a CRC error" |
| 192 | }, |
| 193 | "4": { |
| 194 | "desc": "OMI-DL0 received a nack" |
| 195 | }, |
| 196 | "5": { |
| 197 | "desc": "OMI-DL0 running in degraded mode" |
| 198 | }, |
| 199 | "6": { |
| 200 | "desc": "OMI-DL0 parity error detection on a lane" |
| 201 | }, |
| 202 | "7": { |
| 203 | "desc": "OMI-DL0 retrained due to no forward progress" |
| 204 | }, |
| 205 | "8": { |
| 206 | "desc": "OMI-DL0 remote side initiated a retrain" |
| 207 | }, |
| 208 | "9": { |
| 209 | "desc": "OMI-DL0 retrain due to internal error or software" |
| 210 | }, |
| 211 | "10": { |
| 212 | "desc": "OMI-DL0 threshold reached" |
| 213 | }, |
| 214 | "11": { |
| 215 | "desc": "OMI-DL0 trained" |
| 216 | }, |
| 217 | "12": { |
| 218 | "desc": "OMI-DL0 endpoint error bit 0" |
| 219 | }, |
| 220 | "13": { |
| 221 | "desc": "OMI-DL0 endpoint error bit 1" |
| 222 | }, |
| 223 | "14": { |
| 224 | "desc": "OMI-DL0 endpoint error bit 2" |
| 225 | }, |
| 226 | "15": { |
| 227 | "desc": "OMI-DL0 endpoint error bit 3" |
| 228 | }, |
| 229 | "16": { |
| 230 | "desc": "OMI-DL0 endpoint error bit 4" |
| 231 | }, |
| 232 | "17": { |
| 233 | "desc": "OMI-DL0 endpoint error bit 5" |
| 234 | }, |
| 235 | "18": { |
| 236 | "desc": "OMI-DL0 endpoint error bit 6" |
| 237 | }, |
| 238 | "19": { |
| 239 | "desc": "OMI-DL0 endpoint error bit 7" |
| 240 | }, |
| 241 | "20": { |
| 242 | "desc": "OMI-DL1 fatal error", |
| 243 | "child_node": { |
| 244 | "name": "MC_OMI_DL_ERR_RPT", |
| 245 | "inst": { |
| 246 | "0": 1, |
| 247 | "1": 3, |
| 248 | "2": 5, |
| 249 | "3": 7, |
| 250 | "4": 9, |
| 251 | "5": 11, |
| 252 | "6": 13, |
| 253 | "7": 15 |
| 254 | } |
| 255 | } |
| 256 | }, |
| 257 | "21": { |
| 258 | "desc": "OMI-DL1 UE on data flit" |
| 259 | }, |
| 260 | "22": { |
| 261 | "desc": "OMI-DL1 CE on TL flit" |
| 262 | }, |
| 263 | "23": { |
| 264 | "desc": "OMI-DL1 detected a CRC error" |
| 265 | }, |
| 266 | "24": { |
| 267 | "desc": "OMI-DL1 received a nack" |
| 268 | }, |
| 269 | "25": { |
| 270 | "desc": "OMI-DL1 running in degraded mode" |
| 271 | }, |
| 272 | "26": { |
| 273 | "desc": "OMI-DL1 parity error detection on a lane" |
| 274 | }, |
| 275 | "27": { |
| 276 | "desc": "OMI-DL1 retrained due to no forward progress" |
| 277 | }, |
| 278 | "28": { |
| 279 | "desc": "OMI-DL1 remote side initiated a retrain" |
| 280 | }, |
| 281 | "29": { |
| 282 | "desc": "OMI-DL1 retrain due to internal error or software" |
| 283 | }, |
| 284 | "30": { |
| 285 | "desc": "OMI-DL1 threshold reached" |
| 286 | }, |
| 287 | "31": { |
| 288 | "desc": "OMI-DL1 trained" |
| 289 | }, |
| 290 | "32": { |
| 291 | "desc": "OMI-DL1 endpoint error bit 0" |
| 292 | }, |
| 293 | "33": { |
| 294 | "desc": "OMI-DL1 endpoint error bit 1" |
| 295 | }, |
| 296 | "34": { |
| 297 | "desc": "OMI-DL1 endpoint error bit 2" |
| 298 | }, |
| 299 | "35": { |
| 300 | "desc": "OMI-DL1 endpoint error bit 3" |
| 301 | }, |
| 302 | "36": { |
| 303 | "desc": "OMI-DL1 endpoint error bit 4" |
| 304 | }, |
| 305 | "37": { |
| 306 | "desc": "OMI-DL1 endpoint error bit 5" |
| 307 | }, |
| 308 | "38": { |
| 309 | "desc": "OMI-DL1 endpoint error bit 6" |
| 310 | }, |
| 311 | "39": { |
| 312 | "desc": "OMI-DL1 endpoint error bit 7" |
| 313 | }, |
| 314 | "40": { |
| 315 | "desc": "OMI-DL2 unused" |
| 316 | }, |
| 317 | "41": { |
| 318 | "desc": "OMI-DL2 unused" |
| 319 | }, |
| 320 | "42": { |
| 321 | "desc": "OMI-DL2 unused" |
| 322 | }, |
| 323 | "43": { |
| 324 | "desc": "OMI-DL2 unused" |
| 325 | }, |
| 326 | "44": { |
| 327 | "desc": "OMI-DL2 unused" |
| 328 | }, |
| 329 | "45": { |
| 330 | "desc": "OMI-DL2 unused" |
| 331 | }, |
| 332 | "46": { |
| 333 | "desc": "OMI-DL2 unused" |
| 334 | }, |
| 335 | "47": { |
| 336 | "desc": "OMI-DL2 unused" |
| 337 | }, |
| 338 | "48": { |
| 339 | "desc": "OMI-DL2 unused" |
| 340 | }, |
| 341 | "49": { |
| 342 | "desc": "OMI-DL2 unused" |
| 343 | }, |
| 344 | "50": { |
| 345 | "desc": "OMI-DL2 unused" |
| 346 | }, |
| 347 | "51": { |
| 348 | "desc": "OMI-DL2 unused" |
| 349 | }, |
| 350 | "52": { |
| 351 | "desc": "OMI-DL2 unused" |
| 352 | }, |
| 353 | "53": { |
| 354 | "desc": "OMI-DL2 unused" |
| 355 | }, |
| 356 | "54": { |
| 357 | "desc": "OMI-DL2 unused" |
| 358 | }, |
| 359 | "55": { |
| 360 | "desc": "OMI-DL2 unused" |
| 361 | }, |
| 362 | "56": { |
| 363 | "desc": "OMI-DL2 unused" |
| 364 | }, |
| 365 | "57": { |
| 366 | "desc": "OMI-DL2 unused" |
| 367 | }, |
| 368 | "58": { |
| 369 | "desc": "OMI-DL2 unused" |
| 370 | }, |
| 371 | "59": { |
| 372 | "desc": "OMI-DL2 unused" |
| 373 | }, |
| 374 | "60": { |
| 375 | "desc": "Performance monitor wrapped" |
| 376 | }, |
| 377 | "61": { |
| 378 | "desc": "OMI-DL common FIR Register" |
| 379 | } |
| 380 | }, |
| 381 | "capture_groups": [ |
| 382 | { |
| 383 | "group_name": "MC_OMI_DL_FIR", |
| 384 | "group_inst": { |
| 385 | "0": 0, |
| 386 | "1": 1, |
| 387 | "2": 2, |
| 388 | "3": 3, |
| 389 | "4": 4, |
| 390 | "5": 5, |
| 391 | "6": 6, |
| 392 | "7": 7 |
| 393 | } |
| 394 | } |
| 395 | ] |
| 396 | } |
| 397 | } |
| 398 | } |