blob: 483f5614293c50a54379f6ca5c3fbeeb1b33e11d [file] [log] [blame]
Zane Shelleyb9ea93c2023-03-10 10:41:41 -06001{
2 "version": 1,
3 "model_ec": ["P10_10"],
4 "registers": {
5 "PAU_FIR_0": {
6 "instances": {
7 "0": "0x10010C00",
8 "3": "0x11010C00",
9 "4": "0x12010C00",
10 "5": "0x12011400",
11 "6": "0x13010C00",
12 "7": "0x13011400"
13 }
14 },
15 "PAU_FIR_0_MASK": {
16 "instances": {
17 "0": "0x10010C03",
18 "3": "0x11010C03",
19 "4": "0x12010C03",
20 "5": "0x12011403",
21 "6": "0x13010C03",
22 "7": "0x13011403"
23 }
24 },
25 "PAU_FIR_0_ACT0": {
26 "instances": {
27 "0": "0x10010C06",
28 "3": "0x11010C06",
29 "4": "0x12010C06",
30 "5": "0x12011406",
31 "6": "0x13010C06",
32 "7": "0x13011406"
33 }
34 },
35 "PAU_FIR_0_ACT1": {
36 "instances": {
37 "0": "0x10010C07",
38 "3": "0x11010C07",
39 "4": "0x12010C07",
40 "5": "0x12011407",
41 "6": "0x13010C07",
42 "7": "0x13011407"
43 }
44 }
45 },
46 "isolation_nodes": {
47 "PAU_FIR_0": {
48 "instances": [0, 3, 4, 5, 6, 7],
49 "rules": [
50 {
51 "attn_type": ["CS"],
52 "node_inst": [0, 3, 4, 5, 6, 7],
53 "expr": {
54 "expr_type": "and",
55 "exprs": [
56 {
57 "expr_type": "reg",
58 "reg_name": "PAU_FIR_0"
59 },
60 {
61 "expr_type": "not",
62 "expr": {
63 "expr_type": "reg",
64 "reg_name": "PAU_FIR_0_MASK"
65 }
66 },
67 {
68 "expr_type": "not",
69 "expr": {
70 "expr_type": "reg",
71 "reg_name": "PAU_FIR_0_ACT0"
72 }
73 },
74 {
75 "expr_type": "not",
76 "expr": {
77 "expr_type": "reg",
78 "reg_name": "PAU_FIR_0_ACT1"
79 }
80 }
81 ]
82 }
83 },
84 {
85 "attn_type": ["RE"],
86 "node_inst": [0, 3, 4, 5, 6, 7],
87 "expr": {
88 "expr_type": "and",
89 "exprs": [
90 {
91 "expr_type": "reg",
92 "reg_name": "PAU_FIR_0"
93 },
94 {
95 "expr_type": "not",
96 "expr": {
97 "expr_type": "reg",
98 "reg_name": "PAU_FIR_0_MASK"
99 }
100 },
101 {
102 "expr_type": "not",
103 "expr": {
104 "expr_type": "reg",
105 "reg_name": "PAU_FIR_0_ACT0"
106 }
107 },
108 {
109 "expr_type": "reg",
110 "reg_name": "PAU_FIR_0_ACT1"
111 }
112 ]
113 }
114 },
115 {
116 "attn_type": ["UCS"],
117 "node_inst": [0, 3, 4, 5, 6, 7],
118 "expr": {
119 "expr_type": "and",
120 "exprs": [
121 {
122 "expr_type": "reg",
123 "reg_name": "PAU_FIR_0"
124 },
125 {
126 "expr_type": "not",
127 "expr": {
128 "expr_type": "reg",
129 "reg_name": "PAU_FIR_0_MASK"
130 }
131 },
132 {
133 "expr_type": "reg",
134 "reg_name": "PAU_FIR_0_ACT0"
135 },
136 {
137 "expr_type": "reg",
138 "reg_name": "PAU_FIR_0_ACT1"
139 }
140 ]
141 }
142 }
143 ],
144 "bits": {
145 "0": {
146 "desc": "NTL array CE"
147 },
148 "1": {
149 "desc": "NTL header array UE"
150 },
151 "2": {
152 "desc": "NTL data array UE"
153 },
154 "3": {
155 "desc": "NTL NVLInk Control/Header/AE Parity error"
156 },
157 "4": {
158 "desc": "NTL NVLink Data Parity error"
159 },
160 "5": {
161 "desc": "NTL NVLink Malformed Packet"
162 },
163 "6": {
164 "desc": "NTL NVLink Unsupported Packet"
165 },
166 "7": {
167 "desc": "NTL NVLink Config errors"
168 },
169 "8": {
170 "desc": "NTL NVLink CRC errors or LMD=Stomp"
171 },
172 "9": {
173 "desc": "NTL PRI errors"
174 },
175 "10": {
176 "desc": "NTL logic error"
177 },
178 "11": {
179 "desc": "NTL LMD=Data Poison"
180 },
181 "12": {
182 "desc": "NTL data array SUE"
183 },
184 "13": {
185 "desc": "CQ CTL/SM ASBE Array single-bit correctable error"
186 },
187 "14": {
188 "desc": "CQ CTL/SM PBR PowerBus Recoverable"
189 },
190 "15": {
191 "desc": "CQ CTL/SM REG Register ring error"
192 },
193 "16": {
194 "desc": "CQ CTL/SM DUE Data Uncorrectable error for MMIO store data"
195 },
196 "17": {
197 "desc": "CQ CTL/SM UT=1 to frozen PE"
198 },
199 "18": {
200 "desc": "CQ CTL/SM NCF NVLink configuration error"
201 },
202 "19": {
203 "desc": "CQ CTL/SM NVF NVLink fatal"
204 },
205 "20": {
206 "desc": "CQ CTL/SM OCR OpenCAPI Recoverable, Command failed, and brick not fenced."
207 },
208 "21": {
209 "desc": "CQ CTL/SM AUE Array uncorrectable error"
210 },
211 "22": {
212 "desc": "CQ CTL/SM PBP PowerBus parity error"
213 },
214 "23": {
215 "desc": "CQ CTL/SM PBF PowerBus Fatal"
216 },
217 "24": {
218 "desc": "CQ CTL/SM PBC PowerBus configuration error"
219 },
220 "25": {
221 "desc": "CQ CTL/SM FWD Forward-Progress"
222 },
223 "26": {
224 "desc": "CQ CTL/SM NLG PAU Logic error"
225 },
226 "27": {
227 "desc": "Cresp=Addr_Error received for a load command"
228 },
229 "28": {
230 "desc": "Cresp=Addr_Error received for a store command"
231 },
232 "29": {
233 "desc": "CQ DAT ECC UE on data/BE arrays"
234 },
235 "30": {
236 "desc": "CQ DAT ECC CE on data/BE arrays"
237 },
238 "31": {
239 "desc": "CQ DAT parity error on data/BE latches"
240 },
241 "32": {
242 "desc": "CQ DAT parity errors on configuration registers"
243 },
244 "33": {
245 "desc": "CQ DAT parity errors on received PowerBus rtag"
246 },
247 "34": {
248 "desc": "CQ DAT parity errors on internal state latches"
249 },
250 "35": {
251 "desc": "CQ DAT logic error"
252 },
253 "36": {
254 "desc": "CQ DAT ECC SUE on data/BE arrays"
255 },
256 "37": {
257 "desc": "CQ DAT ECC SUE on PB receive data"
258 },
259 "38": {
260 "desc": "CQ DAT Reserved, macro bit 9"
261 },
262 "39": {
263 "desc": "CQ DAT Reserved, macro bit 10"
264 },
265 "40": {
266 "desc": "XTS internal logic error"
267 },
268 "41": {
269 "desc": "XTS correctable errors in XTS internal SRAM"
270 },
271 "42": {
272 "desc": "XTS uncorrectable errors in XTS internal SRAM"
273 },
274 "43": {
275 "desc": "XTS correctable error on incoming stack transactions"
276 },
277 "44": {
278 "desc": "XTS uncorrectable/protocol errors on incoming stack transaction"
279 },
280 "45": {
281 "desc": "XTS protocol errors on incoming PBUS transaction"
282 },
283 "46": {
284 "desc": "XTS Translate Request Fail"
285 },
286 "47": {
287 "desc": "XTS informational fir that is set when the snooper retries a rpt_hang.check or rpt_hang.poll command."
288 },
289 "48": {
290 "desc": "XTS Reserved, macro bit 8"
291 },
292 "49": {
293 "desc": "XTS Reserved, macro bit 9"
294 },
295 "50": {
296 "desc": "XTS Reserved, macro bit 10"
297 },
298 "51": {
299 "desc": "XTS Reserved, macro bit 11"
300 },
301 "52": {
302 "desc": "XTS Reserved, macro bit 12"
303 },
304 "53": {
305 "desc": "XTS Reserved, macro bit 13"
306 },
307 "54": {
308 "desc": "XTS Reserved, macro bit 14"
309 },
310 "55": {
311 "desc": "XTS Reserved, macro bit 15"
312 },
313 "56": {
314 "desc": "XTS Reserved, macro bit 16"
315 },
316 "57": {
317 "desc": "XTS Reserved, macro bit 17"
318 },
319 "58": {
320 "desc": "XTS Reserved, macro bit 18"
321 },
322 "59": {
323 "desc": "AME Reserved, interrupt"
324 },
325 "60": {
326 "desc": "AME data ECC UE"
327 },
328 "61": {
329 "desc": "AME data SUE"
330 },
331 "62": {
332 "desc": "Unused FIR"
333 },
334 "63": {
335 "desc": "Unused FIR"
336 }
337 }
338 }
339 }
340}