Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
Zane Shelley | f8a726b | 2020-12-16 21:29:32 -0600 | [diff] [blame] | 2 | <attn_node model_ec="P10_20" name="PAU_PHY_FIR" reg_type="SCOM"> |
Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 3 | <local_fir config="W" name="PAU_PHY_FIR"> |
| 4 | <instance addr="0x10012C00" reg_inst="0"/> |
| 5 | <instance addr="0x11012C00" reg_inst="1"/> |
| 6 | <instance addr="0x12012C00" reg_inst="2"/> |
| 7 | <instance addr="0x13012C00" reg_inst="3"/> |
| 8 | <action attn_type="CS" config="00"/> |
| 9 | <action attn_type="RE" config="01"/> |
| 10 | <action attn_type="SPA" config="10"/> |
| 11 | <action attn_type="UCS" config="11"/> |
| 12 | </local_fir> |
| 13 | <bit pos="0">FIR Register - A RX state machine parity or mode register parity error has occurred (IOO0).</bit> |
| 14 | <bit pos="1">FIR Register - A RX state machine parity or mode register parity error has occurred (IOO1).</bit> |
| 15 | <bit pos="2">FIR Register - A RX state machine parity or mode register parity error has occurred (OMI0).</bit> |
| 16 | <bit pos="3">FIR Register - A RX state machine parity or mode register parity error has occurred (OMI1).</bit> |
| 17 | <bit pos="4">FIR Register - A TX state machine parity or mode register parity error has occurred (IOO0).</bit> |
| 18 | <bit pos="5">FIR Register - A TX state machine parity or mode register parity error has occurred (IOO1).</bit> |
| 19 | <bit pos="6">FIR Register - A TX state machine parity or mode register parity error has occurred (OMI0).</bit> |
| 20 | <bit pos="7">FIR Register - A TX state machine parity or mode register parity error has occurred (OMI1).</bit> |
| 21 | <bit pos="8">FIR Register - A TX ZCAL state machine parity or mode register parity error has occurred.</bit> |
| 22 | <bit pos="9">FIR Register - A PPE internal error has occurred.</bit> |
| 23 | <bit pos="10">FIR Register - A PPE external error has occurred.</bit> |
| 24 | <bit pos="11">FIR Register - A PPE Halt due to Watchdog or Interrupt has occurred.</bit> |
| 25 | <bit pos="12">FIR Register - A PPE Halt due to Debug has occurred.</bit> |
| 26 | <bit pos="13">FIR Register - PPE Halted.</bit> |
| 27 | <bit pos="14">FIR Register - A PPE Watchdog Timeout has occurred.</bit> |
| 28 | <bit pos="15">FIR Register - A PPE Array Scrub was missed.</bit> |
| 29 | <bit pos="16">FIR Register - A PPE Array uncorrectable error has occurred.</bit> |
| 30 | <bit pos="17">FIR Register - A PPE Array correctable error has occurred.</bit> |
| 31 | <bit pos="18">FIR Register - A PPE Code Recal Abort has occurred.</bit> |
| 32 | <bit pos="19">FIR Register - A PPE Code Fatal Error has occurred.</bit> |
| 33 | <bit pos="20">FIR Register - A PPE Code Warning has occurred.</bit> |
| 34 | <bit pos="21">FIR Register - A PPE Code DFT Error has occurred.</bit> |
| 35 | <bit pos="22">FIR Register - A PPE Code Recal Not Run has occurred.</bit> |
| 36 | <bit pos="23">FIR Register - A PPE Code Thread Locked has occurred.</bit> |
| 37 | <bit pos="24">FIR Register - A PPE Code FIR 6 has occurred.</bit> |
| 38 | <bit pos="25">FIR Register - A PPE Code FIR 7 has occurred.</bit> |
Zane Shelley | f8a726b | 2020-12-16 21:29:32 -0600 | [diff] [blame] | 39 | <bit pos="26">FIR Register- A SCOM FSM or FIR register parity error has occurred.</bit> |
Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 40 | </attn_node> |