Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
Zane Shelley | f8a726b | 2020-12-16 21:29:32 -0600 | [diff] [blame] | 2 | <attn_node model_ec="P10_10,P10_20" name="CFIR_MC_CS_RE_SPA" reg_type="SCOM"> |
Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 3 | <register name="CFIR_MC_XSTOP"> |
| 4 | <instance addr="0x0C040000" reg_inst="0"/> |
| 5 | <instance addr="0x0D040000" reg_inst="1"/> |
| 6 | <instance addr="0x0E040000" reg_inst="2"/> |
| 7 | <instance addr="0x0F040000" reg_inst="3"/> |
| 8 | </register> |
| 9 | <register name="CFIR_MC_XSTOP_MASK"> |
| 10 | <instance addr="0x0C040040" reg_inst="0"/> |
| 11 | <instance addr="0x0D040040" reg_inst="1"/> |
| 12 | <instance addr="0x0E040040" reg_inst="2"/> |
| 13 | <instance addr="0x0F040040" reg_inst="3"/> |
| 14 | </register> |
| 15 | <register name="CFIR_MC_RECOV"> |
| 16 | <instance addr="0x0C040001" reg_inst="0"/> |
| 17 | <instance addr="0x0D040001" reg_inst="1"/> |
| 18 | <instance addr="0x0E040001" reg_inst="2"/> |
| 19 | <instance addr="0x0F040001" reg_inst="3"/> |
| 20 | </register> |
| 21 | <register name="CFIR_MC_RECOV_MASK"> |
| 22 | <instance addr="0x0C040041" reg_inst="0"/> |
| 23 | <instance addr="0x0D040041" reg_inst="1"/> |
| 24 | <instance addr="0x0E040041" reg_inst="2"/> |
| 25 | <instance addr="0x0F040041" reg_inst="3"/> |
| 26 | </register> |
| 27 | <register name="CFIR_MC_SPATTN"> |
| 28 | <instance addr="0x0C040002" reg_inst="0"/> |
| 29 | <instance addr="0x0D040002" reg_inst="1"/> |
| 30 | <instance addr="0x0E040002" reg_inst="2"/> |
| 31 | <instance addr="0x0F040002" reg_inst="3"/> |
| 32 | </register> |
| 33 | <register name="CFIR_MC_SPATTN_MASK"> |
| 34 | <instance addr="0x0C040042" reg_inst="0"/> |
| 35 | <instance addr="0x0D040042" reg_inst="1"/> |
| 36 | <instance addr="0x0E040042" reg_inst="2"/> |
| 37 | <instance addr="0x0F040042" reg_inst="3"/> |
| 38 | </register> |
| 39 | <rule attn_type="CS" node_inst="0:3"> |
| 40 | <expr type="and"> |
| 41 | <expr type="reg" value1="CFIR_MC_XSTOP"/> |
| 42 | <expr type="not"> |
| 43 | <expr type="reg" value1="CFIR_MC_XSTOP_MASK"/> |
| 44 | </expr> |
| 45 | <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/> |
| 46 | </expr> |
| 47 | </rule> |
| 48 | <rule attn_type="RE" node_inst="0:3"> |
| 49 | <expr type="and"> |
| 50 | <expr type="reg" value1="CFIR_MC_RECOV"/> |
| 51 | <expr type="not"> |
| 52 | <expr type="reg" value1="CFIR_MC_RECOV_MASK"/> |
| 53 | </expr> |
| 54 | <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/> |
| 55 | </expr> |
| 56 | </rule> |
| 57 | <rule attn_type="SPA" node_inst="0:3"> |
| 58 | <expr type="and"> |
| 59 | <expr type="reg" value1="CFIR_MC_SPATTN"/> |
| 60 | <expr type="not"> |
| 61 | <expr type="reg" value1="CFIR_MC_SPATTN_MASK"/> |
| 62 | </expr> |
| 63 | <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/> |
| 64 | </expr> |
| 65 | </rule> |
| 66 | <bit child_node="MC_LOCAL_FIR" node_inst="0,1,2,3" pos="4">Local FIR</bit> |
| 67 | <bit child_node="MC_DSTL_FIR" node_inst="0,2,4,6" pos="5">MC Fault Isolation Register (DSTLFIR)</bit> |
| 68 | <bit child_node="MC_USTL_FIR" node_inst="0,2,4,6" pos="6">MC Fault Isolation Register (USTLFIR)</bit> |
| 69 | <bit child_node="MC_DSTL_FIR" node_inst="1,3,5,7" pos="7">MC Fault Isolation Register (DSTLFIR)</bit> |
| 70 | <bit child_node="MC_USTL_FIR" node_inst="1,3,5,7" pos="8">MC Fault Isolation Register (USTLFIR)</bit> |
| 71 | <bit child_node="MC_FIR" node_inst="0,1,2,3" pos="9">MC Fault Isolation Register (MCFIR)</bit> |
| 72 | <bit child_node="MC_MISC_FIR" node_inst="0,1,2,3" pos="10">MISC Fault Isolation Register</bit> |
| 73 | <bit child_node="MC_OMI_DL_FIR" node_inst="0,2,4,6" pos="13">OMI-DL common FIR Register</bit> |
| 74 | <bit child_node="MC_OMI_DL_FIR" node_inst="1,3,5,7" pos="14">OMI-DL common FIR Register</bit> |
| 75 | </attn_node> |