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gerrit.openbmc.org / openbmc / openpower-libhei / 5119d963fc6f868d0ec08b92b1e90e86444e717f / . / chip_data / odyssey / node_tlx_fir.json
blob: 7ae6bc8f795355ef8708cc706481ba58e9f303cb [file] [log] [blame]
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]1{
2 "version": 1,
3 "model_ec": ["ODYSSEY_10"],
4 "registers": {
5 "TLX_FIR": {
6 "instances": {
7 "0": "0x08012000"
8 }
9 },
Caleb Palmer94ea8ed2024-07-25 14:26:46 -0500[diff] [blame]10 "TLX_FIR_OR": {
11 "access": "WO",
12 "instances": {
13 "0": "0x08012001"
14 }
15 },
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]16 "TLX_FIR_MASK": {
17 "instances": {
18 "0": "0x08012002"
19 }
20 },
Caleb Palmer94ea8ed2024-07-25 14:26:46 -0500[diff] [blame]21 "TLX_FIR_MASK_OR": {
22 "access": "WO",
23 "instances": {
24 "0": "0x08012003"
25 }
26 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]27 "TLX_FIR_CFG_CHIP_CS": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]28 "instances": {
29 "0": "0x08012004"
30 }
31 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]32 "TLX_FIR_CFG_RECOV": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]33 "instances": {
34 "0": "0x08012005"
35 }
36 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]37 "TLX_FIR_CFG_SP_ATTN": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]38 "instances": {
39 "0": "0x08012006"
40 }
41 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]42 "TLX_FIR_CFG_UNIT_CS": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]43 "instances": {
44 "0": "0x08012007"
45 }
46 },
47 "TLX_FIR_WOF": {
48 "instances": {
49 "0": "0x08012008"
50 }
51 },
52 "SRQ_ROQ_CTL_0": {
53 "instances": {
54 "0": "0x0801100F"
55 }
56 },
57 "TLX_CFG_0": {
58 "instances": {
59 "0": "0x0801200C"
60 }
61 },
62 "TLX_CFG_1": {
63 "instances": {
64 "0": "0x0801200D"
65 }
66 },
67 "TLX_CFG_2": {
68 "instances": {
69 "0": "0x0801200E"
70 }
71 },
72 "TLX_CFG_3": {
73 "instances": {
74 "0": "0x0801200F"
75 }
76 },
77 "TLX_ERR_RPT_0": {
78 "instances": {
79 "0": "0x0801201C"
80 }
81 },
82 "TLX_ERR_RPT_1": {
83 "instances": {
84 "0": "0x0801201D"
85 }
86 },
87 "TLX_ERR_RPT_2": {
88 "instances": {
89 "0": "0x0801201E"
90 }
91 }
92 },
93 "isolation_nodes": {
94 "TLX_FIR": {
95 "instances": [0],
96 "rules": [
97 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]98 "attn_type": ["CHIP_CS"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]99 "node_inst": [0],
100 "expr": {
101 "expr_type": "and",
102 "exprs": [
103 {
104 "expr_type": "reg",
105 "reg_name": "TLX_FIR"
106 },
107 {
108 "expr_type": "not",
109 "expr": {
110 "expr_type": "reg",
111 "reg_name": "TLX_FIR_MASK"
112 }
113 },
114 {
115 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]116 "reg_name": "TLX_FIR_CFG_CHIP_CS"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]117 }
118 ]
119 }
120 },
121 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]122 "attn_type": ["RECOV"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]123 "node_inst": [0],
124 "expr": {
125 "expr_type": "and",
126 "exprs": [
127 {
128 "expr_type": "reg",
129 "reg_name": "TLX_FIR"
130 },
131 {
132 "expr_type": "not",
133 "expr": {
134 "expr_type": "reg",
135 "reg_name": "TLX_FIR_MASK"
136 }
137 },
138 {
139 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]140 "reg_name": "TLX_FIR_CFG_RECOV"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]141 }
142 ]
143 }
144 },
145 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]146 "attn_type": ["SP_ATTN"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]147 "node_inst": [0],
148 "expr": {
149 "expr_type": "and",
150 "exprs": [
151 {
152 "expr_type": "reg",
153 "reg_name": "TLX_FIR"
154 },
155 {
156 "expr_type": "not",
157 "expr": {
158 "expr_type": "reg",
159 "reg_name": "TLX_FIR_MASK"
160 }
161 },
162 {
163 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]164 "reg_name": "TLX_FIR_CFG_SP_ATTN"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]165 }
166 ]
167 }
168 },
169 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]170 "attn_type": ["UNIT_CS"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]171 "node_inst": [0],
172 "expr": {
173 "expr_type": "and",
174 "exprs": [
175 {
176 "expr_type": "reg",
177 "reg_name": "TLX_FIR"
178 },
179 {
180 "expr_type": "not",
181 "expr": {
182 "expr_type": "reg",
183 "reg_name": "TLX_FIR_MASK"
184 }
185 },
186 {
187 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]188 "reg_name": "TLX_FIR_CFG_UNIT_CS"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]189 }
190 ]
191 }
192 }
193 ],
Caleb Palmer94ea8ed2024-07-25 14:26:46 -0500[diff] [blame]194 "op_rules": {
195 "FIR_SET": {
196 "op_rule": "atomic_or",
197 "reg_name": "TLX_FIR_OR"
198 },
199 "FIR_CLEAR": {
200 "op_rule": "atomic_or",
201 "reg_name": "TLX_FIR"
202 },
203 "MASK_SET": {
204 "op_rule": "atomic_or",
205 "reg_name": "TLX_FIR_MASK_OR"
206 },
207 "MASK_CLEAR": {
208 "op_rule": "atomic_or",
209 "reg_name": "TLX_FIR_MASK"
210 }
211 },
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]212 "bits": {
213 "0": {
214 "desc": "Internal parity error"
215 },
216 "1": {
217 "desc": "TLXT control register parity error"
218 },
219 "2": {
220 "desc": "TLX VC0 return credit overflow"
221 },
222 "3": {
223 "desc": "TLX VC3 return credit overflow"
224 },
225 "4": {
226 "desc": "TLX DCP0 return credit overflow"
227 },
228 "5": {
229 "desc": "TLX DCP3 return credit overflow"
230 },
231 "6": {
232 "desc": "TLXC error"
233 },
234 "7": {
235 "desc": "TLXC parity error"
236 },
237 "8": {
238 "desc": "TLXT config parity error"
239 },
240 "9": {
241 "desc": "TLXT response parity error"
242 },
243 "10": {
244 "desc": "TLXT framer control parity error"
245 },
246 "11": {
247 "desc": "TLXT Xarb control error"
248 },
249 "12": {
250 "desc": "TLXT DLX interface error"
251 },
252 "13": {
253 "desc": "TLX info register parity error"
254 },
255 "14": {
256 "desc": "TLX reorder queue error"
257 },
258 "15": {
259 "desc": "TLXT invalid configuration"
260 },
261 "16": {
262 "desc": "TLXR is dropping commands after a fatal error"
263 },
264 "17": {
265 "desc": "Malformed OC packet received"
266 },
267 "18": {
268 "desc": "Protocol error detected in OC downstream sequence"
269 },
270 "19": {
271 "desc": "Legal OC command not supported"
272 },
273 "20": {
274 "desc": "Legal OC command length not supported"
275 },
276 "21": {
277 "desc": "TLXR OC Misaligned"
278 },
279 "22": {
280 "desc": "MMIO returned non-zero response to a write"
281 },
282 "23": {
283 "desc": "Hardware error in TLXR control logic"
284 },
285 "24": {
286 "desc": "TLXR Info Event"
287 },
288 "25": {
289 "desc": "TLXR detected internal error"
290 },
291 "26": {
292 "desc": "TLXR Threshold errors"
293 },
294 "27": {
295 "desc": "Trace_Stop from TLXR"
296 }
297 },
298 "capture_groups": [
299 {
300 "group_name": "TLX_FIR",
301 "group_inst": {
302 "0": 0
303 }
304 }
305 ]
306 }
307 },
308 "capture_groups": {
309 "TLX_FIR": [
310 {
311 "reg_name": "SRQ_ROQ_CTL_0",
312 "reg_inst": {
313 "0": 0
314 }
315 },
316 {
317 "reg_name": "TLX_CFG_0",
318 "reg_inst": {
319 "0": 0
320 }
321 },
322 {
323 "reg_name": "TLX_CFG_1",
324 "reg_inst": {
325 "0": 0
326 }
327 },
328 {
329 "reg_name": "TLX_CFG_2",
330 "reg_inst": {
331 "0": 0
332 }
333 },
334 {
335 "reg_name": "TLX_CFG_3",
336 "reg_inst": {
337 "0": 0
338 }
339 },
340 {
341 "reg_name": "TLX_ERR_RPT_0",
342 "reg_inst": {
343 "0": 0
344 }
345 },
346 {
347 "reg_name": "TLX_ERR_RPT_1",
348 "reg_inst": {
349 "0": 0
350 }
351 },
352 {
353 "reg_name": "TLX_ERR_RPT_2",
354 "reg_inst": {
355 "0": 0
356 }
357 }
358 ]
359 }
360}