| Zane Shelley | b9ea93c | 2023-03-10 10:41:41 -0600 | [diff] [blame] | 1 | { |
| 2 | "version": 1, |
| 3 | "model_ec": ["ODYSSEY_10"], |
| 4 | "registers": { |
| 5 | "ODP_FIR": { |
| 6 | "instances": { |
| 7 | "0": "0x08013000", |
| 8 | "1": "0x08013400" |
| 9 | } |
| 10 | }, |
| 11 | "ODP_FIR_MASK": { |
| 12 | "instances": { |
| 13 | "0": "0x08013002", |
| 14 | "1": "0x08013402" |
| 15 | } |
| 16 | }, |
| 17 | "ODP_FIR_CFG_XSTOP": { |
| 18 | "instances": { |
| 19 | "0": "0x08013004", |
| 20 | "1": "0x08013404" |
| 21 | } |
| 22 | }, |
| 23 | "ODP_FIR_CFG_RECOV": { |
| 24 | "instances": { |
| 25 | "0": "0x08013005", |
| 26 | "1": "0x08013405" |
| 27 | } |
| 28 | }, |
| 29 | "ODP_FIR_CFG_ATTN": { |
| 30 | "instances": { |
| 31 | "0": "0x08013006", |
| 32 | "1": "0x08013406" |
| 33 | } |
| 34 | }, |
| 35 | "ODP_FIR_CFG_LXSTOP": { |
| 36 | "instances": { |
| 37 | "0": "0x08013007", |
| 38 | "1": "0x08013407" |
| 39 | } |
| 40 | }, |
| 41 | "ODP_FIR_WOF": { |
| 42 | "instances": { |
| 43 | "0": "0x08013008", |
| 44 | "1": "0x08013408" |
| 45 | } |
| 46 | } |
| 47 | }, |
| 48 | "isolation_nodes": { |
| 49 | "ODP_FIR": { |
| 50 | "instances": [0, 1], |
| 51 | "rules": [ |
| 52 | { |
| 53 | "attn_type": ["CS"], |
| 54 | "node_inst": [0, 1], |
| 55 | "expr": { |
| 56 | "expr_type": "and", |
| 57 | "exprs": [ |
| 58 | { |
| 59 | "expr_type": "reg", |
| 60 | "reg_name": "ODP_FIR" |
| 61 | }, |
| 62 | { |
| 63 | "expr_type": "not", |
| 64 | "expr": { |
| 65 | "expr_type": "reg", |
| 66 | "reg_name": "ODP_FIR_MASK" |
| 67 | } |
| 68 | }, |
| 69 | { |
| 70 | "expr_type": "reg", |
| 71 | "reg_name": "ODP_FIR_CFG_XSTOP" |
| 72 | } |
| 73 | ] |
| 74 | } |
| 75 | }, |
| 76 | { |
| 77 | "attn_type": ["RE"], |
| 78 | "node_inst": [0, 1], |
| 79 | "expr": { |
| 80 | "expr_type": "and", |
| 81 | "exprs": [ |
| 82 | { |
| 83 | "expr_type": "reg", |
| 84 | "reg_name": "ODP_FIR" |
| 85 | }, |
| 86 | { |
| 87 | "expr_type": "not", |
| 88 | "expr": { |
| 89 | "expr_type": "reg", |
| 90 | "reg_name": "ODP_FIR_MASK" |
| 91 | } |
| 92 | }, |
| 93 | { |
| 94 | "expr_type": "reg", |
| 95 | "reg_name": "ODP_FIR_CFG_RECOV" |
| 96 | } |
| 97 | ] |
| 98 | } |
| 99 | }, |
| 100 | { |
| 101 | "attn_type": ["SPA"], |
| 102 | "node_inst": [0, 1], |
| 103 | "expr": { |
| 104 | "expr_type": "and", |
| 105 | "exprs": [ |
| 106 | { |
| 107 | "expr_type": "reg", |
| 108 | "reg_name": "ODP_FIR" |
| 109 | }, |
| 110 | { |
| 111 | "expr_type": "not", |
| 112 | "expr": { |
| 113 | "expr_type": "reg", |
| 114 | "reg_name": "ODP_FIR_MASK" |
| 115 | } |
| 116 | }, |
| 117 | { |
| 118 | "expr_type": "reg", |
| 119 | "reg_name": "ODP_FIR_CFG_ATTN" |
| 120 | } |
| 121 | ] |
| 122 | } |
| 123 | }, |
| 124 | { |
| 125 | "attn_type": ["UCS"], |
| 126 | "node_inst": [0, 1], |
| 127 | "expr": { |
| 128 | "expr_type": "and", |
| 129 | "exprs": [ |
| 130 | { |
| 131 | "expr_type": "reg", |
| 132 | "reg_name": "ODP_FIR" |
| 133 | }, |
| 134 | { |
| 135 | "expr_type": "not", |
| 136 | "expr": { |
| 137 | "expr_type": "reg", |
| 138 | "reg_name": "ODP_FIR_MASK" |
| 139 | } |
| 140 | }, |
| 141 | { |
| 142 | "expr_type": "reg", |
| 143 | "reg_name": "ODP_FIR_CFG_LXSTOP" |
| 144 | } |
| 145 | ] |
| 146 | } |
| 147 | } |
| 148 | ], |
| 149 | "bits": { |
| 150 | "0": { |
| 151 | "desc": "Internal parity error" |
| 152 | }, |
| 153 | "1": { |
| 154 | "desc": "SCOM2APB state machine parity error" |
| 155 | }, |
| 156 | "2": { |
| 157 | "desc": "Write data parity error" |
| 158 | }, |
| 159 | "3": { |
| 160 | "desc": "APB responder error" |
| 161 | }, |
| 162 | "4": { |
| 163 | "desc": "ODPCTRL register parity error" |
| 164 | }, |
| 165 | "5": { |
| 166 | "desc": "PHY error" |
| 167 | }, |
| 168 | "6": { |
| 169 | "desc": "PHY Sticky Unlock Error" |
| 170 | }, |
| 171 | "7": { |
| 172 | "desc": "Bsi Interrupt occurred" |
| 173 | }, |
| 174 | "8": { |
| 175 | "desc": "ANIB Receive Error" |
| 176 | }, |
| 177 | "9": { |
| 178 | "desc": "Parity Error (even parity) for D5ACSM Channel 1 Parity Error" |
| 179 | }, |
| 180 | "10": { |
| 181 | "desc": "Parity Error (even parity) for D5ACSM Channel 0 Parity Error" |
| 182 | }, |
| 183 | "11": { |
| 184 | "desc": "PHY RX FIFO Check Error" |
| 185 | }, |
| 186 | "12": { |
| 187 | "desc": "PHY RX TX PPT Error" |
| 188 | }, |
| 189 | "13": { |
| 190 | "desc": "PHY ECC Error ARC ECC Interrupt" |
| 191 | }, |
| 192 | "14:18": { |
| 193 | "desc": "Reserved Firmware Interrupt" |
| 194 | }, |
| 195 | "19": { |
| 196 | "desc": "PHY Training Failure Interrupt" |
| 197 | }, |
| 198 | "20": { |
| 199 | "desc": "PHY Initialization Complete Interrupt" |
| 200 | }, |
| 201 | "21": { |
| 202 | "desc": "PHY Training Complete Interrupt" |
| 203 | } |
| 204 | } |
| 205 | } |
| 206 | } |
| 207 | } |