| Zane Shelley | b9ea93c | 2023-03-10 10:41:41 -0600 | [diff] [blame] | 1 | { |
| 2 | "version": 1, |
| 3 | "model_ec": ["ODYSSEY_10"], |
| 4 | "registers": { |
| 5 | "TLX_FIR": { |
| 6 | "instances": { |
| 7 | "0": "0x08012000" |
| 8 | } |
| 9 | }, |
| 10 | "TLX_FIR_MASK": { |
| 11 | "instances": { |
| 12 | "0": "0x08012002" |
| 13 | } |
| 14 | }, |
| 15 | "TLX_FIR_CFG_XSTOP": { |
| 16 | "instances": { |
| 17 | "0": "0x08012004" |
| 18 | } |
| 19 | }, |
| 20 | "TLX_FIR_CFG_RECOV": { |
| 21 | "instances": { |
| 22 | "0": "0x08012005" |
| 23 | } |
| 24 | }, |
| 25 | "TLX_FIR_CFG_ATTN": { |
| 26 | "instances": { |
| 27 | "0": "0x08012006" |
| 28 | } |
| 29 | }, |
| 30 | "TLX_FIR_CFG_LXSTOP": { |
| 31 | "instances": { |
| 32 | "0": "0x08012007" |
| 33 | } |
| 34 | }, |
| 35 | "TLX_FIR_WOF": { |
| 36 | "instances": { |
| 37 | "0": "0x08012008" |
| 38 | } |
| 39 | }, |
| 40 | "SRQ_ROQ_CTL_0": { |
| 41 | "instances": { |
| 42 | "0": "0x0801100F" |
| 43 | } |
| 44 | }, |
| 45 | "TLX_CFG_0": { |
| 46 | "instances": { |
| 47 | "0": "0x0801200C" |
| 48 | } |
| 49 | }, |
| 50 | "TLX_CFG_1": { |
| 51 | "instances": { |
| 52 | "0": "0x0801200D" |
| 53 | } |
| 54 | }, |
| 55 | "TLX_CFG_2": { |
| 56 | "instances": { |
| 57 | "0": "0x0801200E" |
| 58 | } |
| 59 | }, |
| 60 | "TLX_CFG_3": { |
| 61 | "instances": { |
| 62 | "0": "0x0801200F" |
| 63 | } |
| 64 | }, |
| 65 | "TLX_ERR_RPT_0": { |
| 66 | "instances": { |
| 67 | "0": "0x0801201C" |
| 68 | } |
| 69 | }, |
| 70 | "TLX_ERR_RPT_1": { |
| 71 | "instances": { |
| 72 | "0": "0x0801201D" |
| 73 | } |
| 74 | }, |
| 75 | "TLX_ERR_RPT_2": { |
| 76 | "instances": { |
| 77 | "0": "0x0801201E" |
| 78 | } |
| 79 | } |
| 80 | }, |
| 81 | "isolation_nodes": { |
| 82 | "TLX_FIR": { |
| 83 | "instances": [0], |
| 84 | "rules": [ |
| 85 | { |
| 86 | "attn_type": ["CS"], |
| 87 | "node_inst": [0], |
| 88 | "expr": { |
| 89 | "expr_type": "and", |
| 90 | "exprs": [ |
| 91 | { |
| 92 | "expr_type": "reg", |
| 93 | "reg_name": "TLX_FIR" |
| 94 | }, |
| 95 | { |
| 96 | "expr_type": "not", |
| 97 | "expr": { |
| 98 | "expr_type": "reg", |
| 99 | "reg_name": "TLX_FIR_MASK" |
| 100 | } |
| 101 | }, |
| 102 | { |
| 103 | "expr_type": "reg", |
| 104 | "reg_name": "TLX_FIR_CFG_XSTOP" |
| 105 | } |
| 106 | ] |
| 107 | } |
| 108 | }, |
| 109 | { |
| 110 | "attn_type": ["RE"], |
| 111 | "node_inst": [0], |
| 112 | "expr": { |
| 113 | "expr_type": "and", |
| 114 | "exprs": [ |
| 115 | { |
| 116 | "expr_type": "reg", |
| 117 | "reg_name": "TLX_FIR" |
| 118 | }, |
| 119 | { |
| 120 | "expr_type": "not", |
| 121 | "expr": { |
| 122 | "expr_type": "reg", |
| 123 | "reg_name": "TLX_FIR_MASK" |
| 124 | } |
| 125 | }, |
| 126 | { |
| 127 | "expr_type": "reg", |
| 128 | "reg_name": "TLX_FIR_CFG_RECOV" |
| 129 | } |
| 130 | ] |
| 131 | } |
| 132 | }, |
| 133 | { |
| 134 | "attn_type": ["SPA"], |
| 135 | "node_inst": [0], |
| 136 | "expr": { |
| 137 | "expr_type": "and", |
| 138 | "exprs": [ |
| 139 | { |
| 140 | "expr_type": "reg", |
| 141 | "reg_name": "TLX_FIR" |
| 142 | }, |
| 143 | { |
| 144 | "expr_type": "not", |
| 145 | "expr": { |
| 146 | "expr_type": "reg", |
| 147 | "reg_name": "TLX_FIR_MASK" |
| 148 | } |
| 149 | }, |
| 150 | { |
| 151 | "expr_type": "reg", |
| 152 | "reg_name": "TLX_FIR_CFG_ATTN" |
| 153 | } |
| 154 | ] |
| 155 | } |
| 156 | }, |
| 157 | { |
| 158 | "attn_type": ["UCS"], |
| 159 | "node_inst": [0], |
| 160 | "expr": { |
| 161 | "expr_type": "and", |
| 162 | "exprs": [ |
| 163 | { |
| 164 | "expr_type": "reg", |
| 165 | "reg_name": "TLX_FIR" |
| 166 | }, |
| 167 | { |
| 168 | "expr_type": "not", |
| 169 | "expr": { |
| 170 | "expr_type": "reg", |
| 171 | "reg_name": "TLX_FIR_MASK" |
| 172 | } |
| 173 | }, |
| 174 | { |
| 175 | "expr_type": "reg", |
| 176 | "reg_name": "TLX_FIR_CFG_LXSTOP" |
| 177 | } |
| 178 | ] |
| 179 | } |
| 180 | } |
| 181 | ], |
| 182 | "bits": { |
| 183 | "0": { |
| 184 | "desc": "Internal parity error" |
| 185 | }, |
| 186 | "1": { |
| 187 | "desc": "TLXT control register parity error" |
| 188 | }, |
| 189 | "2": { |
| 190 | "desc": "TLX VC0 return credit overflow" |
| 191 | }, |
| 192 | "3": { |
| 193 | "desc": "TLX VC3 return credit overflow" |
| 194 | }, |
| 195 | "4": { |
| 196 | "desc": "TLX DCP0 return credit overflow" |
| 197 | }, |
| 198 | "5": { |
| 199 | "desc": "TLX DCP3 return credit overflow" |
| 200 | }, |
| 201 | "6": { |
| 202 | "desc": "TLXC error" |
| 203 | }, |
| 204 | "7": { |
| 205 | "desc": "TLXC parity error" |
| 206 | }, |
| 207 | "8": { |
| 208 | "desc": "TLXT config parity error" |
| 209 | }, |
| 210 | "9": { |
| 211 | "desc": "TLXT response parity error" |
| 212 | }, |
| 213 | "10": { |
| 214 | "desc": "TLXT framer control parity error" |
| 215 | }, |
| 216 | "11": { |
| 217 | "desc": "TLXT Xarb control error" |
| 218 | }, |
| 219 | "12": { |
| 220 | "desc": "TLXT DLX interface error" |
| 221 | }, |
| 222 | "13": { |
| 223 | "desc": "TLX info register parity error" |
| 224 | }, |
| 225 | "14": { |
| 226 | "desc": "TLX reorder queue error" |
| 227 | }, |
| 228 | "15": { |
| 229 | "desc": "TLXT invalid configuration" |
| 230 | }, |
| 231 | "16": { |
| 232 | "desc": "TLXR is dropping commands after a fatal error" |
| 233 | }, |
| 234 | "17": { |
| 235 | "desc": "Malformed OC packet received" |
| 236 | }, |
| 237 | "18": { |
| 238 | "desc": "Protocol error detected in OC downstream sequence" |
| 239 | }, |
| 240 | "19": { |
| 241 | "desc": "Legal OC command not supported" |
| 242 | }, |
| 243 | "20": { |
| 244 | "desc": "Legal OC command length not supported" |
| 245 | }, |
| 246 | "21": { |
| 247 | "desc": "TLXR OC Misaligned" |
| 248 | }, |
| 249 | "22": { |
| 250 | "desc": "MMIO returned non-zero response to a write" |
| 251 | }, |
| 252 | "23": { |
| 253 | "desc": "Hardware error in TLXR control logic" |
| 254 | }, |
| 255 | "24": { |
| 256 | "desc": "TLXR Info Event" |
| 257 | }, |
| 258 | "25": { |
| 259 | "desc": "TLXR detected internal error" |
| 260 | }, |
| 261 | "26": { |
| 262 | "desc": "TLXR Threshold errors" |
| 263 | }, |
| 264 | "27": { |
| 265 | "desc": "Trace_Stop from TLXR" |
| 266 | } |
| 267 | }, |
| 268 | "capture_groups": [ |
| 269 | { |
| 270 | "group_name": "TLX_FIR", |
| 271 | "group_inst": { |
| 272 | "0": 0 |
| 273 | } |
| 274 | } |
| 275 | ] |
| 276 | } |
| 277 | }, |
| 278 | "capture_groups": { |
| 279 | "TLX_FIR": [ |
| 280 | { |
| 281 | "reg_name": "SRQ_ROQ_CTL_0", |
| 282 | "reg_inst": { |
| 283 | "0": 0 |
| 284 | } |
| 285 | }, |
| 286 | { |
| 287 | "reg_name": "TLX_CFG_0", |
| 288 | "reg_inst": { |
| 289 | "0": 0 |
| 290 | } |
| 291 | }, |
| 292 | { |
| 293 | "reg_name": "TLX_CFG_1", |
| 294 | "reg_inst": { |
| 295 | "0": 0 |
| 296 | } |
| 297 | }, |
| 298 | { |
| 299 | "reg_name": "TLX_CFG_2", |
| 300 | "reg_inst": { |
| 301 | "0": 0 |
| 302 | } |
| 303 | }, |
| 304 | { |
| 305 | "reg_name": "TLX_CFG_3", |
| 306 | "reg_inst": { |
| 307 | "0": 0 |
| 308 | } |
| 309 | }, |
| 310 | { |
| 311 | "reg_name": "TLX_ERR_RPT_0", |
| 312 | "reg_inst": { |
| 313 | "0": 0 |
| 314 | } |
| 315 | }, |
| 316 | { |
| 317 | "reg_name": "TLX_ERR_RPT_1", |
| 318 | "reg_inst": { |
| 319 | "0": 0 |
| 320 | } |
| 321 | }, |
| 322 | { |
| 323 | "reg_name": "TLX_ERR_RPT_2", |
| 324 | "reg_inst": { |
| 325 | "0": 0 |
| 326 | } |
| 327 | } |
| 328 | ] |
| 329 | } |
| 330 | } |