Zane Shelley | b9ea93c | 2023-03-10 10:41:41 -0600 | [diff] [blame] | 1 | { |
| 2 | "version": 1, |
| 3 | "model_ec": ["P10_20"], |
| 4 | "registers": { |
| 5 | "PAU_FIR_1": { |
| 6 | "instances": { |
| 7 | "0": "0x10010C40", |
| 8 | "3": "0x11010C40", |
| 9 | "4": "0x12010C40", |
| 10 | "5": "0x12011440", |
| 11 | "6": "0x13010C40", |
| 12 | "7": "0x13011440" |
| 13 | } |
| 14 | }, |
| 15 | "PAU_FIR_1_MASK": { |
| 16 | "instances": { |
| 17 | "0": "0x10010C43", |
| 18 | "3": "0x11010C43", |
| 19 | "4": "0x12010C43", |
| 20 | "5": "0x12011443", |
| 21 | "6": "0x13010C43", |
| 22 | "7": "0x13011443" |
| 23 | } |
| 24 | }, |
| 25 | "PAU_FIR_1_ACT0": { |
| 26 | "instances": { |
| 27 | "0": "0x10010C46", |
| 28 | "3": "0x11010C46", |
| 29 | "4": "0x12010C46", |
| 30 | "5": "0x12011446", |
| 31 | "6": "0x13010C46", |
| 32 | "7": "0x13011446" |
| 33 | } |
| 34 | }, |
| 35 | "PAU_FIR_1_ACT1": { |
| 36 | "instances": { |
| 37 | "0": "0x10010C47", |
| 38 | "3": "0x11010C47", |
| 39 | "4": "0x12010C47", |
| 40 | "5": "0x12011447", |
| 41 | "6": "0x13010C47", |
| 42 | "7": "0x13011447" |
| 43 | } |
| 44 | } |
| 45 | }, |
| 46 | "isolation_nodes": { |
| 47 | "PAU_FIR_1": { |
| 48 | "instances": [0, 3, 4, 5, 6, 7], |
| 49 | "rules": [ |
| 50 | { |
| 51 | "attn_type": ["CS"], |
| 52 | "node_inst": [0, 3, 4, 5, 6, 7], |
| 53 | "expr": { |
| 54 | "expr_type": "and", |
| 55 | "exprs": [ |
| 56 | { |
| 57 | "expr_type": "reg", |
| 58 | "reg_name": "PAU_FIR_1" |
| 59 | }, |
| 60 | { |
| 61 | "expr_type": "not", |
| 62 | "expr": { |
| 63 | "expr_type": "reg", |
| 64 | "reg_name": "PAU_FIR_1_MASK" |
| 65 | } |
| 66 | }, |
| 67 | { |
| 68 | "expr_type": "not", |
| 69 | "expr": { |
| 70 | "expr_type": "reg", |
| 71 | "reg_name": "PAU_FIR_1_ACT0" |
| 72 | } |
| 73 | }, |
| 74 | { |
| 75 | "expr_type": "not", |
| 76 | "expr": { |
| 77 | "expr_type": "reg", |
| 78 | "reg_name": "PAU_FIR_1_ACT1" |
| 79 | } |
| 80 | } |
| 81 | ] |
| 82 | } |
| 83 | }, |
| 84 | { |
| 85 | "attn_type": ["RE"], |
| 86 | "node_inst": [0, 3, 4, 5, 6, 7], |
| 87 | "expr": { |
| 88 | "expr_type": "and", |
| 89 | "exprs": [ |
| 90 | { |
| 91 | "expr_type": "reg", |
| 92 | "reg_name": "PAU_FIR_1" |
| 93 | }, |
| 94 | { |
| 95 | "expr_type": "not", |
| 96 | "expr": { |
| 97 | "expr_type": "reg", |
| 98 | "reg_name": "PAU_FIR_1_MASK" |
| 99 | } |
| 100 | }, |
| 101 | { |
| 102 | "expr_type": "not", |
| 103 | "expr": { |
| 104 | "expr_type": "reg", |
| 105 | "reg_name": "PAU_FIR_1_ACT0" |
| 106 | } |
| 107 | }, |
| 108 | { |
| 109 | "expr_type": "reg", |
| 110 | "reg_name": "PAU_FIR_1_ACT1" |
| 111 | } |
| 112 | ] |
| 113 | } |
| 114 | }, |
| 115 | { |
| 116 | "attn_type": ["UCS"], |
| 117 | "node_inst": [0, 3, 4, 5, 6, 7], |
| 118 | "expr": { |
| 119 | "expr_type": "and", |
| 120 | "exprs": [ |
| 121 | { |
| 122 | "expr_type": "reg", |
| 123 | "reg_name": "PAU_FIR_1" |
| 124 | }, |
| 125 | { |
| 126 | "expr_type": "not", |
| 127 | "expr": { |
| 128 | "expr_type": "reg", |
| 129 | "reg_name": "PAU_FIR_1_MASK" |
| 130 | } |
| 131 | }, |
| 132 | { |
| 133 | "expr_type": "reg", |
| 134 | "reg_name": "PAU_FIR_1_ACT0" |
| 135 | }, |
| 136 | { |
| 137 | "expr_type": "reg", |
| 138 | "reg_name": "PAU_FIR_1_ACT1" |
| 139 | } |
| 140 | ] |
| 141 | } |
| 142 | } |
| 143 | ], |
| 144 | "bits": { |
| 145 | "0": { |
| 146 | "desc": "NDL Brick0 stall" |
| 147 | }, |
| 148 | "1": { |
| 149 | "desc": "NDL Brick0 nostall" |
| 150 | }, |
| 151 | "2": { |
| 152 | "desc": "NDL Brick1 stall" |
| 153 | }, |
| 154 | "3": { |
| 155 | "desc": "NDL Brick1 nostall" |
| 156 | }, |
| 157 | "4": { |
| 158 | "desc": "NDL Brick2 stall" |
| 159 | }, |
| 160 | "5": { |
| 161 | "desc": "NDL Brick2 nostall" |
| 162 | }, |
| 163 | "6": { |
| 164 | "desc": "NDL Brick3 stall" |
| 165 | }, |
| 166 | "7": { |
| 167 | "desc": "NDL Brick3 nostall" |
| 168 | }, |
| 169 | "8": { |
| 170 | "desc": "NDL Brick4 stall" |
| 171 | }, |
| 172 | "9": { |
| 173 | "desc": "NDL Brick4 nostall" |
| 174 | }, |
| 175 | "10": { |
| 176 | "desc": "NDL Brick5 stall" |
| 177 | }, |
| 178 | "11": { |
| 179 | "desc": "NDL Brick5 nostall" |
| 180 | }, |
| 181 | "12": { |
| 182 | "desc": "MISC Register ring error" |
| 183 | }, |
| 184 | "13": { |
| 185 | "desc": "MISC Parity error from interrupt base real address register" |
| 186 | }, |
| 187 | "14": { |
| 188 | "desc": "MISC Parity error on Indirect SCOM Address register" |
| 189 | }, |
| 190 | "15": { |
| 191 | "desc": "MISC Parity error on MISC Control register" |
| 192 | }, |
| 193 | "16": { |
| 194 | "desc": "FIR1 Reserved, bit 16" |
| 195 | }, |
| 196 | "17": { |
| 197 | "desc": "ATS Invalid TVT entry" |
| 198 | }, |
| 199 | "18": { |
| 200 | "desc": "ATS TVT Address range error" |
| 201 | }, |
| 202 | "19": { |
| 203 | "desc": "ATS TCE Page access error during TCE cache lookup" |
| 204 | }, |
| 205 | "20": { |
| 206 | "desc": "ATS Effective Address hit multiple TCE cache entries" |
| 207 | }, |
| 208 | "21": { |
| 209 | "desc": "ATS TCE Page access error during TCE table-walk" |
| 210 | }, |
| 211 | "22": { |
| 212 | "desc": "ATS Timeout on TCE tree walk" |
| 213 | }, |
| 214 | "23": { |
| 215 | "desc": "ATS Parity error on TCE cache directory array" |
| 216 | }, |
| 217 | "24": { |
| 218 | "desc": "ATS Parity error on TCE cache data array" |
| 219 | }, |
| 220 | "25": { |
| 221 | "desc": "ATS ECC UE on Effective Address array" |
| 222 | }, |
| 223 | "26": { |
| 224 | "desc": "ATS ECC CE on Effective Address array" |
| 225 | }, |
| 226 | "27": { |
| 227 | "desc": "ATS ECC UE on TDRmem array" |
| 228 | }, |
| 229 | "28": { |
| 230 | "desc": "ATS ECC CE on TDRmem array" |
| 231 | }, |
| 232 | "29": { |
| 233 | "desc": "ATS ECC UE on CQ CTL DMA Read data to TDR_mem array during table-walk" |
| 234 | }, |
| 235 | "30": { |
| 236 | "desc": "ATS ECC CE on CQ CTL DMA Read data to TDR_mem array during table-walk" |
| 237 | }, |
| 238 | "31": { |
| 239 | "desc": "ATS Parity error on TVT entry" |
| 240 | }, |
| 241 | "32": { |
| 242 | "desc": "ATS Parity error on IODA Address Register" |
| 243 | }, |
| 244 | "33": { |
| 245 | "desc": "ATS Parity error on ATS Control Register" |
| 246 | }, |
| 247 | "34": { |
| 248 | "desc": "ATS Parity error on ATS Timeout Control register" |
| 249 | }, |
| 250 | "35": { |
| 251 | "desc": "ATS Invalid IODA Table Address Register Table Select entry" |
| 252 | }, |
| 253 | "36": { |
| 254 | "desc": "ATS Reserved, macro bit 19" |
| 255 | }, |
| 256 | "37": { |
| 257 | "desc": "kill xlate epoch timeout." |
| 258 | }, |
| 259 | "38": { |
| 260 | "desc": "XSL Reserved, macro bit 19." |
| 261 | }, |
| 262 | "39": { |
| 263 | "desc": "XSL Reserved, macro bit 20." |
| 264 | }, |
| 265 | "40": { |
| 266 | "desc": "XSL Reserved, macro bit 21." |
| 267 | }, |
| 268 | "41": { |
| 269 | "desc": "XSL Reserved, macro bit 22." |
| 270 | }, |
| 271 | "42": { |
| 272 | "desc": "XSL Reserved, macro bit 23." |
| 273 | }, |
| 274 | "43": { |
| 275 | "desc": "XSL Reserved, macro bit 24." |
| 276 | }, |
| 277 | "44": { |
| 278 | "desc": "XSL Reserved, macro bit 25." |
| 279 | }, |
| 280 | "45": { |
| 281 | "desc": "XSL Reserved, macro bit 26." |
| 282 | }, |
| 283 | "46": { |
| 284 | "desc": "XSL Reserved, macro bit 27." |
| 285 | }, |
| 286 | "47": { |
| 287 | "desc": "NDL Brick6 stall" |
| 288 | }, |
| 289 | "48": { |
| 290 | "desc": "NDL Brick6 nostall" |
| 291 | }, |
| 292 | "49": { |
| 293 | "desc": "NDL Brick7 stall" |
| 294 | }, |
| 295 | "50": { |
| 296 | "desc": "NDL Brick7 nostall" |
| 297 | }, |
| 298 | "51": { |
| 299 | "desc": "NDL Brick8 stall" |
| 300 | }, |
| 301 | "52": { |
| 302 | "desc": "NDL Brick8 nostall" |
| 303 | }, |
| 304 | "53": { |
| 305 | "desc": "NDL Brick9 stall" |
| 306 | }, |
| 307 | "54": { |
| 308 | "desc": "NDL Brick9 nostall" |
| 309 | }, |
| 310 | "55": { |
| 311 | "desc": "NDL Brick10 stall" |
| 312 | }, |
| 313 | "56": { |
| 314 | "desc": "NDL Brick10 nostall" |
| 315 | }, |
| 316 | "57": { |
| 317 | "desc": "NDL Brick11 stall" |
| 318 | }, |
| 319 | "58": { |
| 320 | "desc": "NDL Brick11 nostall" |
| 321 | }, |
| 322 | "59": { |
| 323 | "desc": "AME ECC CE" |
| 324 | }, |
| 325 | "60": { |
| 326 | "desc": "MISC Pervasive SCOM satellite signaled internal FSM error (ring 0, sat 0)" |
| 327 | }, |
| 328 | "61": { |
| 329 | "desc": "MISC Pervasive SCOM satellite signaled internal FSM error (ring 0, sat 1)" |
| 330 | }, |
| 331 | "62": { |
| 332 | "desc": "Unused FIR" |
| 333 | }, |
| 334 | "63": { |
| 335 | "desc": "Unused FIR" |
| 336 | } |
| 337 | } |
| 338 | } |
| 339 | } |
| 340 | } |