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Zane Shelley871adec2019-07-30 11:01:39 -05001#pragma once
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -05002
Zane Shelley52cb1a92019-08-21 14:38:31 -05003#include <hei_includes.hpp>
4#include <register/hei_register.hpp>
5#include <util/hei_bit_string.hpp>
6
Zane Shelley871adec2019-07-30 11:01:39 -05007namespace libhei
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -05008{
9
Zane Shelley61565dc2019-09-18 21:57:10 -050010/**
Zane Shelley8deb0902019-10-14 15:52:27 -050011 * @brief An abstract class containing information (e.g. address, type, length,
12 * etc.) for an actual hardware register.
Zane Shelley61565dc2019-09-18 21:57:10 -050013 *
14 * Hardware access:
15 *
16 * Actual hardware access is defined by the user application via the user
17 * interface APIs. In order to tell the user application which chip to target,
Zane Shelley53efc352019-10-03 21:46:39 -050018 * the user application will give the isolator a list of pointers to its
19 * objects. They will then be passed into the public functions of this class
20 * and eventually given back to the user application when hardware access is
21 * needed.
Zane Shelleyd0af3582019-09-19 10:48:59 -050022 *
23 * Register cache:
24 *
25 * In order to save memory space, each instance of this class does not store
26 * the contents of the target hardware register. Instead, that data is stored
Paul Greenwood6574f6e2019-09-17 09:43:22 -050027 * in a register cache, which is a static variable defined in this class. This
Zane Shelleyd0af3582019-09-19 10:48:59 -050028 * allows us to store only what we need. The cache can also be thought of as a
29 * snapshot of the registers at the time of isolation, which can be useful if
30 * the hardware is still running and register values could change.
31 *
32 * In order to ensure stale data isn't used from the cache, call
33 * HardwareRegister::flushAll() before beginning isolation on a new attention.
34 * Also, HardwareRegister::flushAll() should be called when the isolator is
35 * uninitialized before the rest of the isolation objects are deleted.
Zane Shelley61565dc2019-09-18 21:57:10 -050036 */
Zane Shelleycd36f432019-08-30 21:22:07 -050037class HardwareRegister : public Register
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -050038{
39 public:
40
Zane Shelley8deb0902019-10-14 15:52:27 -050041 /** @brief Pure virtual destructor. */
42 virtual ~HardwareRegister() = 0;
43
44 protected:
45
46 /**
47 * @brief Constructor from components.
48 * @param i_chipType Type of chip associated with this register.
49 * @param i_id Unique ID for this register.
50 * @param i_instance Instance of this register
51 * @param i_accessLevel Hardware access level for this register.
52 */
53 HardwareRegister( ChipType_t i_chipType, RegisterId_t i_id,
54 RegisterInstance_t i_instance,
55 RegisterAccessLevel_t i_accessLevel ) :
56 Register(), iv_chipType( i_chipType ), iv_id( i_id ),
57 iv_instance( i_instance ), iv_accessLevel( i_accessLevel )
58 {}
59
60 private: // Instance variables
61
62 /** The type of chip associated with register. */
63 const ChipType_t iv_chipType;
64
65 /** The unique ID for this register. */
66 const RegisterId_t iv_id;
67
68 /** A register may have multiple instances. All of which will have the same
69 * ID. This variable is used to distinguish between each instance of the
70 * register. */
71 const RegisterInstance_t iv_instance;
72
73 /** The hardware access level of this register (read/write, read-only,
74 * write-only, etc.). */
75 const RegisterAccessLevel_t iv_accessLevel;
76
77 public: // Accessor functions
78
79 /** @return The type of chip associated with this register. */
80 ChipType_t getChipType() const { return iv_chipType; }
81
82 /* @return The unique ID for this register. */
83 RegisterId_t getId() const { return iv_id; }
84
85 /* @return The instance of this register. */
86 RegisterInstance_t getInstance() const { return iv_instance; }
87
88 /** @return The hardware access level of this register. */
89 RegisterAccessLevel_t getAccessLevel() const { return iv_accessLevel; }
90
91 // NOTE: The following are determined by child classes.
92
93 /** @return This register's type. */
94 virtual RegisterType_t getRegisterType() const = 0;
95
96 /** @return The address of this register. */
97 virtual RegisterAddress_t getAddress() const = 0;
98
99 /** @return The size (in bytes) of this register. */
100 virtual size_t getSize() const = 0;
101
102 public:
103
Zane Shelley65ed96a2019-10-14 13:06:11 -0500104 /** Function overloaded from parent Register class. */
Zane Shelley53efc352019-10-03 21:46:39 -0500105 virtual const BitString * getBitString( const Chip & i_chip ) const;
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500106
Zane Shelley65ed96a2019-10-14 13:06:11 -0500107#if 0
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500108 /**
109 * @brief Updates bit string contents associated with register
110 * @param i_bs poiner to bit string
111 * @return Nil
112 */
Paul Greenwood6574f6e2019-09-17 09:43:22 -0500113 virtual void setBitString(const BitString * i_bs) ;
Zane Shelley61565dc2019-09-18 21:57:10 -0500114#endif
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500115
116 /**
Zane Shelley61565dc2019-09-18 21:57:10 -0500117 * @brief Reads a register from hardware via the user interface APIs.
Zane Shelley53efc352019-10-03 21:46:39 -0500118 * @param i_chip The target chip in which this register belongs.
Zane Shelley61565dc2019-09-18 21:57:10 -0500119 * @param i_force When false, this function will only read from hardware if
120 * an entry for this instance does not already exist in the
121 * register cache. When true, the entry in the register
122 * cache is flushed, if it exists. Then this function will
123 * read from hardware and update the cache.
124 * @return See the return code from the registerRead() user interface API.
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500125 */
Zane Shelley53efc352019-10-03 21:46:39 -0500126 ReturnCode read( const Chip & i_chip, bool i_force = false ) const;
Zane Shelley61565dc2019-09-18 21:57:10 -0500127
128 #ifndef __HEI_READ_ONLY
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500129
130 /**
Zane Shelley61565dc2019-09-18 21:57:10 -0500131 * @brief Writes the value stored in the register cache to hardware via the
132 * user interface APIs.
Zane Shelley53efc352019-10-03 21:46:39 -0500133 * @param i_chip The target chip in which this register belongs.
Zane Shelley61565dc2019-09-18 21:57:10 -0500134 * @return See the return code from the registerWrite() user interface API.
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500135 */
Zane Shelley53efc352019-10-03 21:46:39 -0500136 ReturnCode write( const Chip & i_chip ) const;
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500137
Zane Shelley61565dc2019-09-18 21:57:10 -0500138 #endif // __HEI_READ_ONLY
139
140#if 0
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500141 protected: // Functions
142
143 /**
Zane Shelley53efc352019-10-03 21:46:39 -0500144 * @param i_chip The target chip in which this register belongs.
Paul Greenwood6574f6e2019-09-17 09:43:22 -0500145 * @return If iv_operationType indicates a register read is possible
146 * (ACCESS_RO or ACCESS_RW), returns a reference to bit string.
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500147 */
Zane Shelley53efc352019-10-03 21:46:39 -0500148 virtual BitString & accessBitString( const Chip & i_chip );
Zane Shelleyb77b5732019-08-30 22:01:06 -0500149#endif
Zane Shelley61565dc2019-09-18 21:57:10 -0500150
Zane Shelley61565dc2019-09-18 21:57:10 -0500151 private: // Hardware accessor management functions.
152
Zane Shelley53efc352019-10-03 21:46:39 -0500153 /** @brief Asserts this register belongs on the target accessor chip. */
154 void verifyAccessorChip( const Chip & i_chip ) const
Zane Shelley61565dc2019-09-18 21:57:10 -0500155 {
Zane Shelley53efc352019-10-03 21:46:39 -0500156 HEI_ASSERT( getChipType() == i_chip.getType() );
Zane Shelley61565dc2019-09-18 21:57:10 -0500157 }
Zane Shelleyd0af3582019-09-19 10:48:59 -0500158
159 private: // Register cache class variable
160
161 /**
162 * @brief Caches the contents of registers read from hardware.
163 *
164 * The goal is to create a snapshot of the hardware register contents as
165 * close to the reported attention as possible. This snapshot is then used
166 * for additional analysis/debug when needed.
167 */
168 class Cache
169 {
170 public:
171
172 /** @brief Default constructor. */
173 Cache() = default;
174
175 /** @brief Destructor. */
176 ~Cache() = default;
177
178 /** @brief Copy constructor. */
179 Cache( const Cache & ) = delete;
180
181 /** @brief Assignment operator. */
182 Cache & operator=( const Cache & ) = delete;
183
184 /**
185 * @brief Queries if a specific entry exists in the cache.
186 * @param i_chip The target chip.
187 * @param i_hwReg The target register.
188 * @return True if the entry exists, false otherwise.
189 */
190 bool query( const Chip & i_chip,
191 const HardwareRegister * i_hwReg ) const;
192
193 /**
194 * @brief Returns the data buffer for the given chip and register.
195 * @param i_chip The target chip.
196 * @param i_hwReg The target register.
197 * @return A reference to the BitString containing the register data.
198 * @note If an entry does not exist in the cache, an entry will be
199 * created and the BitString will be initialized to 0.
200 */
201 BitString & access( const Chip & i_chip,
202 const HardwareRegister * i_hwReg );
203
204 /** @brief Flushes entire contents from cache. */
205 void flush();
206
207 /**
208 * @brief Removes a single register from the cache.
209 * @param i_chip The target chip.
210 * @param i_hwReg The target register.
211 */
212 void flush( const Chip & i_chip, const HardwareRegister * i_hwReg );
213
214 private:
215
216 /**
217 * @brief Stores a BitStringBuffer for each HardwareRegister per Chip.
218 *
219 * The HardwareRegister keys will just be pointers to the isolation
220 * objects created in the main initialize() API. Those should exist
221 * until the main uninitialize() API is called. It is important that the
222 * cache is flushed at the beginning of the uninitialize() API before
223 * the rest of the isolation objects are deleted.
224 *
225 * The Chip keys are copies of the objects passed to the isolator
226 * because the user application is responsible for storage of the
227 * objects passed to the isolator. We don't want to chance a Chip was
228 * created as a local variable that goes out of scope, or other similar
229 * situations.
230 */
231 std::map<Chip, std::map<const HardwareRegister*, BitString*>> iv_cache;
232 };
233
234 /** This allows all HardwareRegister objects access to the cache. */
235 static Cache cv_cache;
236
237 public: // Register cache management functions.
238
239 /** @brief Flushes the entire register cache. */
240 static void flushAll() { cv_cache.flush(); }
241
Zane Shelley53efc352019-10-03 21:46:39 -0500242 /**
243 * @brief Flushes this register from the cache.
244 * @param i_chip The target chip in which this register belongs.
245 */
246 void flush( const Chip & i_chip ) const
Zane Shelleyd0af3582019-09-19 10:48:59 -0500247 {
Zane Shelley53efc352019-10-03 21:46:39 -0500248 cv_cache.flush( i_chip, this );
Zane Shelleyd0af3582019-09-19 10:48:59 -0500249 }
250
Zane Shelley53efc352019-10-03 21:46:39 -0500251 private: // Register cache management functions.
252
253 /**
254 * @param i_chip The target chip in which this register belongs.
255 * @return True if an entry for this register exist in this cache.
256 */
257 bool queryCache( const Chip & i_chip ) const
Zane Shelleyd0af3582019-09-19 10:48:59 -0500258 {
Zane Shelley53efc352019-10-03 21:46:39 -0500259 return cv_cache.query( i_chip, this );
260 }
261
262 /**
263 * @param i_chip The target chip in which this register belongs.
264 * @return A reference to this register's BitString in cache.
265 */
266 BitString & accessCache( const Chip & i_chip ) const
267 {
268 return cv_cache.access( i_chip, this );
Zane Shelleyd0af3582019-09-19 10:48:59 -0500269 }
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500270};
271
Zane Shelley871adec2019-07-30 11:01:39 -0500272} // end namespace libhei
Zane Shelleyfd3f9cc2019-07-29 15:02:24 -0500273