blob: 4554c54f6522b57ef081933ebe83d9e93be6f3a7 [file] [log] [blame]
Zane Shelleyb9ea93c2023-03-10 10:41:41 -06001{
2 "version": 1,
3 "model_ec": ["ODYSSEY_10"],
4 "isolation_nodes": {
5 "DLX_ERR_RPT": {
6 "instances": [0],
7 "rules": [
8 {
9 "attn_type": ["CS"],
10 "node_inst": [0],
11 "expr": {
12 "expr_type": "and",
13 "exprs": [
14 {
15 "expr_type": "reg",
16 "reg_name": "DLX_ERR_RPT"
17 },
18 {
19 "expr_type": "int",
20 "int_value": "0x0000000000003FFF"
21 }
22 ]
23 }
24 },
25 {
26 "attn_type": ["RE"],
27 "node_inst": [0],
28 "expr": {
29 "expr_type": "and",
30 "exprs": [
31 {
32 "expr_type": "reg",
33 "reg_name": "DLX_ERR_RPT"
34 },
35 {
36 "expr_type": "int",
37 "int_value": "0x0000000000003FFF"
38 }
39 ]
40 }
41 },
42 {
43 "attn_type": ["SPA"],
44 "node_inst": [0],
45 "expr": {
46 "expr_type": "and",
47 "exprs": [
48 {
49 "expr_type": "reg",
50 "reg_name": "DLX_ERR_RPT"
51 },
52 {
53 "expr_type": "int",
54 "int_value": "0x0000000000003FFF"
55 }
56 ]
57 }
58 },
59 {
60 "attn_type": ["UCS"],
61 "node_inst": [0],
62 "expr": {
63 "expr_type": "and",
64 "exprs": [
65 {
66 "expr_type": "reg",
67 "reg_name": "DLX_ERR_RPT"
68 },
69 {
70 "expr_type": "int",
71 "int_value": "0x0000000000003FFF"
72 }
73 ]
74 }
75 }
76 ],
77 "bits": {
78 "50": {
79 "desc": "buffer UE"
80 },
81 "51": {
82 "desc": "insufficient working lanes"
83 },
84 "52": {
85 "desc": "bad CRC from TLXT"
86 },
87 "53": {
88 "desc": "flit hammer"
89 },
90 "54": {
91 "desc": "TX lane reversal"
92 },
93 "55": {
94 "desc": "RX receiving slow A"
95 },
96 "56": {
97 "desc": "RX receiving illegal run length"
98 },
99 "57": {
100 "desc": "control parity error"
101 },
102 "58": {
103 "desc": "scom register parity error"
104 },
105 "59": {
106 "desc": "truncated flit from TL"
107 },
108 "60": {
109 "desc": "illegal run length from TL"
110 },
111 "61": {
112 "desc": "ack pointer overflow"
113 },
114 "62": {
115 "desc": "UE on bus from TLXT"
116 },
117 "63": {
118 "desc": "ECC UE on dword containing run length"
119 }
120 }
121 }
122 }
123}