Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
Zane Shelley | f8a726b | 2020-12-16 21:29:32 -0600 | [diff] [blame] | 2 | <attn_node model_ec="P10_10,P10_20" name="NX_DMA_ENG_FIR" reg_type="SCOM"> |
Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 3 | <local_fir config="W" name="NX_DMA_ENG_FIR"> |
| 4 | <instance addr="0x02011100" reg_inst="0"/> |
| 5 | <action attn_type="CS" config="00"/> |
| 6 | <action attn_type="RE" config="01"/> |
| 7 | <action attn_type="UCS" config="11"/> |
| 8 | </local_fir> |
Zane Shelley | 9afb3f1 | 2021-10-07 16:03:04 -0500 | [diff] [blame] | 9 | <register name="SU_DMA_ERROR_REPORT_0"> |
| 10 | <instance addr="0x02011057" reg_inst="0"/> |
| 11 | </register> |
| 12 | <register name="SU_DMA_ERROR_REPORT_1"> |
| 13 | <instance addr="0x02011058" reg_inst="0"/> |
| 14 | </register> |
| 15 | <capture_group node_inst="0"> |
| 16 | <capture_register reg_inst="0" reg_name="SU_DMA_ERROR_REPORT_0" /> |
| 17 | <capture_register reg_inst="0" reg_name="SU_DMA_ERROR_REPORT_1" /> |
| 18 | </capture_group> |
| 19 | <bit pos="0">DMA hang timer expired</bit> |
| 20 | <bit pos="1">SHM invalid state</bit> |
| 21 | <bit pos="2">reserved</bit> |
| 22 | <bit pos="3">reserved</bit> |
| 23 | <bit pos="4">Channel 0 842 engine ECC CE</bit> |
| 24 | <bit pos="5">Channel 0 842 engine ECC UE</bit> |
| 25 | <bit pos="6">Channel 1 842 engine ECC CE</bit> |
| 26 | <bit pos="7">Channel 1 842 engine ECC UE</bit> |
| 27 | <bit pos="8">DMA Non-zero CSB CC detected</bit> |
| 28 | <bit pos="9">DMA array ECC CE</bit> |
| 29 | <bit pos="10">DMA outbound write/inbound read ECC CE</bit> |
| 30 | <bit pos="11">Channel 4 GZIP ECC CE</bit> |
| 31 | <bit pos="12">Channel 4 GZIP ECC UE</bit> |
| 32 | <bit pos="13">Channel 4 GZIP ECC PE</bit> |
| 33 | <bit pos="14">Error from other SCOM satellites</bit> |
| 34 | <bit pos="15">DMA invalid state error (unrecoverable)</bit> |
| 35 | <bit pos="16">DMA invalid state error (unrecoverable)</bit> |
| 36 | <bit pos="17">DMA array ECC UE</bit> |
| 37 | <bit pos="18">DMA outbound write/inbound read ECC UE</bit> |
| 38 | <bit pos="19">DMA inbound read error</bit> |
| 39 | <bit pos="20">Channel 0 842 invalid state error</bit> |
| 40 | <bit pos="21">Channel 1 842 invalid state error</bit> |
| 41 | <bit pos="22">Channel 2 SYM invalid state error</bit> |
| 42 | <bit pos="23">Channel 3 SYM invalid state error</bit> |
| 43 | <bit pos="24">Channel 4 GZIP invalid state error</bit> |
| 44 | <bit pos="25">reserved</bit> |
| 45 | <bit pos="26">reserved</bit> |
| 46 | <bit pos="27">reserved</bit> |
| 47 | <bit pos="28">reserved</bit> |
| 48 | <bit pos="29">reserved</bit> |
| 49 | <bit pos="30">reserved</bit> |
| 50 | <bit pos="31">UE error on CRB QW0 or QW4</bit> |
| 51 | <bit pos="32">SUE error on CRB QW0 or QW4</bit> |
| 52 | <bit pos="33">SUE error on something other than CRB QW0 or QW4</bit> |
| 53 | <bit pos="34">Channel 0 842 watchdog timer expired</bit> |
| 54 | <bit pos="35">Channel 1 842 watchdog timer expired</bit> |
| 55 | <bit pos="36">Channel 2 SYM watchdog timer expired</bit> |
| 56 | <bit pos="37">Channel 3 SYM watchdog timer expired</bit> |
| 57 | <bit pos="38">Hypervisor local checkstop</bit> |
| 58 | <bit pos="39">Channel 4 Gzip watchdog timer expired</bit> |
| 59 | <bit pos="40">reserved</bit> |
| 60 | <bit pos="41">reserved</bit> |
| 61 | <bit pos="42">reserved</bit> |
| 62 | <bit pos="43">reserved</bit> |
| 63 | <bit pos="44">reserved</bit> |
| 64 | <bit pos="45">reserved</bit> |
| 65 | <bit pos="46">reserved</bit> |
| 66 | <bit pos="47">reserved</bit> |
Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 67 | </attn_node> |