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gerrit.openbmc.org / openbmc / openpower-libhei / 8db65db6333e5b38d1aa19dc94bbca9e5424ffed / . / chip_data / odyssey / node_srq_fir.json
blob: 24e6b310f424936dec7e1c52990997079719a63b [file] [log] [blame]
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]1{
2 "version": 1,
3 "model_ec": ["ODYSSEY_10"],
4 "registers": {
5 "SRQ_FIR": {
6 "instances": {
7 "0": "0x08011000"
8 }
9 },
Caleb Palmer94ea8ed2024-07-25 14:26:46 -0500[diff] [blame]10 "SRQ_FIR_OR": {
11 "access": "WO",
12 "instances": {
13 "0": "0x08011001"
14 }
15 },
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]16 "SRQ_FIR_MASK": {
17 "instances": {
18 "0": "0x08011002"
19 }
20 },
Caleb Palmer94ea8ed2024-07-25 14:26:46 -0500[diff] [blame]21 "SRQ_FIR_MASK_OR": {
22 "access": "WO",
23 "instances": {
24 "0": "0x08011003"
25 }
26 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]27 "SRQ_FIR_CFG_CHIP_CS": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]28 "instances": {
29 "0": "0x08011004"
30 }
31 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]32 "SRQ_FIR_CFG_RECOV": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]33 "instances": {
34 "0": "0x08011005"
35 }
36 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]37 "SRQ_FIR_CFG_SP_ATTN": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]38 "instances": {
39 "0": "0x08011006"
40 }
41 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]42 "SRQ_FIR_CFG_UNIT_CS": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]43 "instances": {
44 "0": "0x08011007"
45 }
46 },
47 "SRQ_FIR_WOF": {
48 "instances": {
49 "0": "0x08011008"
50 }
51 },
52 "SRQ_ERR_RPT": {
53 "instances": {
54 "0": "0x0801101C"
55 }
56 },
57 "MBXLT0": {
58 "instances": {
59 "0": "0x08011012"
60 }
61 },
62 "MBXLT1": {
63 "instances": {
64 "0": "0x08011013"
65 }
66 },
67 "MBXLT2": {
68 "instances": {
69 "0": "0x08011014"
70 }
71 },
72 "MBXLT3": {
73 "instances": {
74 "0": "0x08011021"
75 }
76 },
77 "WESR": {
78 "instances": {
79 "0": "0x08011C06"
80 }
81 },
82 "SRQ_ERR_RPT_HOLD": {
83 "instances": {
84 "0": "0x08011C07"
85 }
86 }
87 },
88 "isolation_nodes": {
89 "SRQ_FIR": {
90 "instances": [0],
91 "rules": [
92 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]93 "attn_type": ["CHIP_CS"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]94 "node_inst": [0],
95 "expr": {
96 "expr_type": "and",
97 "exprs": [
98 {
99 "expr_type": "reg",
100 "reg_name": "SRQ_FIR"
101 },
102 {
103 "expr_type": "not",
104 "expr": {
105 "expr_type": "reg",
106 "reg_name": "SRQ_FIR_MASK"
107 }
108 },
109 {
110 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]111 "reg_name": "SRQ_FIR_CFG_CHIP_CS"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]112 }
113 ]
114 }
115 },
116 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]117 "attn_type": ["RECOV"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]118 "node_inst": [0],
119 "expr": {
120 "expr_type": "and",
121 "exprs": [
122 {
123 "expr_type": "reg",
124 "reg_name": "SRQ_FIR"
125 },
126 {
127 "expr_type": "not",
128 "expr": {
129 "expr_type": "reg",
130 "reg_name": "SRQ_FIR_MASK"
131 }
132 },
133 {
134 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]135 "reg_name": "SRQ_FIR_CFG_RECOV"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]136 }
137 ]
138 }
139 },
140 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]141 "attn_type": ["SP_ATTN"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]142 "node_inst": [0],
143 "expr": {
144 "expr_type": "and",
145 "exprs": [
146 {
147 "expr_type": "reg",
148 "reg_name": "SRQ_FIR"
149 },
150 {
151 "expr_type": "not",
152 "expr": {
153 "expr_type": "reg",
154 "reg_name": "SRQ_FIR_MASK"
155 }
156 },
157 {
158 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]159 "reg_name": "SRQ_FIR_CFG_SP_ATTN"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]160 }
161 ]
162 }
163 },
164 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]165 "attn_type": ["UNIT_CS"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]166 "node_inst": [0],
167 "expr": {
168 "expr_type": "and",
169 "exprs": [
170 {
171 "expr_type": "reg",
172 "reg_name": "SRQ_FIR"
173 },
174 {
175 "expr_type": "not",
176 "expr": {
177 "expr_type": "reg",
178 "reg_name": "SRQ_FIR_MASK"
179 }
180 },
181 {
182 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]183 "reg_name": "SRQ_FIR_CFG_UNIT_CS"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]184 }
185 ]
186 }
187 }
188 ],
Caleb Palmer94ea8ed2024-07-25 14:26:46 -0500[diff] [blame]189 "op_rules": {
190 "FIR_SET": {
191 "op_rule": "atomic_or",
192 "reg_name": "SRQ_FIR_OR"
193 },
194 "FIR_CLEAR": {
195 "op_rule": "atomic_or",
196 "reg_name": "SRQ_FIR"
197 },
198 "MASK_SET": {
199 "op_rule": "atomic_or",
200 "reg_name": "SRQ_FIR_MASK_OR"
201 },
202 "MASK_CLEAR": {
203 "op_rule": "atomic_or",
204 "reg_name": "SRQ_FIR_MASK"
205 }
206 },
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]207 "bits": {
208 "0": {
209 "desc": "Internal parity error"
210 },
211 "1": {
212 "desc": "SRQ nonrecoverable parity error"
213 },
214 "2": {
215 "desc": "refresh overrun port0"
216 },
217 "3": {
218 "desc": "WAT error"
219 },
220 "4": {
221 "desc": "RCD parity error port0"
222 },
223 "5": {
224 "desc": "MCB control logic Error in NCF"
225 },
226 "6": {
227 "desc": "Emergency throttle engaged"
228 },
229 "7": {
230 "desc": "DSM errors port0"
231 },
232 "8": {
233 "desc": "event_n was active on the DDR interface port0"
234 },
235 "9": {
236 "desc": "WRQ or RRQ is in a hung state port0"
237 },
238 "10": {
239 "desc": "state machine one hot error port0"
240 },
241 "11": {
242 "desc": "ROQ errors port0"
243 },
244 "12": {
245 "desc": "Address parity error seen internal to sequencer on read or write command port0"
246 },
247 "13": {
248 "desc": "port0 has failed due to a persistent retry"
249 },
250 "14": {
251 "desc": "informational register parity error"
252 },
253 "15": {
254 "desc": "soft error reported from error report register"
255 },
256 "16": {
257 "desc": "WDF unrecoverable mainline error"
258 },
259 "17": {
260 "desc": "WDF mmio error"
261 },
262 "18": {
263 "desc": "WDF array UE on mainline operations (SUE put in mem)"
264 },
265 "19": {
266 "desc": "WDF mainline dataflow error (SUE not reliably put in mem)"
267 },
268 "20": {
269 "desc": "WDF scom register parity error, affecting mainline config"
270 },
271 "21": {
272 "desc": "WDF scom register parity error, affecting scom ops only"
273 },
274 "22": {
275 "desc": "WDF SCOM fsm parity error"
276 },
277 "23": {
278 "desc": "WDF write buffer array CE"
279 },
280 "24": {
281 "desc": "refresh management CE port0"
282 },
283 "25": {
284 "desc": "refresh management RAA counter UE port0"
285 },
286 "26": {
287 "desc": "NCF fifo error port0"
288 },
289 "27": {
290 "desc": "NCF fifo error port1"
291 },
292 "28": {
293 "desc": "memcntl cmd xstop"
294 },
295 "29": {
296 "desc": "SRQ recoverable parity error"
297 },
298 "30": {
299 "desc": "DFI error port0"
300 },
301 "31": {
302 "desc": "xlat addr error port0"
303 },
304 "32": {
305 "desc": "refresh overrun port1"
306 },
307 "33": {
308 "desc": "RCD parity error port1"
309 },
310 "34": {
311 "desc": "DFI error port1"
312 },
313 "35": {
314 "desc": "event_n was active on the DDR interface port1"
315 },
316 "36": {
317 "desc": "WRQ or RRQ is in a hung state port1"
318 },
319 "37": {
320 "desc": "state machine one hot error port1"
321 },
322 "38": {
323 "desc": "ROQ errors port1"
324 },
325 "39": {
326 "desc": "Address parity error seen internal to sequencer on read or write command port1"
327 },
328 "40": {
329 "desc": "port1 has failed due to a persistent retry"
330 },
331 "41": {
332 "desc": "refresh management CE port1"
333 },
334 "42": {
335 "desc": "refresh management RAA counter UE port1"
336 },
337 "43": {
338 "desc": "xlat addr error port1"
339 },
340 "44": {
341 "desc": "check on ccs in progress bit"
342 },
343 "45": {
344 "desc": "DSM errors port1"
Caleb Palmer7729af72023-08-16 10:00:03 -0500[diff] [blame]345 },
Caleb Palmer94ea8ed2024-07-25 14:26:46 -0500[diff] [blame]346 "46": {
347 "desc": "Firmware initiated channel fail"
348 },
349 "47:48": {
Caleb Palmer7729af72023-08-16 10:00:03 -0500[diff] [blame]350 "desc": "reserved"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]351 }
352 },
353 "capture_groups": [
354 {
355 "group_name": "SRQ_FIR",
356 "group_inst": {
357 "0": 0
358 }
359 }
360 ]
361 }
362 },
363 "capture_groups": {
364 "SRQ_FIR": [
365 {
366 "reg_name": "SRQ_ERR_RPT",
367 "reg_inst": {
368 "0": 0
369 }
370 },
371 {
372 "reg_name": "MBXLT0",
373 "reg_inst": {
374 "0": 0
375 }
376 },
377 {
378 "reg_name": "MBXLT1",
379 "reg_inst": {
380 "0": 0
381 }
382 },
383 {
384 "reg_name": "MBXLT2",
385 "reg_inst": {
386 "0": 0
387 }
388 },
389 {
390 "reg_name": "MBXLT3",
391 "reg_inst": {
392 "0": 0
393 }
394 },
395 {
396 "reg_name": "WESR",
397 "reg_inst": {
398 "0": 0
399 }
400 },
401 {
402 "reg_name": "SRQ_ERR_RPT_HOLD",
403 "reg_inst": {
404 "0": 0
405 }
406 }
407 ]
408 }
409}