blob: d0a08243de84d4a375bbd63955528e4ab3e0365b [file] [log] [blame]
Zane Shelleyb9ea93c2023-03-10 10:41:41 -06001{
2 "version": 1,
3 "model_ec": ["EXPLORER_11", "EXPLORER_20"],
4 "registers": {
5 "MMIOFIR": {
6 "instances": {
7 "0": "0x08010870"
8 }
9 },
10 "MMIOFIR_MASK": {
11 "instances": {
12 "0": "0x08010873"
13 }
14 },
15 "MMIOFIR_ACT0": {
16 "instances": {
17 "0": "0x08010876"
18 }
19 },
20 "MMIOFIR_ACT1": {
21 "instances": {
22 "0": "0x08010877"
23 }
24 },
25 "MMIOFIR_WOF": {
26 "instances": {
27 "0": "0x08010878"
28 }
29 },
30 "MMIO_ERR_RPT_0": {
31 "instances": {
32 "0": "0x0801087C"
33 }
34 },
35 "MMIO_ERR_RPT_1": {
36 "instances": {
37 "0": "0x0801087E"
38 }
39 }
40 },
41 "isolation_nodes": {
42 "MMIOFIR": {
43 "instances": [0],
44 "rules": [
45 {
Zane Shelley925c3ed2023-04-14 13:42:22 -050046 "attn_type": ["CHIP_CS"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -060047 "node_inst": [0],
48 "expr": {
49 "expr_type": "and",
50 "exprs": [
51 {
52 "expr_type": "reg",
53 "reg_name": "MMIOFIR"
54 },
55 {
56 "expr_type": "not",
57 "expr": {
58 "expr_type": "reg",
59 "reg_name": "MMIOFIR_MASK"
60 }
61 },
62 {
63 "expr_type": "not",
64 "expr": {
65 "expr_type": "reg",
66 "reg_name": "MMIOFIR_ACT0"
67 }
68 },
69 {
70 "expr_type": "not",
71 "expr": {
72 "expr_type": "reg",
73 "reg_name": "MMIOFIR_ACT1"
74 }
75 }
76 ]
77 }
78 },
79 {
Zane Shelley925c3ed2023-04-14 13:42:22 -050080 "attn_type": ["RECOV"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -060081 "node_inst": [0],
82 "expr": {
83 "expr_type": "and",
84 "exprs": [
85 {
86 "expr_type": "reg",
87 "reg_name": "MMIOFIR"
88 },
89 {
90 "expr_type": "not",
91 "expr": {
92 "expr_type": "reg",
93 "reg_name": "MMIOFIR_MASK"
94 }
95 },
96 {
97 "expr_type": "not",
98 "expr": {
99 "expr_type": "reg",
100 "reg_name": "MMIOFIR_ACT0"
101 }
102 },
103 {
104 "expr_type": "reg",
105 "reg_name": "MMIOFIR_ACT1"
106 }
107 ]
108 }
109 },
110 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500111 "attn_type": ["SP_ATTN"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600112 "node_inst": [0],
113 "expr": {
114 "expr_type": "and",
115 "exprs": [
116 {
117 "expr_type": "reg",
118 "reg_name": "MMIOFIR"
119 },
120 {
121 "expr_type": "not",
122 "expr": {
123 "expr_type": "reg",
124 "reg_name": "MMIOFIR_MASK"
125 }
126 },
127 {
128 "expr_type": "reg",
129 "reg_name": "MMIOFIR_ACT0"
130 },
131 {
132 "expr_type": "not",
133 "expr": {
134 "expr_type": "reg",
135 "reg_name": "MMIOFIR_ACT1"
136 }
137 }
138 ]
139 }
140 }
141 ],
142 "bits": {
143 "0": {
144 "desc": "AFU desc unimp"
145 },
146 "1": {
147 "desc": "MMIO err"
148 },
149 "2": {
150 "desc": "SCOM err"
151 },
152 "3": {
153 "desc": "FSM perr"
154 },
155 "4": {
156 "desc": "FIFO overflow"
157 },
158 "5": {
159 "desc": "Ctl reg parity err"
160 },
161 "6": {
162 "desc": "Info reg parity error"
163 },
164 "7": {
165 "desc": "SNSC both starts err"
166 },
167 "8": {
168 "desc": "SNSC mult seq parity err"
169 },
170 "9": {
171 "desc": "SNSC FSM parity err"
172 },
173 "10": {
174 "desc": "SNSC reg parity err"
175 },
176 "11": {
177 "desc": "acTAG PASID cfg err"
178 }
179 },
180 "capture_groups": [
181 {
182 "group_name": "MMIOFIR",
183 "group_inst": {
184 "0": 0
185 }
186 }
187 ]
188 }
189 },
190 "capture_groups": {
191 "MMIOFIR": [
192 {
193 "reg_name": "MMIO_ERR_RPT_0",
194 "reg_inst": {
195 "0": 0
196 }
197 },
198 {
199 "reg_name": "MMIO_ERR_RPT_1",
200 "reg_inst": {
201 "0": 0
202 }
203 }
204 ]
205 }
206}