blob: 4786883be44fb3a8fd26a1a5850ada1cd3e9b3e8 [file] [log] [blame]
Zane Shelleyb9ea93c2023-03-10 10:41:41 -06001{
2 "version": 1,
3 "model_ec": ["EXPLORER_11", "EXPLORER_20"],
4 "registers": {
5 "OCMB_LFIR": {
6 "instances": {
7 "0": "0x0804000A"
8 }
9 },
10 "OCMB_LFIR_MASK": {
11 "instances": {
12 "0": "0x0804000D"
13 }
14 },
15 "OCMB_LFIR_ACT0": {
16 "instances": {
17 "0": "0x08040010"
18 }
19 },
20 "OCMB_LFIR_ACT1": {
21 "instances": {
22 "0": "0x08040011"
23 }
24 },
25 "ADSP_PCBI": {
26 "instances": {
27 "0": "0x00200860",
28 "1": "0x00201860",
29 "2": "0x00202860",
30 "3": "0x00203860",
31 "4": "0x00204860",
32 "5": "0x00205860",
33 "6": "0x00206860",
34 "7": "0x00207860"
35 }
36 },
37 "CSU_PCBI": {
38 "instances": {
39 "0": "0x002000B0",
40 "1": "0x002010B0",
41 "2": "0x002020B0",
42 "3": "0x002030B0",
43 "4": "0x002040B0",
44 "5": "0x002050B0",
45 "6": "0x002060B0",
46 "7": "0x002070B0"
47 }
48 }
49 },
50 "isolation_nodes": {
51 "OCMB_LFIR": {
52 "instances": [0],
53 "rules": [
54 {
Zane Shelley925c3ed2023-04-14 13:42:22 -050055 "attn_type": ["CHIP_CS"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -060056 "node_inst": [0],
57 "expr": {
58 "expr_type": "and",
59 "exprs": [
60 {
61 "expr_type": "reg",
62 "reg_name": "OCMB_LFIR"
63 },
64 {
65 "expr_type": "not",
66 "expr": {
67 "expr_type": "reg",
68 "reg_name": "OCMB_LFIR_MASK"
69 }
70 },
71 {
72 "expr_type": "not",
73 "expr": {
74 "expr_type": "reg",
75 "reg_name": "OCMB_LFIR_ACT0"
76 }
77 },
78 {
79 "expr_type": "not",
80 "expr": {
81 "expr_type": "reg",
82 "reg_name": "OCMB_LFIR_ACT1"
83 }
84 }
85 ]
86 }
87 },
88 {
Zane Shelley925c3ed2023-04-14 13:42:22 -050089 "attn_type": ["RECOV"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -060090 "node_inst": [0],
91 "expr": {
92 "expr_type": "and",
93 "exprs": [
94 {
95 "expr_type": "reg",
96 "reg_name": "OCMB_LFIR"
97 },
98 {
99 "expr_type": "not",
100 "expr": {
101 "expr_type": "reg",
102 "reg_name": "OCMB_LFIR_MASK"
103 }
104 },
105 {
106 "expr_type": "not",
107 "expr": {
108 "expr_type": "reg",
109 "reg_name": "OCMB_LFIR_ACT0"
110 }
111 },
112 {
113 "expr_type": "reg",
114 "reg_name": "OCMB_LFIR_ACT1"
115 }
116 ]
117 }
118 }
119 ],
120 "bits": {
121 "0": {
122 "desc": "CFIR access PCB error"
123 },
124 "1": {
125 "desc": "CFIR internal parity error"
126 },
127 "2": {
128 "desc": "LFIR internal parity error"
129 },
130 "3": {
131 "desc": "Debug scom satellite error"
132 },
133 "4": {
134 "desc": "PSCOM Logic: PCB Access Error"
135 },
136 "5": {
137 "desc": "PSCOM Logic: Summarized internal errors"
138 },
139 "6": {
140 "desc": "Trace Logic : Scom Satellite Error - Trace0"
141 },
142 "7": {
143 "desc": "Trace Logic : Scom Satellite Error - Trace1"
144 },
145 "8": {
146 "desc": "PIB2GIF parity error on FSM or Registers"
147 },
148 "9": {
149 "desc": "MSG access PCB error"
150 },
151 "10:18": {
152 "desc": "unused"
153 },
154 "19": {
155 "desc": "DLL IRQ"
156 },
157 "20": {
158 "desc": "Watchdog timer interrupt"
159 },
160 "21": {
161 "desc": "internal temp sensor tripped a threshold"
162 },
163 "22": {
164 "desc": "GPBC_FATAL_ERROR"
165 },
166 "23": {
167 "desc": "GPBC_NON_FATAL_ERROR"
168 },
169 "24": {
170 "desc": "early power off warning"
171 },
172 "25": {
173 "desc": "TOP fatal interrupts"
174 },
175 "26": {
176 "desc": "TOP non fatal interrupts"
177 },
178 "27:30": {
179 "desc": "Interrupt from OPSe to OCMB"
180 },
181 "31": {
182 "desc": "SerDes continuous calibration failure"
183 },
184 "32": {
185 "desc": "Firmware Assert or CPU Exception"
186 },
187 "33": {
188 "desc": "Extended error information ready"
189 },
190 "34": {
191 "desc": "Interrupt from OPSe to OCMB"
192 },
193 "35": {
194 "desc": "DDR thermal event"
195 },
196 "36": {
197 "desc": "DDR4 PHY fatal"
198 },
199 "37": {
200 "desc": "DDR4 PHY non fatal"
201 },
202 "38": {
203 "desc": "DDR4 PHY interrupt"
204 },
205 "39": {
206 "desc": "foxhound fatal lane 7"
207 },
208 "40": {
209 "desc": "foxhound fatal lane 6"
210 },
211 "41": {
212 "desc": "foxhound fatal lane 5"
213 },
214 "42": {
215 "desc": "foxhound fatal lane 4"
216 },
217 "43": {
218 "desc": "foxhound fatal lane 3"
219 },
220 "44": {
221 "desc": "foxhound fatal lane 2"
222 },
223 "45": {
224 "desc": "foxhound fatal lane 1"
225 },
226 "46": {
227 "desc": "foxhound fatal lane 0"
228 },
229 "47:54": {
230 "desc": "foxhound non fatal"
231 },
232 "55:62": {
233 "desc": "foxhound serdes interrupt"
234 },
235 "63": {
236 "desc": "GIF2PCB parity error on FSM or Registers"
237 }
238 },
239 "capture_groups": [
240 {
241 "group_name": "OCMB_LFIR",
242 "group_inst": {
243 "0": 0
244 }
245 }
246 ]
247 }
248 },
249 "capture_groups": {
250 "OCMB_LFIR": [
251 {
252 "reg_name": "ADSP_PCBI",
253 "reg_inst": {
254 "0": 0
255 }
256 },
257 {
258 "reg_name": "ADSP_PCBI",
259 "reg_inst": {
260 "0": 1
261 }
262 },
263 {
264 "reg_name": "ADSP_PCBI",
265 "reg_inst": {
266 "0": 2
267 }
268 },
269 {
270 "reg_name": "ADSP_PCBI",
271 "reg_inst": {
272 "0": 3
273 }
274 },
275 {
276 "reg_name": "ADSP_PCBI",
277 "reg_inst": {
278 "0": 4
279 }
280 },
281 {
282 "reg_name": "ADSP_PCBI",
283 "reg_inst": {
284 "0": 5
285 }
286 },
287 {
288 "reg_name": "ADSP_PCBI",
289 "reg_inst": {
290 "0": 6
291 }
292 },
293 {
294 "reg_name": "ADSP_PCBI",
295 "reg_inst": {
296 "0": 7
297 }
298 },
299 {
300 "reg_name": "CSU_PCBI",
301 "reg_inst": {
302 "0": 0
303 }
304 },
305 {
306 "reg_name": "CSU_PCBI",
307 "reg_inst": {
308 "0": 1
309 }
310 },
311 {
312 "reg_name": "CSU_PCBI",
313 "reg_inst": {
314 "0": 2
315 }
316 },
317 {
318 "reg_name": "CSU_PCBI",
319 "reg_inst": {
320 "0": 3
321 }
322 },
323 {
324 "reg_name": "CSU_PCBI",
325 "reg_inst": {
326 "0": 4
327 }
328 },
329 {
330 "reg_name": "CSU_PCBI",
331 "reg_inst": {
332 "0": 5
333 }
334 },
335 {
336 "reg_name": "CSU_PCBI",
337 "reg_inst": {
338 "0": 6
339 }
340 },
341 {
342 "reg_name": "CSU_PCBI",
343 "reg_inst": {
344 "0": 7
345 }
346 }
347 ]
348 }
349}