| Zane Shelley | b9ea93c | 2023-03-10 10:41:41 -0600 | [diff] [blame] | 1 | { |
| 2 | "version": 1, |
| 3 | "model_ec": ["EXPLORER_11", "EXPLORER_20"], |
| 4 | "registers": { |
| 5 | "TLXFIR": { |
| 6 | "instances": { |
| 7 | "0": "0x08012400" |
| 8 | } |
| 9 | }, |
| 10 | "TLXFIR_MASK": { |
| 11 | "instances": { |
| 12 | "0": "0x08012403" |
| 13 | } |
| 14 | }, |
| 15 | "TLXFIR_ACT0": { |
| 16 | "instances": { |
| 17 | "0": "0x08012406" |
| 18 | } |
| 19 | }, |
| 20 | "TLXFIR_ACT1": { |
| 21 | "instances": { |
| 22 | "0": "0x08012407" |
| 23 | } |
| 24 | }, |
| 25 | "TLXFIR_WOF": { |
| 26 | "instances": { |
| 27 | "0": "0x08012408" |
| 28 | } |
| 29 | }, |
| 30 | "TLX_ERR_RPT_0": { |
| 31 | "instances": { |
| 32 | "0": "0x0801241C" |
| 33 | } |
| 34 | }, |
| 35 | "TLX_ERR_RPT_1": { |
| 36 | "instances": { |
| 37 | "0": "0x0801241D" |
| 38 | } |
| 39 | }, |
| 40 | "TLX_ERR_RPT_2": { |
| 41 | "instances": { |
| 42 | "0": "0x0801241E" |
| 43 | } |
| 44 | }, |
| 45 | "TLX_ERR_RPT_0_MASK": { |
| 46 | "instances": { |
| 47 | "0": "0x08012414" |
| 48 | } |
| 49 | }, |
| 50 | "TLX_ERR_RPT_1_MASK": { |
| 51 | "instances": { |
| 52 | "0": "0x08012415" |
| 53 | } |
| 54 | }, |
| 55 | "TLX_ERR_RPT_2_MASK": { |
| 56 | "instances": { |
| 57 | "0": "0x08012416" |
| 58 | } |
| 59 | } |
| 60 | }, |
| 61 | "isolation_nodes": { |
| 62 | "TLXFIR": { |
| 63 | "instances": [0], |
| 64 | "rules": [ |
| 65 | { |
| 66 | "attn_type": ["CS"], |
| 67 | "node_inst": [0], |
| 68 | "expr": { |
| 69 | "expr_type": "and", |
| 70 | "exprs": [ |
| 71 | { |
| 72 | "expr_type": "reg", |
| 73 | "reg_name": "TLXFIR" |
| 74 | }, |
| 75 | { |
| 76 | "expr_type": "not", |
| 77 | "expr": { |
| 78 | "expr_type": "reg", |
| 79 | "reg_name": "TLXFIR_MASK" |
| 80 | } |
| 81 | }, |
| 82 | { |
| 83 | "expr_type": "not", |
| 84 | "expr": { |
| 85 | "expr_type": "reg", |
| 86 | "reg_name": "TLXFIR_ACT0" |
| 87 | } |
| 88 | }, |
| 89 | { |
| 90 | "expr_type": "not", |
| 91 | "expr": { |
| 92 | "expr_type": "reg", |
| 93 | "reg_name": "TLXFIR_ACT1" |
| 94 | } |
| 95 | } |
| 96 | ] |
| 97 | } |
| 98 | }, |
| 99 | { |
| 100 | "attn_type": ["RE"], |
| 101 | "node_inst": [0], |
| 102 | "expr": { |
| 103 | "expr_type": "and", |
| 104 | "exprs": [ |
| 105 | { |
| 106 | "expr_type": "reg", |
| 107 | "reg_name": "TLXFIR" |
| 108 | }, |
| 109 | { |
| 110 | "expr_type": "not", |
| 111 | "expr": { |
| 112 | "expr_type": "reg", |
| 113 | "reg_name": "TLXFIR_MASK" |
| 114 | } |
| 115 | }, |
| 116 | { |
| 117 | "expr_type": "not", |
| 118 | "expr": { |
| 119 | "expr_type": "reg", |
| 120 | "reg_name": "TLXFIR_ACT0" |
| 121 | } |
| 122 | }, |
| 123 | { |
| 124 | "expr_type": "reg", |
| 125 | "reg_name": "TLXFIR_ACT1" |
| 126 | } |
| 127 | ] |
| 128 | } |
| 129 | }, |
| 130 | { |
| 131 | "attn_type": ["SPA"], |
| 132 | "node_inst": [0], |
| 133 | "expr": { |
| 134 | "expr_type": "and", |
| 135 | "exprs": [ |
| 136 | { |
| 137 | "expr_type": "reg", |
| 138 | "reg_name": "TLXFIR" |
| 139 | }, |
| 140 | { |
| 141 | "expr_type": "not", |
| 142 | "expr": { |
| 143 | "expr_type": "reg", |
| 144 | "reg_name": "TLXFIR_MASK" |
| 145 | } |
| 146 | }, |
| 147 | { |
| 148 | "expr_type": "reg", |
| 149 | "reg_name": "TLXFIR_ACT0" |
| 150 | }, |
| 151 | { |
| 152 | "expr_type": "not", |
| 153 | "expr": { |
| 154 | "expr_type": "reg", |
| 155 | "reg_name": "TLXFIR_ACT1" |
| 156 | } |
| 157 | } |
| 158 | ] |
| 159 | } |
| 160 | } |
| 161 | ], |
| 162 | "bits": { |
| 163 | "0": { |
| 164 | "desc": "Info reg parity error" |
| 165 | }, |
| 166 | "1": { |
| 167 | "desc": "Ctrl reg parity error" |
| 168 | }, |
| 169 | "2": { |
| 170 | "desc": "TLX VC0 return credit counter overflow" |
| 171 | }, |
| 172 | "3": { |
| 173 | "desc": "TLX VC1 return credit counter overflow" |
| 174 | }, |
| 175 | "4": { |
| 176 | "desc": "TLX dcp0 return credit counter overflow" |
| 177 | }, |
| 178 | "5": { |
| 179 | "desc": "TLX dcp1 return credit counter overflow" |
| 180 | }, |
| 181 | "6": { |
| 182 | "desc": "TLX credit management block error" |
| 183 | }, |
| 184 | "7": { |
| 185 | "desc": "TLX credit management block parity error" |
| 186 | }, |
| 187 | "8": { |
| 188 | "desc": "TLXT fatal parity error" |
| 189 | }, |
| 190 | "9": { |
| 191 | "desc": "TLXT recoverable error", |
| 192 | "child_node": { |
| 193 | "name": "TLX_ERR_RPT_1" |
| 194 | } |
| 195 | }, |
| 196 | "10": { |
| 197 | "desc": "TLXT configuration error" |
| 198 | }, |
| 199 | "11": { |
| 200 | "desc": "TLXT informational parity error" |
| 201 | }, |
| 202 | "12": { |
| 203 | "desc": "TLXT hard error" |
| 204 | }, |
| 205 | "13:15": { |
| 206 | "desc": "Reserved" |
| 207 | }, |
| 208 | "16": { |
| 209 | "desc": "Corrupted pad mem pattern" |
| 210 | }, |
| 211 | "17": { |
| 212 | "desc": "Downstream OC parity error" |
| 213 | }, |
| 214 | "18": { |
| 215 | "desc": "OC malformed" |
| 216 | }, |
| 217 | "19": { |
| 218 | "desc": "OC protocol error" |
| 219 | }, |
| 220 | "20": { |
| 221 | "desc": "Address translate error" |
| 222 | }, |
| 223 | "21": { |
| 224 | "desc": "Metadata unc or data parity error" |
| 225 | }, |
| 226 | "22": { |
| 227 | "desc": "OC unsupported group 2" |
| 228 | }, |
| 229 | "23": { |
| 230 | "desc": "OC unsupported group 1" |
| 231 | }, |
| 232 | "24": { |
| 233 | "desc": "Bit flip control error" |
| 234 | }, |
| 235 | "25": { |
| 236 | "desc": "Control HW error" |
| 237 | }, |
| 238 | "26": { |
| 239 | "desc": "ECC corrected and others" |
| 240 | }, |
| 241 | "27": { |
| 242 | "desc": "Trace stop" |
| 243 | }, |
| 244 | "28": { |
| 245 | "desc": "Internal SCOM error" |
| 246 | }, |
| 247 | "29": { |
| 248 | "desc": "Internal SCOM error clone" |
| 249 | } |
| 250 | }, |
| 251 | "capture_groups": [ |
| 252 | { |
| 253 | "group_name": "TLXFIR", |
| 254 | "group_inst": { |
| 255 | "0": 0 |
| 256 | } |
| 257 | } |
| 258 | ] |
| 259 | } |
| 260 | }, |
| 261 | "capture_groups": { |
| 262 | "TLXFIR": [ |
| 263 | { |
| 264 | "reg_name": "TLX_ERR_RPT_0", |
| 265 | "reg_inst": { |
| 266 | "0": 0 |
| 267 | } |
| 268 | }, |
| 269 | { |
| 270 | "reg_name": "TLX_ERR_RPT_1", |
| 271 | "reg_inst": { |
| 272 | "0": 0 |
| 273 | } |
| 274 | }, |
| 275 | { |
| 276 | "reg_name": "TLX_ERR_RPT_2", |
| 277 | "reg_inst": { |
| 278 | "0": 0 |
| 279 | } |
| 280 | }, |
| 281 | { |
| 282 | "reg_name": "TLX_ERR_RPT_0_MASK", |
| 283 | "reg_inst": { |
| 284 | "0": 0 |
| 285 | } |
| 286 | }, |
| 287 | { |
| 288 | "reg_name": "TLX_ERR_RPT_1_MASK", |
| 289 | "reg_inst": { |
| 290 | "0": 0 |
| 291 | } |
| 292 | }, |
| 293 | { |
| 294 | "reg_name": "TLX_ERR_RPT_2_MASK", |
| 295 | "reg_inst": { |
| 296 | "0": 0 |
| 297 | } |
| 298 | } |
| 299 | ] |
| 300 | } |
| 301 | } |