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gerrit.openbmc.org / openbmc / openpower-libhei / 94ea8ed1369e0b26be0aec2fe7dfdf87ccada581 / . / chip_data / odyssey / node_mmio_fir.json
blob: 8504759cf46b0b7d2d475d297b4742a3ab8b97c3 [file] [log] [blame]
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]1{
2 "version": 1,
3 "model_ec": ["ODYSSEY_10"],
4 "registers": {
5 "MMIO_FIR": {
6 "instances": {
7 "0": "0x08010870"
8 }
9 },
Caleb Palmer94ea8ed2024-07-25 14:26:46 -0500[diff] [blame^]10 "MMIO_FIR_OR": {
11 "access": "WO",
12 "instances": {
13 "0": "0x08010871"
14 }
15 },
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]16 "MMIO_FIR_MASK": {
17 "instances": {
18 "0": "0x08010872"
19 }
20 },
Caleb Palmer94ea8ed2024-07-25 14:26:46 -0500[diff] [blame^]21 "MMIO_FIR_MASK_OR": {
22 "access": "WO",
23 "instances": {
24 "0": "0x08010873"
25 }
26 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]27 "MMIO_FIR_CFG_CHIP_CS": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]28 "instances": {
29 "0": "0x08010874"
30 }
31 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]32 "MMIO_FIR_CFG_RECOV": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]33 "instances": {
34 "0": "0x08010875"
35 }
36 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]37 "MMIO_FIR_CFG_SP_ATTN": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]38 "instances": {
39 "0": "0x08010876"
40 }
41 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]42 "MMIO_FIR_CFG_UNIT_CS": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]43 "instances": {
44 "0": "0x08010877"
45 }
46 },
47 "MMIO_FIR_WOF": {
48 "instances": {
49 "0": "0x08010878"
50 }
51 },
52 "MMIO_ERR_RPT_0": {
53 "instances": {
54 "0": "0x0801087C"
55 }
56 },
57 "MMIO_ERR_RPT_1": {
58 "instances": {
59 "0": "0x0801087E"
60 }
61 }
62 },
63 "isolation_nodes": {
64 "MMIO_FIR": {
65 "instances": [0],
66 "rules": [
67 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]68 "attn_type": ["CHIP_CS"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]69 "node_inst": [0],
70 "expr": {
71 "expr_type": "and",
72 "exprs": [
73 {
74 "expr_type": "reg",
75 "reg_name": "MMIO_FIR"
76 },
77 {
78 "expr_type": "not",
79 "expr": {
80 "expr_type": "reg",
81 "reg_name": "MMIO_FIR_MASK"
82 }
83 },
84 {
85 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]86 "reg_name": "MMIO_FIR_CFG_CHIP_CS"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]87 }
88 ]
89 }
90 },
91 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]92 "attn_type": ["RECOV"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]93 "node_inst": [0],
94 "expr": {
95 "expr_type": "and",
96 "exprs": [
97 {
98 "expr_type": "reg",
99 "reg_name": "MMIO_FIR"
100 },
101 {
102 "expr_type": "not",
103 "expr": {
104 "expr_type": "reg",
105 "reg_name": "MMIO_FIR_MASK"
106 }
107 },
108 {
109 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]110 "reg_name": "MMIO_FIR_CFG_RECOV"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]111 }
112 ]
113 }
114 },
115 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]116 "attn_type": ["SP_ATTN"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]117 "node_inst": [0],
118 "expr": {
119 "expr_type": "and",
120 "exprs": [
121 {
122 "expr_type": "reg",
123 "reg_name": "MMIO_FIR"
124 },
125 {
126 "expr_type": "not",
127 "expr": {
128 "expr_type": "reg",
129 "reg_name": "MMIO_FIR_MASK"
130 }
131 },
132 {
133 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]134 "reg_name": "MMIO_FIR_CFG_SP_ATTN"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]135 }
136 ]
137 }
138 },
139 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]140 "attn_type": ["UNIT_CS"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]141 "node_inst": [0],
142 "expr": {
143 "expr_type": "and",
144 "exprs": [
145 {
146 "expr_type": "reg",
147 "reg_name": "MMIO_FIR"
148 },
149 {
150 "expr_type": "not",
151 "expr": {
152 "expr_type": "reg",
153 "reg_name": "MMIO_FIR_MASK"
154 }
155 },
156 {
157 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]158 "reg_name": "MMIO_FIR_CFG_UNIT_CS"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]159 }
160 ]
161 }
162 }
163 ],
Caleb Palmer94ea8ed2024-07-25 14:26:46 -0500[diff] [blame^]164 "op_rules": {
165 "FIR_SET": {
166 "op_rule": "atomic_or",
167 "reg_name": "MMIO_FIR_OR"
168 },
169 "FIR_CLEAR": {
170 "op_rule": "atomic_or",
171 "reg_name": "MMIO_FIR"
172 },
173 "MASK_SET": {
174 "op_rule": "atomic_or",
175 "reg_name": "MMIO_FIR_MASK_OR"
176 },
177 "MASK_CLEAR": {
178 "op_rule": "atomic_or",
179 "reg_name": "MMIO_FIR_MASK"
180 }
181 },
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]182 "bits": {
183 "0": {
184 "desc": "Interal SCOM logic parity error"
185 },
186 "1": {
187 "desc": "Attempt to access an unimplemented address in the AFU descriptor"
188 },
189 "2": {
190 "desc": "Error detected during MMIO inband or senor cache access"
191 },
192 "3": {
193 "desc": "Parity error in SCOM satellite component FSM"
194 },
195 "4": {
196 "desc": "Parity error in MMIO/CFG logic FSM"
197 },
198 "5": {
199 "desc": "Overflow detected in internal MMIO/CFG logic FIFO"
200 },
201 "6": {
202 "desc": "Fatal parity error detected in control register"
203 },
204 "7": {
205 "desc": "Parity error detected in informational register"
206 },
207 "8": {
208 "desc": "Both start signals asserted to Sensor cache logic"
209 },
210 "9": {
211 "desc": "Multiple parity errors on data from sequencer to sensor cache logic"
212 },
213 "10": {
214 "desc": "State machine parity error in sensor cache logic"
215 },
216 "11": {
217 "desc": "Sensor cache register parity error"
218 },
219 "12": {
220 "desc": "acTAG PASID config error"
221 }
222 },
223 "capture_groups": [
224 {
225 "group_name": "MMIO_FIR",
226 "group_inst": {
227 "0": 0
228 }
229 }
230 ]
231 }
232 },
233 "capture_groups": {
234 "MMIO_FIR": [
235 {
236 "reg_name": "MMIO_ERR_RPT_0",
237 "reg_inst": {
238 "0": 0
239 }
240 },
241 {
242 "reg_name": "MMIO_ERR_RPT_1",
243 "reg_inst": {
244 "0": 0
245 }
246 }
247 ]
248 }
249}