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gerrit.openbmc.org / openbmc / openpower-libhei / a27b584cb2153070872b2a9c3f16020a4cd348f3 / . / chip_data / odyssey / node_dlx_fir.json
blob: e687b7f40005c47042416407f3cc3773f4b0f1ac [file] [log] [blame]
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]1{
2 "version": 1,
3 "model_ec": ["ODYSSEY_10"],
4 "registers": {
5 "DLX_FIR": {
6 "instances": {
7 "0": "0x08012400"
8 }
9 },
Caleb Palmer94ea8ed2024-07-25 14:26:46 -0500[diff] [blame]10 "DLX_FIR_OR": {
11 "access": "WO",
12 "instances": {
13 "0": "0x08012401"
14 }
15 },
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]16 "DLX_FIR_MASK": {
17 "instances": {
18 "0": "0x08012402"
19 }
20 },
Caleb Palmer94ea8ed2024-07-25 14:26:46 -0500[diff] [blame]21 "DLX_FIR_MASK_OR": {
22 "access": "WO",
23 "instances": {
24 "0": "0x08012403"
25 }
26 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]27 "DLX_FIR_CFG_CHIP_CS": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]28 "instances": {
29 "0": "0x08012404"
30 }
31 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]32 "DLX_FIR_CFG_RECOV": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]33 "instances": {
34 "0": "0x08012405"
35 }
36 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]37 "DLX_FIR_CFG_SP_ATTN": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]38 "instances": {
39 "0": "0x08012406"
40 }
41 },
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]42 "DLX_FIR_CFG_UNIT_CS": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]43 "instances": {
44 "0": "0x08012407"
45 }
46 },
47 "DLX_FIR_WOF": {
48 "instances": {
49 "0": "0x08012408"
50 }
51 },
52 "CMN_CONFIG": {
53 "instances": {
54 "0": "0x0801240E"
55 }
56 },
57 "PMU_CNTR": {
58 "instances": {
59 "0": "0x0801240F"
60 }
61 },
62 "DLX_CONFIG0": {
63 "instances": {
64 "0": "0x08012410"
65 }
66 },
67 "DLX_CONFIG1": {
68 "instances": {
69 "0": "0x08012411"
70 }
71 },
72 "DLX_ERR_MASK": {
73 "instances": {
74 "0": "0x08012412"
75 }
76 },
77 "DLX_ERR_RPT": {
78 "instances": {
79 "0": "0x08012413"
80 }
81 },
82 "DLX_EDPL_MAX_COUNT": {
83 "instances": {
84 "0": "0x08012415"
85 }
86 },
87 "DLX_STATUS": {
88 "instances": {
89 "0": "0x08012416"
90 }
91 },
92 "DLX_TRAINING_STATUS": {
93 "instances": {
94 "0": "0x08012417"
95 }
96 },
97 "DLX_RMT_CONFIG": {
98 "instances": {
99 "0": "0x08012418"
100 }
101 },
102 "DLX_RMT_INFO": {
103 "instances": {
104 "0": "0x08012419"
105 }
106 },
107 "DLX_SKIT_CTL": {
108 "instances": {
109 "0": "0x0801241A"
110 }
111 },
112 "DLX_SKIT_STATUS": {
113 "instances": {
114 "0": "0x0801241B"
115 }
116 },
117 "DLX_CYA2": {
118 "instances": {
119 "0": "0x0801241C"
120 }
121 },
122 "DLX_ERR_ACTION": {
123 "instances": {
124 "0": "0x0801241D"
125 }
126 },
127 "DLX_DEBUG_AID": {
128 "instances": {
129 "0": "0x0801241E"
130 }
131 },
132 "DLX_CYA_BITS": {
133 "instances": {
134 "0": "0x0801241F"
135 }
136 }
137 },
138 "isolation_nodes": {
139 "DLX_FIR": {
140 "instances": [0],
141 "rules": [
142 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]143 "attn_type": ["CHIP_CS"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]144 "node_inst": [0],
145 "expr": {
146 "expr_type": "and",
147 "exprs": [
148 {
149 "expr_type": "reg",
150 "reg_name": "DLX_FIR"
151 },
152 {
153 "expr_type": "not",
154 "expr": {
155 "expr_type": "reg",
156 "reg_name": "DLX_FIR_MASK"
157 }
158 },
159 {
160 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]161 "reg_name": "DLX_FIR_CFG_CHIP_CS"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]162 }
163 ]
164 }
165 },
166 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]167 "attn_type": ["RECOV"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]168 "node_inst": [0],
169 "expr": {
170 "expr_type": "and",
171 "exprs": [
172 {
173 "expr_type": "reg",
174 "reg_name": "DLX_FIR"
175 },
176 {
177 "expr_type": "not",
178 "expr": {
179 "expr_type": "reg",
180 "reg_name": "DLX_FIR_MASK"
181 }
182 },
183 {
184 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]185 "reg_name": "DLX_FIR_CFG_RECOV"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]186 }
187 ]
188 }
189 },
190 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]191 "attn_type": ["SP_ATTN"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]192 "node_inst": [0],
193 "expr": {
194 "expr_type": "and",
195 "exprs": [
196 {
197 "expr_type": "reg",
198 "reg_name": "DLX_FIR"
199 },
200 {
201 "expr_type": "not",
202 "expr": {
203 "expr_type": "reg",
204 "reg_name": "DLX_FIR_MASK"
205 }
206 },
207 {
208 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]209 "reg_name": "DLX_FIR_CFG_SP_ATTN"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]210 }
211 ]
212 }
213 },
214 {
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]215 "attn_type": ["UNIT_CS"],
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]216 "node_inst": [0],
217 "expr": {
218 "expr_type": "and",
219 "exprs": [
220 {
221 "expr_type": "reg",
222 "reg_name": "DLX_FIR"
223 },
224 {
225 "expr_type": "not",
226 "expr": {
227 "expr_type": "reg",
228 "reg_name": "DLX_FIR_MASK"
229 }
230 },
231 {
232 "expr_type": "reg",
Zane Shelley925c3ed2023-04-14 13:42:22 -0500[diff] [blame]233 "reg_name": "DLX_FIR_CFG_UNIT_CS"
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]234 }
235 ]
236 }
237 }
238 ],
Caleb Palmer94ea8ed2024-07-25 14:26:46 -0500[diff] [blame]239 "op_rules": {
240 "FIR_SET": {
241 "op_rule": "atomic_or",
242 "reg_name": "DLX_FIR_OR"
243 },
244 "FIR_CLEAR": {
245 "op_rule": "atomic_or",
246 "reg_name": "DLX_FIR"
247 },
248 "MASK_SET": {
249 "op_rule": "atomic_or",
250 "reg_name": "DLX_FIR_MASK_OR"
251 },
252 "MASK_CLEAR": {
253 "op_rule": "atomic_or",
254 "reg_name": "DLX_FIR_MASK"
255 }
256 },
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]257 "bits": {
258 "0": {
259 "desc": "Internal parity error in SCOM component"
260 },
261 "1": {
262 "desc": "DL0 fatal error",
263 "child_node": {
264 "name": "DLX_ERR_RPT",
265 "inst": {
266 "0": 0
267 }
268 }
269 },
270 "2": {
271 "desc": "DL0 buffer UE / insufficient working lanes",
272 "child_node": {
273 "name": "DLX_ERR_RPT",
274 "inst": {
275 "0": 0
276 }
277 }
278 },
279 "3": {
280 "desc": "DL0 CE on TL flit"
281 },
282 "4": {
283 "desc": "DL0 detected a CRC error"
284 },
285 "5": {
286 "desc": "DL0 received a nack"
287 },
288 "6": {
289 "desc": "DL0 running in degraded mode"
290 },
291 "7": {
292 "desc": "DL0 parity error detection on a lane"
293 },
294 "8": {
295 "desc": "DL0 retrained due to no forward progress"
296 },
297 "9": {
298 "desc": "DL0 remote side initiated a retrain"
299 },
300 "10": {
301 "desc": "DL0 retrain due to internal error or software"
302 },
303 "11": {
304 "desc": "DL0 threshold reached"
305 },
306 "12": {
307 "desc": "DL0 trained"
308 },
309 "13": {
310 "desc": "DL0 received replay flit with link_errors bit 0"
311 },
312 "14": {
313 "desc": "DL0 received replay flit with link_errors bit 1"
314 },
315 "15": {
316 "desc": "DL0 received replay flit with link_errors bit 2"
317 },
318 "16": {
319 "desc": "DL0 received replay flit with link_errors bit 3"
320 },
321 "17": {
322 "desc": "DL0 received replay flit with link_errors bit 4"
323 },
324 "18": {
325 "desc": "DL0 received replay flit with link_errors bit 5"
326 },
327 "19": {
328 "desc": "DL0 received replay flit with link_errors bit 6"
329 },
330 "20": {
331 "desc": "DL0 received replay flit with link_errors bit 7"
332 },
333 "21": {
334 "desc": "DL0 skitter error"
335 },
336 "22": {
337 "desc": "DL0 skitter drift detected"
338 },
Caleb Palmer7729af72023-08-16 10:00:03 -0500[diff] [blame]339 "23:44": {
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame]340 "desc": "reserved"
341 }
342 },
343 "capture_groups": [
344 {
345 "group_name": "DLX_FIR",
346 "group_inst": {
347 "0": 0
348 }
349 }
350 ]
351 }
352 },
353 "capture_groups": {
354 "DLX_FIR": [
355 {
356 "reg_name": "CMN_CONFIG",
357 "reg_inst": {
358 "0": 0
359 }
360 },
361 {
362 "reg_name": "PMU_CNTR",
363 "reg_inst": {
364 "0": 0
365 }
366 },
367 {
368 "reg_name": "DLX_CONFIG0",
369 "reg_inst": {
370 "0": 0
371 }
372 },
373 {
374 "reg_name": "DLX_CONFIG1",
375 "reg_inst": {
376 "0": 0
377 }
378 },
379 {
380 "reg_name": "DLX_ERR_MASK",
381 "reg_inst": {
382 "0": 0
383 }
384 },
385 {
386 "reg_name": "DLX_ERR_RPT",
387 "reg_inst": {
388 "0": 0
389 }
390 },
391 {
392 "reg_name": "DLX_EDPL_MAX_COUNT",
393 "reg_inst": {
394 "0": 0
395 }
396 },
397 {
398 "reg_name": "DLX_STATUS",
399 "reg_inst": {
400 "0": 0
401 }
402 },
403 {
404 "reg_name": "DLX_TRAINING_STATUS",
405 "reg_inst": {
406 "0": 0
407 }
408 },
409 {
410 "reg_name": "DLX_RMT_CONFIG",
411 "reg_inst": {
412 "0": 0
413 }
414 },
415 {
416 "reg_name": "DLX_RMT_INFO",
417 "reg_inst": {
418 "0": 0
419 }
420 },
421 {
422 "reg_name": "DLX_SKIT_CTL",
423 "reg_inst": {
424 "0": 0
425 }
426 },
427 {
428 "reg_name": "DLX_SKIT_STATUS",
429 "reg_inst": {
430 "0": 0
431 }
432 },
433 {
434 "reg_name": "DLX_CYA2",
435 "reg_inst": {
436 "0": 0
437 }
438 },
439 {
440 "reg_name": "DLX_ERR_ACTION",
441 "reg_inst": {
442 "0": 0
443 }
444 },
445 {
446 "reg_name": "DLX_DEBUG_AID",
447 "reg_inst": {
448 "0": 0
449 }
450 },
451 {
452 "reg_name": "DLX_CYA_BITS",
453 "reg_inst": {
454 "0": 0
455 }
456 }
457 ]
458 }
459}