xml/p10/node_int_cq_fir.xml

<?xml version="1.0" encoding="UTF-8"?>
<attn_node model_ec="P10_10" name="INT_CQ_FIR" reg_type="SCOM">
    <local_fir config="W" name="INT_CQ_FIR">
        <instance addr="0x02010830" reg_inst="0"/>
        <action attn_type="CS" config="00"/>
        <action attn_type="RE" config="01"/>
        <action attn_type="SPA" config="10"/>
    </local_fir>
    <bit pos="0">Correctable ECC error detected while consuming data from the PowerBus Data ramp.  See INT_CQ_ERR_INFO2 for details.</bit>
    <bit pos="1">Uncorrectable ECC error detected while consuming data from the PowerBus Data ramp.  See INT_CQ_ERR_INFO2 for details.</bit>
    <bit pos="2">Special uncorrectable ECC error detected while consuming data on the PowerBus Data ramp for a Master DMA Read or Master CI Read.</bit>
    <bit pos="3">Correctable ECC error detected while reading the PowerBus Data In Array. See INT_CQ_ERR_INFO2 for details.</bit>
    <bit pos="4">Uncorrectable ECC error detected while reading the PowerBus Data In Array.  See INT_CQ_ERR_INFO2 for details.</bit>
    <bit pos="5">Correctable ECC error detected while reading the PowerBus Data Out  Array. See INT_CQ_ERR_INFO2 for details.</bit>
    <bit pos="6">Uncorrectable ECC error detected while reading the PowerBus Data Out Array.  See INT_CQ_ERR_INFO2 for details.</bit>
    <bit pos="7">Correctable ECC error detected while consuming data on the AIB Data Bus.  See INT_CQ_ERR_INFO2 for details.</bit>
    <bit pos="8">Uncorrectable ECC error detected while consuming data on the AIB Data Bus.  See INT_CQ_ERR_INFO2 for details.</bit>
    <bit pos="9">Received an unsolicited master Combined Response - The master cResp tTag(0:11) matched my topology ID and unit ID, but tTag(12:19) pointed to TxIDs</bit>
    <bit pos="10">Received unsolicited PowerBus data - The rTag(0:11) of incoming PB data matched my topology ID and unit ID, but rTag(12:19) pointed to TxIDs that</bit>
    <bit pos="11">Parity error detected on AIB credit signals from PC</bit>
    <bit pos="12">Parity error detected on AIB credit available signals from PC</bit>
    <bit pos="13">Parity error detected on AIB credit signals from VC</bit>
    <bit pos="14">Parity error detected on AIB credit available signals from VC</bit>
    <bit pos="15">Parity error detected on AIB Command Control</bit>
    <bit pos="16">Parity error detected on AIB Command Bus</bit>
    <bit pos="17">Parity error detected on AIB Data Control</bit>
    <bit pos="18">Parity error detected on one of the following PowerBus interfaces (Rcmdx, cRespx, Data rtag).  See INT_CQ_ERR_INFO0 for details.</bit>
    <bit pos="19">Slave CI Store or CI Load to an improper location.  This includes a Read targeting a WO space, a Write targeting a RO space, or targeting reserved</bit>
    <bit pos="20">Slave CI Store or CI Load to an invalid Set Translation Table entry (that are associated with the NVPG, NVC, ESB and END BARs).</bit>
    <bit pos="21">Slave CI Store or CI Load (that targets the IC_BAR) with a size violation, alignment problem, or comes from an unsupported source.</bit>
    <bit pos="22">Slave CI Store or CI Load (that does not target the IC_BAR) with a size violation, alignment problem or comes from an unsupported source.</bit>
    <bit pos="23">Migration Register Table (MRT) access - invalid entry selected.</bit>
    <bit pos="24">Migration Register Table (MRT) access - The Table Size received in the AIB command is greater than the Target Page Size in the MRT entry.</bit>
    <bit pos="25">SCOM satellite error</bit>
    <bit pos="26">Topology ID Index Translation Table Entry Invalid - When INT initiates a master op (Read or Write) on the PowerBus, in determining the initial</bit>
    <bit pos="27">Master Write Queue has flagged a PowerBus operational hang</bit>
    <bit pos="28">Master Read Queue has flagged a PowerBus operational hang</bit>
    <bit pos="29">Master Interrupt Queue has flagged a PowerBus operational hang</bit>
    <bit pos="30">Master Read Queue has flagged a PowerBus data hang</bit>
    <bit pos="31">CI Store Queue has flagged a PowerBus data hang</bit>
    <bit pos="32">CI Load Queue has flagged an AIB data hang - Once a CI Load request has been sent on AIB, I use the PowerBus data hang timer mechanism (the</bit>
    <bit pos="33">Bad cResp received during a Master Write command.</bit>
    <bit pos="34">Bad cResp received during a Master Read command.</bit>
    <bit pos="35">Bad cResp received during a Master Interrupt command.</bit>
    <bit pos="36">A Master Read machine received cResp of abort_trm or abort_trm_ed. In addition to setting this error bit, the Read machine behaved as if the cResp was</bit>
    <bit pos="37">Master Interrupt Protocol Error - The PowerBus cResp to a master interrupt command was a response that should never happen.  In the P10 INT Workbook,</bit>
    <bit pos="38">Master Memory Op Targeted Secure Memory - VC or PC sent CQ a memory operation with the secure RA bit (bit 12) = 1 while SMF is enabled.</bit>
    <bit pos="39">AIB Fence Raised - This bit is set whenever CQ, PC, or VC assert &quot;AIB Fence&quot;.  This bit is useful to know if AIB fence was raised before another FIR</bit>
    <bit pos="40">Parity error detected on CQs configuration registers.</bit>
    <bit pos="41">Reserved</bit>
    <bit pos="42">Command Queue (FSM) severe error summary.  See INT_CQ_ERR_INFO3 for details.  This includes queue overflows and FSM parity errors.</bit>
    <bit pos="43">PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)</bit>
    <bit pos="44">PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)</bit>
    <bit pos="45">PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)</bit>
    <bit pos="46">PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)</bit>
    <bit pos="47">PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)</bit>
    <bit pos="48">PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)</bit>
    <bit pos="49">PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)</bit>
    <bit pos="50">PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)</bit>
    <bit pos="51">PC informational error summary, as indicated on pc_cq_info_error(0:3)</bit>
    <bit pos="52">PC informational error summary, as indicated on pc_cq_info_error(0:3)</bit>
    <bit pos="53">PC informational error summary, as indicated on pc_cq_info_error(0:3)</bit>
    <bit pos="54">PC informational error summary, as indicated on pc_cq_info_error(0:3)</bit>
    <bit pos="55">VC fatal error summary, as indicated on vc_cq_fatal_error(0:2)</bit>
    <bit pos="56">VC fatal error summary, as indicated on vc_cq_fatal_error(0:2)</bit>
    <bit pos="57">VC fatal error summary, as indicated on vc_cq_fatal_error(0:2)</bit>
    <bit pos="58">VC recoverable error summary, as indicated on vc_cq_recov_error(0:2)</bit>
    <bit pos="59">VC recoverable error summary, as indicated on vc_cq_recov_error(0:2)</bit>
    <bit pos="60">VC recoverable error summary, as indicated on vc_cq_recov_error(0:2)</bit>
    <bit pos="61">VC informational error summary, as indicated on vc_cq_info_error(0:2)</bit>
    <bit pos="62">VC informational error summary, as indicated on vc_cq_info_error(0:2)</bit>
    <bit pos="63">VC informational error summary, as indicated on vc_cq_info_error(0:2)</bit>
</attn_node>