Zane Shelley | b9ea93c | 2023-03-10 10:41:41 -0600 | [diff] [blame^] | 1 | { |
| 2 | "version": 1, |
| 3 | "model_ec": ["P10_10"], |
| 4 | "registers": { |
| 5 | "EQ_CORE_FIR": { |
| 6 | "instances": { |
| 7 | "0": "0x20028440", |
| 8 | "1": "0x20024440", |
| 9 | "2": "0x20022440", |
| 10 | "3": "0x20021440", |
| 11 | "4": "0x21028440", |
| 12 | "5": "0x21024440", |
| 13 | "6": "0x21022440", |
| 14 | "7": "0x21021440", |
| 15 | "8": "0x22028440", |
| 16 | "9": "0x22024440", |
| 17 | "10": "0x22022440", |
| 18 | "11": "0x22021440", |
| 19 | "12": "0x23028440", |
| 20 | "13": "0x23024440", |
| 21 | "14": "0x23022440", |
| 22 | "15": "0x23021440", |
| 23 | "16": "0x24028440", |
| 24 | "17": "0x24024440", |
| 25 | "18": "0x24022440", |
| 26 | "19": "0x24021440", |
| 27 | "20": "0x25028440", |
| 28 | "21": "0x25024440", |
| 29 | "22": "0x25022440", |
| 30 | "23": "0x25021440", |
| 31 | "24": "0x26028440", |
| 32 | "25": "0x26024440", |
| 33 | "26": "0x26022440", |
| 34 | "27": "0x26021440", |
| 35 | "28": "0x27028440", |
| 36 | "29": "0x27024440", |
| 37 | "30": "0x27022440", |
| 38 | "31": "0x27021440" |
| 39 | } |
| 40 | }, |
| 41 | "EQ_CORE_FIR_MASK": { |
| 42 | "instances": { |
| 43 | "0": "0x20028443", |
| 44 | "1": "0x20024443", |
| 45 | "2": "0x20022443", |
| 46 | "3": "0x20021443", |
| 47 | "4": "0x21028443", |
| 48 | "5": "0x21024443", |
| 49 | "6": "0x21022443", |
| 50 | "7": "0x21021443", |
| 51 | "8": "0x22028443", |
| 52 | "9": "0x22024443", |
| 53 | "10": "0x22022443", |
| 54 | "11": "0x22021443", |
| 55 | "12": "0x23028443", |
| 56 | "13": "0x23024443", |
| 57 | "14": "0x23022443", |
| 58 | "15": "0x23021443", |
| 59 | "16": "0x24028443", |
| 60 | "17": "0x24024443", |
| 61 | "18": "0x24022443", |
| 62 | "19": "0x24021443", |
| 63 | "20": "0x25028443", |
| 64 | "21": "0x25024443", |
| 65 | "22": "0x25022443", |
| 66 | "23": "0x25021443", |
| 67 | "24": "0x26028443", |
| 68 | "25": "0x26024443", |
| 69 | "26": "0x26022443", |
| 70 | "27": "0x26021443", |
| 71 | "28": "0x27028443", |
| 72 | "29": "0x27024443", |
| 73 | "30": "0x27022443", |
| 74 | "31": "0x27021443" |
| 75 | } |
| 76 | }, |
| 77 | "EQ_CORE_FIR_ACT0": { |
| 78 | "instances": { |
| 79 | "0": "0x20028446", |
| 80 | "1": "0x20024446", |
| 81 | "2": "0x20022446", |
| 82 | "3": "0x20021446", |
| 83 | "4": "0x21028446", |
| 84 | "5": "0x21024446", |
| 85 | "6": "0x21022446", |
| 86 | "7": "0x21021446", |
| 87 | "8": "0x22028446", |
| 88 | "9": "0x22024446", |
| 89 | "10": "0x22022446", |
| 90 | "11": "0x22021446", |
| 91 | "12": "0x23028446", |
| 92 | "13": "0x23024446", |
| 93 | "14": "0x23022446", |
| 94 | "15": "0x23021446", |
| 95 | "16": "0x24028446", |
| 96 | "17": "0x24024446", |
| 97 | "18": "0x24022446", |
| 98 | "19": "0x24021446", |
| 99 | "20": "0x25028446", |
| 100 | "21": "0x25024446", |
| 101 | "22": "0x25022446", |
| 102 | "23": "0x25021446", |
| 103 | "24": "0x26028446", |
| 104 | "25": "0x26024446", |
| 105 | "26": "0x26022446", |
| 106 | "27": "0x26021446", |
| 107 | "28": "0x27028446", |
| 108 | "29": "0x27024446", |
| 109 | "30": "0x27022446", |
| 110 | "31": "0x27021446" |
| 111 | } |
| 112 | }, |
| 113 | "EQ_CORE_FIR_ACT1": { |
| 114 | "instances": { |
| 115 | "0": "0x20028447", |
| 116 | "1": "0x20024447", |
| 117 | "2": "0x20022447", |
| 118 | "3": "0x20021447", |
| 119 | "4": "0x21028447", |
| 120 | "5": "0x21024447", |
| 121 | "6": "0x21022447", |
| 122 | "7": "0x21021447", |
| 123 | "8": "0x22028447", |
| 124 | "9": "0x22024447", |
| 125 | "10": "0x22022447", |
| 126 | "11": "0x22021447", |
| 127 | "12": "0x23028447", |
| 128 | "13": "0x23024447", |
| 129 | "14": "0x23022447", |
| 130 | "15": "0x23021447", |
| 131 | "16": "0x24028447", |
| 132 | "17": "0x24024447", |
| 133 | "18": "0x24022447", |
| 134 | "19": "0x24021447", |
| 135 | "20": "0x25028447", |
| 136 | "21": "0x25024447", |
| 137 | "22": "0x25022447", |
| 138 | "23": "0x25021447", |
| 139 | "24": "0x26028447", |
| 140 | "25": "0x26024447", |
| 141 | "26": "0x26022447", |
| 142 | "27": "0x26021447", |
| 143 | "28": "0x27028447", |
| 144 | "29": "0x27024447", |
| 145 | "30": "0x27022447", |
| 146 | "31": "0x27021447" |
| 147 | } |
| 148 | }, |
| 149 | "EQ_CORE_FIR_WOF": { |
| 150 | "instances": { |
| 151 | "0": "0x20028448", |
| 152 | "1": "0x20024448", |
| 153 | "2": "0x20022448", |
| 154 | "3": "0x20021448", |
| 155 | "4": "0x21028448", |
| 156 | "5": "0x21024448", |
| 157 | "6": "0x21022448", |
| 158 | "7": "0x21021448", |
| 159 | "8": "0x22028448", |
| 160 | "9": "0x22024448", |
| 161 | "10": "0x22022448", |
| 162 | "11": "0x22021448", |
| 163 | "12": "0x23028448", |
| 164 | "13": "0x23024448", |
| 165 | "14": "0x23022448", |
| 166 | "15": "0x23021448", |
| 167 | "16": "0x24028448", |
| 168 | "17": "0x24024448", |
| 169 | "18": "0x24022448", |
| 170 | "19": "0x24021448", |
| 171 | "20": "0x25028448", |
| 172 | "21": "0x25024448", |
| 173 | "22": "0x25022448", |
| 174 | "23": "0x25021448", |
| 175 | "24": "0x26028448", |
| 176 | "25": "0x26024448", |
| 177 | "26": "0x26022448", |
| 178 | "27": "0x26021448", |
| 179 | "28": "0x27028448", |
| 180 | "29": "0x27024448", |
| 181 | "30": "0x27022448", |
| 182 | "31": "0x27021448" |
| 183 | } |
| 184 | } |
| 185 | }, |
| 186 | "isolation_nodes": { |
| 187 | "EQ_CORE_FIR": { |
| 188 | "instances": [ |
| 189 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, |
| 190 | 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 |
| 191 | ], |
| 192 | "rules": [ |
| 193 | { |
| 194 | "attn_type": ["CS"], |
| 195 | "node_inst": [ |
| 196 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, |
| 197 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, |
| 198 | 30, 31 |
| 199 | ], |
| 200 | "expr": { |
| 201 | "expr_type": "and", |
| 202 | "exprs": [ |
| 203 | { |
| 204 | "expr_type": "reg", |
| 205 | "reg_name": "EQ_CORE_FIR" |
| 206 | }, |
| 207 | { |
| 208 | "expr_type": "not", |
| 209 | "expr": { |
| 210 | "expr_type": "reg", |
| 211 | "reg_name": "EQ_CORE_FIR_MASK" |
| 212 | } |
| 213 | }, |
| 214 | { |
| 215 | "expr_type": "not", |
| 216 | "expr": { |
| 217 | "expr_type": "reg", |
| 218 | "reg_name": "EQ_CORE_FIR_ACT0" |
| 219 | } |
| 220 | }, |
| 221 | { |
| 222 | "expr_type": "not", |
| 223 | "expr": { |
| 224 | "expr_type": "reg", |
| 225 | "reg_name": "EQ_CORE_FIR_ACT1" |
| 226 | } |
| 227 | } |
| 228 | ] |
| 229 | } |
| 230 | }, |
| 231 | { |
| 232 | "attn_type": ["RE"], |
| 233 | "node_inst": [ |
| 234 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, |
| 235 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, |
| 236 | 30, 31 |
| 237 | ], |
| 238 | "expr": { |
| 239 | "expr_type": "and", |
| 240 | "exprs": [ |
| 241 | { |
| 242 | "expr_type": "reg", |
| 243 | "reg_name": "EQ_CORE_FIR_WOF" |
| 244 | }, |
| 245 | { |
| 246 | "expr_type": "not", |
| 247 | "expr": { |
| 248 | "expr_type": "reg", |
| 249 | "reg_name": "EQ_CORE_FIR_MASK" |
| 250 | } |
| 251 | }, |
| 252 | { |
| 253 | "expr_type": "not", |
| 254 | "expr": { |
| 255 | "expr_type": "reg", |
| 256 | "reg_name": "EQ_CORE_FIR_ACT0" |
| 257 | } |
| 258 | }, |
| 259 | { |
| 260 | "expr_type": "reg", |
| 261 | "reg_name": "EQ_CORE_FIR_ACT1" |
| 262 | } |
| 263 | ] |
| 264 | } |
| 265 | }, |
| 266 | { |
| 267 | "attn_type": ["UCS"], |
| 268 | "node_inst": [ |
| 269 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, |
| 270 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, |
| 271 | 30, 31 |
| 272 | ], |
| 273 | "expr": { |
| 274 | "expr_type": "and", |
| 275 | "exprs": [ |
| 276 | { |
| 277 | "expr_type": "reg", |
| 278 | "reg_name": "EQ_CORE_FIR" |
| 279 | }, |
| 280 | { |
| 281 | "expr_type": "not", |
| 282 | "expr": { |
| 283 | "expr_type": "reg", |
| 284 | "reg_name": "EQ_CORE_FIR_MASK" |
| 285 | } |
| 286 | }, |
| 287 | { |
| 288 | "expr_type": "reg", |
| 289 | "reg_name": "EQ_CORE_FIR_ACT0" |
| 290 | }, |
| 291 | { |
| 292 | "expr_type": "reg", |
| 293 | "reg_name": "EQ_CORE_FIR_ACT1" |
| 294 | } |
| 295 | ] |
| 296 | } |
| 297 | } |
| 298 | ], |
| 299 | "bits": { |
| 300 | "0": { |
| 301 | "desc": "IFU SRAM recoverable error (ICACHE parity error, etc)" |
| 302 | }, |
| 303 | "1": { |
| 304 | "desc": "TC checkstop" |
| 305 | }, |
| 306 | "2": { |
| 307 | "desc": "IFU RegFile recoverable error" |
| 308 | }, |
| 309 | "3": { |
| 310 | "desc": "IFU RegFile core checkstop" |
| 311 | }, |
| 312 | "4": { |
| 313 | "desc": "IFU logic recoverable error" |
| 314 | }, |
| 315 | "5": { |
| 316 | "desc": "IFU logic core checkstop" |
| 317 | }, |
| 318 | "6": { |
| 319 | "desc": "reserved" |
| 320 | }, |
| 321 | "7": { |
| 322 | "desc": "VSU Inference Accumulator recoverable error" |
| 323 | }, |
| 324 | "8": { |
| 325 | "desc": "Recovery core checkstop" |
| 326 | }, |
| 327 | "9": { |
| 328 | "desc": "VSU Slice Targeted File (STF) recoverable error" |
| 329 | }, |
| 330 | "10": { |
| 331 | "desc": "reserved" |
| 332 | }, |
| 333 | "11": { |
| 334 | "desc": "ISU logic recoverable error" |
| 335 | }, |
| 336 | "12": { |
| 337 | "desc": "ISU logic core checkstop" |
| 338 | }, |
| 339 | "13": { |
| 340 | "desc": "ISU recoverable if not in MT window" |
| 341 | }, |
| 342 | "14": { |
| 343 | "desc": "MCHK received while ME=0 - non recoverable" |
| 344 | }, |
| 345 | "15": { |
| 346 | "desc": "UE from L2" |
| 347 | }, |
| 348 | "16": { |
| 349 | "desc": "Number of UEs from L2 above threshold" |
| 350 | }, |
| 351 | "17": { |
| 352 | "desc": "UE on CI load" |
| 353 | }, |
| 354 | "18": { |
| 355 | "desc": "MMU TLB parity recoverable error" |
| 356 | }, |
| 357 | "19": { |
| 358 | "desc": "MMU SLB parity recoverable error" |
| 359 | }, |
| 360 | "20": { |
| 361 | "desc": "reserved" |
| 362 | }, |
| 363 | "21": { |
| 364 | "desc": "MMU CXT recoverable error" |
| 365 | }, |
| 366 | "22": { |
| 367 | "desc": "MMU logic core checkstop" |
| 368 | }, |
| 369 | "23": { |
| 370 | "desc": "MMU system checkstop" |
| 371 | }, |
| 372 | "24": { |
| 373 | "desc": "VSU logic recoverable error" |
| 374 | }, |
| 375 | "25": { |
| 376 | "desc": "VSU logic core checkstop" |
| 377 | }, |
| 378 | "26": { |
| 379 | "desc": "Thread in maintenance mode and receives recovery request" |
| 380 | }, |
| 381 | "27": { |
| 382 | "desc": "reserved" |
| 383 | }, |
| 384 | "28": { |
| 385 | "desc": "PC system checkstop - Recoverable error received when recovery disabled" |
| 386 | }, |
| 387 | "29": { |
| 388 | "desc": "LSU SRAM recoverable error (DCACHE parity error, ERAT parity error, etc)" |
| 389 | }, |
| 390 | "30": { |
| 391 | "desc": "LSU set deleted" |
| 392 | }, |
| 393 | "31": { |
| 394 | "desc": "LSU RegFile recoverable error" |
| 395 | }, |
| 396 | "32": { |
| 397 | "desc": "LSU RegFile core checkstop" |
| 398 | }, |
| 399 | "33": { |
| 400 | "desc": "MMU TLB multi hit error occurred" |
| 401 | }, |
| 402 | "34": { |
| 403 | "desc": "MMU SLB multi hit error occurred" |
| 404 | }, |
| 405 | "35": { |
| 406 | "desc": "LSU ERAT multi hit error occurred" |
| 407 | }, |
| 408 | "36": { |
| 409 | "desc": "PC forward progress error" |
| 410 | }, |
| 411 | "37": { |
| 412 | "desc": "LSU logic recoverable error" |
| 413 | }, |
| 414 | "38": { |
| 415 | "desc": "LSU logic core checkstop" |
| 416 | }, |
| 417 | "39": { |
| 418 | "desc": "reserved" |
| 419 | }, |
| 420 | "40": { |
| 421 | "desc": "reserved" |
| 422 | }, |
| 423 | "41": { |
| 424 | "desc": "LSU system checkstop" |
| 425 | }, |
| 426 | "42": { |
| 427 | "desc": "reserved" |
| 428 | }, |
| 429 | "43": { |
| 430 | "desc": "PC thread hang recoverable error" |
| 431 | }, |
| 432 | "44": { |
| 433 | "desc": "reserved" |
| 434 | }, |
| 435 | "45": { |
| 436 | "desc": "PC logic checkstop" |
| 437 | }, |
| 438 | "46": { |
| 439 | "desc": "PC TimeBase Facility checkstop" |
| 440 | }, |
| 441 | "47": { |
| 442 | "desc": "PC TimeBase Facility checkstop" |
| 443 | }, |
| 444 | "48": { |
| 445 | "desc": "reserved" |
| 446 | }, |
| 447 | "49": { |
| 448 | "desc": "reserved" |
| 449 | }, |
| 450 | "50": { |
| 451 | "desc": "reserved" |
| 452 | }, |
| 453 | "51": { |
| 454 | "desc": "reserved" |
| 455 | }, |
| 456 | "52": { |
| 457 | "desc": "Hang Recovery Failed" |
| 458 | }, |
| 459 | "53": { |
| 460 | "desc": "Core Hang detected" |
| 461 | }, |
| 462 | "54": { |
| 463 | "desc": "reserved" |
| 464 | }, |
| 465 | "55": { |
| 466 | "desc": "Nest Hang detected" |
| 467 | }, |
| 468 | "56": { |
| 469 | "desc": "Other Core Chiplet recoverable error" |
| 470 | }, |
| 471 | "57": { |
| 472 | "desc": "Other Core Chiplet core checkstop" |
| 473 | }, |
| 474 | "58": { |
| 475 | "desc": "Other Core Chiplet system checkstop" |
| 476 | }, |
| 477 | "59": { |
| 478 | "desc": "SCOM satellite error detected" |
| 479 | }, |
| 480 | "60": { |
| 481 | "desc": "Debug Trigger error inject" |
| 482 | }, |
| 483 | "61": { |
| 484 | "desc": "SCOM or Firmware recoverable error inject" |
| 485 | }, |
| 486 | "62": { |
| 487 | "desc": "Firmware checkstop error inject" |
| 488 | }, |
| 489 | "63": { |
| 490 | "desc": "PHYP checkstop via SPRC/SPRD" |
| 491 | } |
| 492 | }, |
| 493 | "capture_groups": [ |
| 494 | { |
| 495 | "group_name": "EQ_CORE_FIR", |
| 496 | "group_inst": { |
| 497 | "0": 0, |
| 498 | "1": 1, |
| 499 | "2": 2, |
| 500 | "3": 3, |
| 501 | "4": 4, |
| 502 | "5": 5, |
| 503 | "6": 6, |
| 504 | "7": 7, |
| 505 | "8": 8, |
| 506 | "9": 9, |
| 507 | "10": 10, |
| 508 | "11": 11, |
| 509 | "12": 12, |
| 510 | "13": 13, |
| 511 | "14": 14, |
| 512 | "15": 15, |
| 513 | "16": 16, |
| 514 | "17": 17, |
| 515 | "18": 18, |
| 516 | "19": 19, |
| 517 | "20": 20, |
| 518 | "21": 21, |
| 519 | "22": 22, |
| 520 | "23": 23, |
| 521 | "24": 24, |
| 522 | "25": 25, |
| 523 | "26": 26, |
| 524 | "27": 27, |
| 525 | "28": 28, |
| 526 | "29": 29, |
| 527 | "30": 30, |
| 528 | "31": 31 |
| 529 | } |
| 530 | } |
| 531 | ] |
| 532 | } |
| 533 | } |
| 534 | } |