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gerrit.openbmc.org / openbmc / openpower-libhei / b9ea93c5cb15b8fed0f44780f9b2a6a0ffe34f28 / . / chip_data / p10_10 / node_eq_l2_fir.json
blob: e69146b2d2bbabd32f0ccc0053f7a3d1285443ef [file] [log] [blame]
Zane Shelleyb9ea93c2023-03-10 10:41:41 -0600[diff] [blame^]1{
2 "version": 1,
3 "model_ec": ["P10_10"],
4 "registers": {
5 "EQ_L2_FIR": {
6 "instances": {
7 "0": "0x20028000",
8 "1": "0x20024000",
9 "2": "0x20022000",
10 "3": "0x20021000",
11 "4": "0x21028000",
12 "5": "0x21024000",
13 "6": "0x21022000",
14 "7": "0x21021000",
15 "8": "0x22028000",
16 "9": "0x22024000",
17 "10": "0x22022000",
18 "11": "0x22021000",
19 "12": "0x23028000",
20 "13": "0x23024000",
21 "14": "0x23022000",
22 "15": "0x23021000",
23 "16": "0x24028000",
24 "17": "0x24024000",
25 "18": "0x24022000",
26 "19": "0x24021000",
27 "20": "0x25028000",
28 "21": "0x25024000",
29 "22": "0x25022000",
30 "23": "0x25021000",
31 "24": "0x26028000",
32 "25": "0x26024000",
33 "26": "0x26022000",
34 "27": "0x26021000",
35 "28": "0x27028000",
36 "29": "0x27024000",
37 "30": "0x27022000",
38 "31": "0x27021000"
39 }
40 },
41 "EQ_L2_FIR_MASK": {
42 "instances": {
43 "0": "0x20028003",
44 "1": "0x20024003",
45 "2": "0x20022003",
46 "3": "0x20021003",
47 "4": "0x21028003",
48 "5": "0x21024003",
49 "6": "0x21022003",
50 "7": "0x21021003",
51 "8": "0x22028003",
52 "9": "0x22024003",
53 "10": "0x22022003",
54 "11": "0x22021003",
55 "12": "0x23028003",
56 "13": "0x23024003",
57 "14": "0x23022003",
58 "15": "0x23021003",
59 "16": "0x24028003",
60 "17": "0x24024003",
61 "18": "0x24022003",
62 "19": "0x24021003",
63 "20": "0x25028003",
64 "21": "0x25024003",
65 "22": "0x25022003",
66 "23": "0x25021003",
67 "24": "0x26028003",
68 "25": "0x26024003",
69 "26": "0x26022003",
70 "27": "0x26021003",
71 "28": "0x27028003",
72 "29": "0x27024003",
73 "30": "0x27022003",
74 "31": "0x27021003"
75 }
76 },
77 "EQ_L2_FIR_ACT0": {
78 "instances": {
79 "0": "0x20028006",
80 "1": "0x20024006",
81 "2": "0x20022006",
82 "3": "0x20021006",
83 "4": "0x21028006",
84 "5": "0x21024006",
85 "6": "0x21022006",
86 "7": "0x21021006",
87 "8": "0x22028006",
88 "9": "0x22024006",
89 "10": "0x22022006",
90 "11": "0x22021006",
91 "12": "0x23028006",
92 "13": "0x23024006",
93 "14": "0x23022006",
94 "15": "0x23021006",
95 "16": "0x24028006",
96 "17": "0x24024006",
97 "18": "0x24022006",
98 "19": "0x24021006",
99 "20": "0x25028006",
100 "21": "0x25024006",
101 "22": "0x25022006",
102 "23": "0x25021006",
103 "24": "0x26028006",
104 "25": "0x26024006",
105 "26": "0x26022006",
106 "27": "0x26021006",
107 "28": "0x27028006",
108 "29": "0x27024006",
109 "30": "0x27022006",
110 "31": "0x27021006"
111 }
112 },
113 "EQ_L2_FIR_ACT1": {
114 "instances": {
115 "0": "0x20028007",
116 "1": "0x20024007",
117 "2": "0x20022007",
118 "3": "0x20021007",
119 "4": "0x21028007",
120 "5": "0x21024007",
121 "6": "0x21022007",
122 "7": "0x21021007",
123 "8": "0x22028007",
124 "9": "0x22024007",
125 "10": "0x22022007",
126 "11": "0x22021007",
127 "12": "0x23028007",
128 "13": "0x23024007",
129 "14": "0x23022007",
130 "15": "0x23021007",
131 "16": "0x24028007",
132 "17": "0x24024007",
133 "18": "0x24022007",
134 "19": "0x24021007",
135 "20": "0x25028007",
136 "21": "0x25024007",
137 "22": "0x25022007",
138 "23": "0x25021007",
139 "24": "0x26028007",
140 "25": "0x26024007",
141 "26": "0x26022007",
142 "27": "0x26021007",
143 "28": "0x27028007",
144 "29": "0x27024007",
145 "30": "0x27022007",
146 "31": "0x27021007"
147 }
148 }
149 },
150 "isolation_nodes": {
151 "EQ_L2_FIR": {
152 "instances": [
153 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
154 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
155 ],
156 "rules": [
157 {
158 "attn_type": ["CS"],
159 "node_inst": [
160 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
161 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
162 30, 31
163 ],
164 "expr": {
165 "expr_type": "and",
166 "exprs": [
167 {
168 "expr_type": "reg",
169 "reg_name": "EQ_L2_FIR"
170 },
171 {
172 "expr_type": "not",
173 "expr": {
174 "expr_type": "reg",
175 "reg_name": "EQ_L2_FIR_MASK"
176 }
177 },
178 {
179 "expr_type": "not",
180 "expr": {
181 "expr_type": "reg",
182 "reg_name": "EQ_L2_FIR_ACT0"
183 }
184 },
185 {
186 "expr_type": "not",
187 "expr": {
188 "expr_type": "reg",
189 "reg_name": "EQ_L2_FIR_ACT1"
190 }
191 }
192 ]
193 }
194 },
195 {
196 "attn_type": ["RE"],
197 "node_inst": [
198 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
199 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
200 30, 31
201 ],
202 "expr": {
203 "expr_type": "and",
204 "exprs": [
205 {
206 "expr_type": "reg",
207 "reg_name": "EQ_L2_FIR"
208 },
209 {
210 "expr_type": "not",
211 "expr": {
212 "expr_type": "reg",
213 "reg_name": "EQ_L2_FIR_MASK"
214 }
215 },
216 {
217 "expr_type": "not",
218 "expr": {
219 "expr_type": "reg",
220 "reg_name": "EQ_L2_FIR_ACT0"
221 }
222 },
223 {
224 "expr_type": "reg",
225 "reg_name": "EQ_L2_FIR_ACT1"
226 }
227 ]
228 }
229 }
230 ],
231 "bits": {
232 "0": {
233 "desc": "L2 cache read CE"
234 },
235 "1": {
236 "desc": "L2 cache read UE"
237 },
238 "2": {
239 "desc": "L2 cache read SUE"
240 },
241 "3": {
242 "desc": "Hw directory initiated line delete"
243 },
244 "4": {
245 "desc": "UE or SUE detected by on modified line"
246 },
247 "5": {
248 "desc": "UE or SUE detected on non-modified line"
249 },
250 "6": {
251 "desc": "L2 directory read CE"
252 },
253 "7": {
254 "desc": "L2 directory read UE"
255 },
256 "8": {
257 "desc": "L2 directory CE due to stuck bit"
258 },
259 "9": {
260 "desc": "L2 directory stuck bit CE repair failed"
261 },
262 "10": {
263 "desc": "reserved"
264 },
265 "11": {
266 "desc": "LRU read error detected"
267 },
268 "12": {
269 "desc": "RC timed out waiting for powerbus to return data"
270 },
271 "13": {
272 "desc": "NCU timed out waiting for powerbus to return data"
273 },
274 "14": {
275 "desc": "Internal h/w control error"
276 },
277 "15": {
278 "desc": "LRU all members in a class line deleted"
279 },
280 "16": {
281 "desc": "Cache Inhibited Ld/St hit a line in the L2 cache"
282 },
283 "17": {
284 "desc": "(RC) load received pb cresp addr error"
285 },
286 "18": {
287 "desc": "(RC) store received pb cresp addr error"
288 },
289 "19": {
290 "desc": "RC incoming Power Bus data had a CE error"
291 },
292 "20": {
293 "desc": "RC incoming Power Bus data had a UE error"
294 },
295 "21": {
296 "desc": "RC incoming Power Bus data had a SUE error"
297 },
298 "22": {
299 "desc": "Targetted nodal request got rty_inc cresp"
300 },
301 "23": {
302 "desc": "RC fabric op Ld cresp addr error for hyp"
303 },
304 "24": {
305 "desc": "RCDAT read parity error"
306 },
307 "25": {
308 "desc": "L2 castout or CN cresp addr err"
309 },
310 "26": {
311 "desc": "LVDIR took a parity error"
312 },
313 "27": {
314 "desc": "Bad topology table config software error"
315 },
316 "28": {
317 "desc": "Darn timed out waiting for data"
318 },
319 "29": {
320 "desc": "Early hang in L2"
321 },
322 "30": {
323 "desc": "Unexpected cast-out or push during chip_contained"
324 },
325 "31": {
326 "desc": "reserved"
327 },
328 "32": {
329 "desc": "Time out during PEC sequence trying to correct l2dir error"
330 },
331 "33": {
332 "desc": "reserved"
333 },
334 "34": {
335 "desc": "reserved"
336 },
337 "35": {
338 "desc": "reserved"
339 },
340 "36": {
341 "desc": "Cache CE and UE in short time period"
342 },
343 "37": {
344 "desc": "reserved"
345 },
346 "38": {
347 "desc": "reserved"
348 },
349 "39": {
350 "desc": "reserved"
351 }
352 },
353 "capture_groups": [
354 {
355 "group_name": "EQ_L2_FIR",
356 "group_inst": {
357 "0": 0,
358 "1": 1,
359 "2": 2,
360 "3": 3,
361 "4": 4,
362 "5": 5,
363 "6": 6,
364 "7": 7,
365 "8": 8,
366 "9": 9,
367 "10": 10,
368 "11": 11,
369 "12": 12,
370 "13": 13,
371 "14": 14,
372 "15": 15,
373 "16": 16,
374 "17": 17,
375 "18": 18,
376 "19": 19,
377 "20": 20,
378 "21": 21,
379 "22": 22,
380 "23": 23,
381 "24": 24,
382 "25": 25,
383 "26": 26,
384 "27": 27,
385 "28": 28,
386 "29": 29,
387 "30": 30,
388 "31": 31
389 }
390 }
391 ]
392 }
393 }
394}