Zane Shelley | b1749b8 | 2021-10-02 22:23:06 -0500 | [diff] [blame] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
| 2 | <attn_node model_ec="P10_10,P10_20" name="IOHS_DLP_FIR_SMP" reg_type="SCOM"> |
| 3 | <local_fir config="W" name="IOHS_DLP_FIR"> |
| 4 | <instance addr="0x18011000" reg_inst="0"/> |
| 5 | <instance addr="0x19011000" reg_inst="1"/> |
| 6 | <instance addr="0x1A011000" reg_inst="2"/> |
| 7 | <instance addr="0x1B011000" reg_inst="3"/> |
| 8 | <instance addr="0x1C011000" reg_inst="4"/> |
| 9 | <instance addr="0x1D011000" reg_inst="5"/> |
| 10 | <instance addr="0x1E011000" reg_inst="6"/> |
| 11 | <instance addr="0x1F011000" reg_inst="7"/> |
| 12 | <action attn_type="CS" config="00"/> |
| 13 | <action attn_type="RE" config="01"/> |
| 14 | <action attn_type="SPA" config="10"/> |
| 15 | </local_fir> |
Zane Shelley | bd48bf9 | 2022-06-11 11:07:14 -0500 | [diff] [blame^] | 16 | <register name="IOHS_DLP_CONFIG"> |
| 17 | <instance addr="0x1801100A" reg_inst="0"/> |
| 18 | <instance addr="0x1901100A" reg_inst="1"/> |
| 19 | <instance addr="0x1A01100A" reg_inst="2"/> |
| 20 | <instance addr="0x1B01100A" reg_inst="3"/> |
| 21 | <instance addr="0x1C01100A" reg_inst="4"/> |
| 22 | <instance addr="0x1D01100A" reg_inst="5"/> |
| 23 | <instance addr="0x1E01100A" reg_inst="6"/> |
| 24 | <instance addr="0x1F01100A" reg_inst="7"/> |
| 25 | </register> |
| 26 | <register name="IOHS_DLP_CONTROL"> |
| 27 | <instance addr="0x1801100B" reg_inst="0"/> |
| 28 | <instance addr="0x1901100B" reg_inst="1"/> |
| 29 | <instance addr="0x1A01100B" reg_inst="2"/> |
| 30 | <instance addr="0x1B01100B" reg_inst="3"/> |
| 31 | <instance addr="0x1C01100B" reg_inst="4"/> |
| 32 | <instance addr="0x1D01100B" reg_inst="5"/> |
| 33 | <instance addr="0x1E01100B" reg_inst="6"/> |
| 34 | <instance addr="0x1F01100B" reg_inst="7"/> |
| 35 | </register> |
| 36 | <register name="IOHS_DLP_PHY_CONFIG"> |
Zane Shelley | b1749b8 | 2021-10-02 22:23:06 -0500 | [diff] [blame] | 37 | <instance addr="0x1801100C" reg_inst="0"/> |
| 38 | <instance addr="0x1901100C" reg_inst="1"/> |
| 39 | <instance addr="0x1A01100C" reg_inst="2"/> |
| 40 | <instance addr="0x1B01100C" reg_inst="3"/> |
| 41 | <instance addr="0x1C01100C" reg_inst="4"/> |
| 42 | <instance addr="0x1D01100C" reg_inst="5"/> |
| 43 | <instance addr="0x1E01100C" reg_inst="6"/> |
| 44 | <instance addr="0x1F01100C" reg_inst="7"/> |
| 45 | </register> |
Zane Shelley | bd48bf9 | 2022-06-11 11:07:14 -0500 | [diff] [blame^] | 46 | <register name="IOHS_DLP_SEC_CONFIG"> |
| 47 | <instance addr="0x1801100D" reg_inst="0"/> |
| 48 | <instance addr="0x1901100D" reg_inst="1"/> |
| 49 | <instance addr="0x1A01100D" reg_inst="2"/> |
| 50 | <instance addr="0x1B01100D" reg_inst="3"/> |
| 51 | <instance addr="0x1C01100D" reg_inst="4"/> |
| 52 | <instance addr="0x1D01100D" reg_inst="5"/> |
| 53 | <instance addr="0x1E01100D" reg_inst="6"/> |
| 54 | <instance addr="0x1F01100D" reg_inst="7"/> |
| 55 | </register> |
| 56 | <register name="IOHS_DLP_OPTICAL_CONFIG"> |
| 57 | <instance addr="0x1801100F" reg_inst="0"/> |
| 58 | <instance addr="0x1901100F" reg_inst="1"/> |
| 59 | <instance addr="0x1A01100F" reg_inst="2"/> |
| 60 | <instance addr="0x1B01100F" reg_inst="3"/> |
| 61 | <instance addr="0x1C01100F" reg_inst="4"/> |
| 62 | <instance addr="0x1D01100F" reg_inst="5"/> |
| 63 | <instance addr="0x1E01100F" reg_inst="6"/> |
| 64 | <instance addr="0x1F01100F" reg_inst="7"/> |
| 65 | </register> |
Zane Shelley | b1749b8 | 2021-10-02 22:23:06 -0500 | [diff] [blame] | 66 | <register name="IOHS_DLP_LINK0_TX_LANE_CONTROL"> |
| 67 | <instance addr="0x18011010" reg_inst="0"/> |
| 68 | <instance addr="0x19011010" reg_inst="1"/> |
| 69 | <instance addr="0x1A011010" reg_inst="2"/> |
| 70 | <instance addr="0x1B011010" reg_inst="3"/> |
| 71 | <instance addr="0x1C011010" reg_inst="4"/> |
| 72 | <instance addr="0x1D011010" reg_inst="5"/> |
| 73 | <instance addr="0x1E011010" reg_inst="6"/> |
| 74 | <instance addr="0x1F011010" reg_inst="7"/> |
| 75 | </register> |
| 76 | <register name="IOHS_DLP_LINK1_TX_LANE_CONTROL"> |
| 77 | <instance addr="0x18011011" reg_inst="0"/> |
| 78 | <instance addr="0x19011011" reg_inst="1"/> |
| 79 | <instance addr="0x1A011011" reg_inst="2"/> |
| 80 | <instance addr="0x1B011011" reg_inst="3"/> |
| 81 | <instance addr="0x1C011011" reg_inst="4"/> |
| 82 | <instance addr="0x1D011011" reg_inst="5"/> |
| 83 | <instance addr="0x1E011011" reg_inst="6"/> |
| 84 | <instance addr="0x1F011011" reg_inst="7"/> |
| 85 | </register> |
| 86 | <register name="IOHS_DLP_LINK0_RX_LANE_CONTROL"> |
| 87 | <instance addr="0x18011012" reg_inst="0"/> |
| 88 | <instance addr="0x19011012" reg_inst="1"/> |
| 89 | <instance addr="0x1A011012" reg_inst="2"/> |
| 90 | <instance addr="0x1B011012" reg_inst="3"/> |
| 91 | <instance addr="0x1C011012" reg_inst="4"/> |
| 92 | <instance addr="0x1D011012" reg_inst="5"/> |
| 93 | <instance addr="0x1E011012" reg_inst="6"/> |
| 94 | <instance addr="0x1F011012" reg_inst="7"/> |
| 95 | </register> |
| 96 | <register name="IOHS_DLP_LINK1_RX_LANE_CONTROL"> |
| 97 | <instance addr="0x18011013" reg_inst="0"/> |
| 98 | <instance addr="0x19011013" reg_inst="1"/> |
| 99 | <instance addr="0x1A011013" reg_inst="2"/> |
| 100 | <instance addr="0x1B011013" reg_inst="3"/> |
| 101 | <instance addr="0x1C011013" reg_inst="4"/> |
| 102 | <instance addr="0x1D011013" reg_inst="5"/> |
| 103 | <instance addr="0x1E011013" reg_inst="6"/> |
| 104 | <instance addr="0x1F011013" reg_inst="7"/> |
| 105 | </register> |
| 106 | <register name="IOHS_DLP_LINK0_INFO"> |
| 107 | <instance addr="0x18011014" reg_inst="0"/> |
| 108 | <instance addr="0x19011014" reg_inst="1"/> |
| 109 | <instance addr="0x1A011014" reg_inst="2"/> |
| 110 | <instance addr="0x1B011014" reg_inst="3"/> |
| 111 | <instance addr="0x1C011014" reg_inst="4"/> |
| 112 | <instance addr="0x1D011014" reg_inst="5"/> |
| 113 | <instance addr="0x1E011014" reg_inst="6"/> |
| 114 | <instance addr="0x1F011014" reg_inst="7"/> |
| 115 | </register> |
| 116 | <register name="IOHS_DLP_LINK1_INFO"> |
| 117 | <instance addr="0x18011015" reg_inst="0"/> |
| 118 | <instance addr="0x19011015" reg_inst="1"/> |
| 119 | <instance addr="0x1A011015" reg_inst="2"/> |
| 120 | <instance addr="0x1B011015" reg_inst="3"/> |
| 121 | <instance addr="0x1C011015" reg_inst="4"/> |
| 122 | <instance addr="0x1D011015" reg_inst="5"/> |
| 123 | <instance addr="0x1E011015" reg_inst="6"/> |
| 124 | <instance addr="0x1F011015" reg_inst="7"/> |
| 125 | </register> |
| 126 | <register name="IOHS_DLP_LINK0_ERROR_STATUS"> |
| 127 | <instance addr="0x18011016" reg_inst="0"/> |
| 128 | <instance addr="0x19011016" reg_inst="1"/> |
| 129 | <instance addr="0x1A011016" reg_inst="2"/> |
| 130 | <instance addr="0x1B011016" reg_inst="3"/> |
| 131 | <instance addr="0x1C011016" reg_inst="4"/> |
| 132 | <instance addr="0x1D011016" reg_inst="5"/> |
| 133 | <instance addr="0x1E011016" reg_inst="6"/> |
| 134 | <instance addr="0x1F011016" reg_inst="7"/> |
| 135 | </register> |
| 136 | <register name="IOHS_DLP_LINK1_ERROR_STATUS"> |
| 137 | <instance addr="0x18011017" reg_inst="0"/> |
| 138 | <instance addr="0x19011017" reg_inst="1"/> |
| 139 | <instance addr="0x1A011017" reg_inst="2"/> |
| 140 | <instance addr="0x1B011017" reg_inst="3"/> |
| 141 | <instance addr="0x1C011017" reg_inst="4"/> |
| 142 | <instance addr="0x1D011017" reg_inst="5"/> |
| 143 | <instance addr="0x1E011017" reg_inst="6"/> |
| 144 | <instance addr="0x1F011017" reg_inst="7"/> |
| 145 | </register> |
| 146 | <register name="IOHS_DLP_REPLAY_THRESHOLD"> |
| 147 | <instance addr="0x18011018" reg_inst="0"/> |
| 148 | <instance addr="0x19011018" reg_inst="1"/> |
| 149 | <instance addr="0x1A011018" reg_inst="2"/> |
| 150 | <instance addr="0x1B011018" reg_inst="3"/> |
| 151 | <instance addr="0x1C011018" reg_inst="4"/> |
| 152 | <instance addr="0x1D011018" reg_inst="5"/> |
| 153 | <instance addr="0x1E011018" reg_inst="6"/> |
| 154 | <instance addr="0x1F011018" reg_inst="7"/> |
| 155 | </register> |
| 156 | <register name="IOHS_DLP_SL_ECC_THRESHOLD"> |
| 157 | <instance addr="0x18011019" reg_inst="0"/> |
| 158 | <instance addr="0x19011019" reg_inst="1"/> |
| 159 | <instance addr="0x1A011019" reg_inst="2"/> |
| 160 | <instance addr="0x1B011019" reg_inst="3"/> |
| 161 | <instance addr="0x1C011019" reg_inst="4"/> |
| 162 | <instance addr="0x1D011019" reg_inst="5"/> |
| 163 | <instance addr="0x1E011019" reg_inst="6"/> |
| 164 | <instance addr="0x1F011019" reg_inst="7"/> |
| 165 | </register> |
| 166 | <register name="IOHS_DLP_LINK0_SYN_CAPTURE"> |
| 167 | <instance addr="0x18011022" reg_inst="0"/> |
| 168 | <instance addr="0x19011022" reg_inst="1"/> |
| 169 | <instance addr="0x1A011022" reg_inst="2"/> |
| 170 | <instance addr="0x1B011022" reg_inst="3"/> |
| 171 | <instance addr="0x1C011022" reg_inst="4"/> |
| 172 | <instance addr="0x1D011022" reg_inst="5"/> |
| 173 | <instance addr="0x1E011022" reg_inst="6"/> |
| 174 | <instance addr="0x1F011022" reg_inst="7"/> |
| 175 | </register> |
| 176 | <register name="IOHS_DLP_LINK1_SYN_CAPTURE"> |
| 177 | <instance addr="0x18011023" reg_inst="0"/> |
| 178 | <instance addr="0x19011023" reg_inst="1"/> |
| 179 | <instance addr="0x1A011023" reg_inst="2"/> |
| 180 | <instance addr="0x1B011023" reg_inst="3"/> |
| 181 | <instance addr="0x1C011023" reg_inst="4"/> |
| 182 | <instance addr="0x1D011023" reg_inst="5"/> |
| 183 | <instance addr="0x1E011023" reg_inst="6"/> |
| 184 | <instance addr="0x1F011023" reg_inst="7"/> |
| 185 | </register> |
| 186 | <register name="IOHS_DLP_LINK0_EDPL_STATUS"> |
| 187 | <instance addr="0x18011024" reg_inst="0"/> |
| 188 | <instance addr="0x19011024" reg_inst="1"/> |
| 189 | <instance addr="0x1A011024" reg_inst="2"/> |
| 190 | <instance addr="0x1B011024" reg_inst="3"/> |
| 191 | <instance addr="0x1C011024" reg_inst="4"/> |
| 192 | <instance addr="0x1D011024" reg_inst="5"/> |
| 193 | <instance addr="0x1E011024" reg_inst="6"/> |
| 194 | <instance addr="0x1F011024" reg_inst="7"/> |
| 195 | </register> |
| 196 | <register name="IOHS_DLP_LINK1_EDPL_STATUS"> |
| 197 | <instance addr="0x18011025" reg_inst="0"/> |
| 198 | <instance addr="0x19011025" reg_inst="1"/> |
| 199 | <instance addr="0x1A011025" reg_inst="2"/> |
| 200 | <instance addr="0x1B011025" reg_inst="3"/> |
| 201 | <instance addr="0x1C011025" reg_inst="4"/> |
| 202 | <instance addr="0x1D011025" reg_inst="5"/> |
| 203 | <instance addr="0x1E011025" reg_inst="6"/> |
| 204 | <instance addr="0x1F011025" reg_inst="7"/> |
| 205 | </register> |
| 206 | <register name="IOHS_DLP_LINK0_QUALITY"> |
| 207 | <instance addr="0x18011026" reg_inst="0"/> |
| 208 | <instance addr="0x19011026" reg_inst="1"/> |
| 209 | <instance addr="0x1A011026" reg_inst="2"/> |
| 210 | <instance addr="0x1B011026" reg_inst="3"/> |
| 211 | <instance addr="0x1C011026" reg_inst="4"/> |
| 212 | <instance addr="0x1D011026" reg_inst="5"/> |
| 213 | <instance addr="0x1E011026" reg_inst="6"/> |
| 214 | <instance addr="0x1F011026" reg_inst="7"/> |
| 215 | </register> |
| 216 | <register name="IOHS_DLP_LINK1_QUALITY"> |
| 217 | <instance addr="0x18011027" reg_inst="0"/> |
| 218 | <instance addr="0x19011027" reg_inst="1"/> |
| 219 | <instance addr="0x1A011027" reg_inst="2"/> |
| 220 | <instance addr="0x1B011027" reg_inst="3"/> |
| 221 | <instance addr="0x1C011027" reg_inst="4"/> |
| 222 | <instance addr="0x1D011027" reg_inst="5"/> |
| 223 | <instance addr="0x1E011027" reg_inst="6"/> |
| 224 | <instance addr="0x1F011027" reg_inst="7"/> |
| 225 | </register> |
| 226 | <register name="IOHS_DLP_DLL_STATUS"> |
| 227 | <instance addr="0x18011028" reg_inst="0"/> |
| 228 | <instance addr="0x19011028" reg_inst="1"/> |
| 229 | <instance addr="0x1A011028" reg_inst="2"/> |
| 230 | <instance addr="0x1B011028" reg_inst="3"/> |
| 231 | <instance addr="0x1C011028" reg_inst="4"/> |
| 232 | <instance addr="0x1D011028" reg_inst="5"/> |
| 233 | <instance addr="0x1E011028" reg_inst="6"/> |
| 234 | <instance addr="0x1F011028" reg_inst="7"/> |
| 235 | </register> |
| 236 | <register name="IOHS_DLP_MISC_ERROR_STATUS"> |
| 237 | <instance addr="0x18011029" reg_inst="0"/> |
| 238 | <instance addr="0x19011029" reg_inst="1"/> |
| 239 | <instance addr="0x1A011029" reg_inst="2"/> |
| 240 | <instance addr="0x1B011029" reg_inst="3"/> |
| 241 | <instance addr="0x1C011029" reg_inst="4"/> |
| 242 | <instance addr="0x1D011029" reg_inst="5"/> |
| 243 | <instance addr="0x1E011029" reg_inst="6"/> |
| 244 | <instance addr="0x1F011029" reg_inst="7"/> |
| 245 | </register> |
| 246 | <capture_group node_inst="0:7"> |
Zane Shelley | bd48bf9 | 2022-06-11 11:07:14 -0500 | [diff] [blame^] | 247 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_CONFIG" /> |
| 248 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_CONTROL" /> |
| 249 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_PHY_CONFIG" /> |
| 250 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_SEC_CONFIG" /> |
Zane Shelley | b1749b8 | 2021-10-02 22:23:06 -0500 | [diff] [blame] | 251 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_OPTICAL_CONFIG" /> |
| 252 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK0_TX_LANE_CONTROL" /> |
| 253 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK1_TX_LANE_CONTROL" /> |
| 254 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK0_RX_LANE_CONTROL" /> |
| 255 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK1_RX_LANE_CONTROL" /> |
| 256 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK0_INFO" /> |
| 257 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK1_INFO" /> |
| 258 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK0_ERROR_STATUS" /> |
| 259 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK1_ERROR_STATUS" /> |
| 260 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_REPLAY_THRESHOLD" /> |
| 261 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_SL_ECC_THRESHOLD" /> |
| 262 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK0_SYN_CAPTURE" /> |
| 263 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK1_SYN_CAPTURE" /> |
| 264 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK0_EDPL_STATUS" /> |
| 265 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK1_EDPL_STATUS" /> |
| 266 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK0_QUALITY" /> |
| 267 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_LINK1_QUALITY" /> |
| 268 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_DLL_STATUS" /> |
| 269 | <capture_register reg_inst="0:7" reg_name="IOHS_DLP_MISC_ERROR_STATUS" /> |
| 270 | </capture_group> |
| 271 | <bit pos="0">link0 trained</bit> |
| 272 | <bit pos="1">link1 trained</bit> |
| 273 | <bit pos="2">link0 op irq</bit> |
| 274 | <bit pos="3">link1 op irq</bit> |
| 275 | <bit pos="4">link0 replay threshold</bit> |
| 276 | <bit pos="5">link1 replay threshold</bit> |
| 277 | <bit pos="6">link0 crc error</bit> |
| 278 | <bit pos="7">link1 crc error</bit> |
| 279 | <bit pos="8">link0 nak received</bit> |
| 280 | <bit pos="9">link1 nak received</bit> |
| 281 | <bit pos="10">link0 replay buffer full</bit> |
| 282 | <bit pos="11">link1 replay buffer full</bit> |
| 283 | <bit pos="12">link0 sl ecc threshold</bit> |
| 284 | <bit pos="13">link1 sl ecc threshold</bit> |
| 285 | <bit pos="14">link0 sl ecc correctable</bit> |
| 286 | <bit pos="15">link1 sl ecc correctable</bit> |
| 287 | <bit pos="16">link0 sl ecc ue</bit> |
| 288 | <bit pos="17">link1 sl ecc ue</bit> |
| 289 | <bit pos="18">link0 retrain threshold</bit> |
| 290 | <bit pos="19">link1 retrain threshold</bit> |
| 291 | <bit pos="20">link0 loss block align</bit> |
| 292 | <bit pos="21">link1 loss block align</bit> |
| 293 | <bit pos="22">link0 invalid block</bit> |
| 294 | <bit pos="23">link1 invalid block</bit> |
| 295 | <bit pos="24">link0 deskew error</bit> |
| 296 | <bit pos="25">link1 deskew error</bit> |
| 297 | <bit pos="26">link0 deskew overflow</bit> |
| 298 | <bit pos="27">link1 deskew overflow</bit> |
| 299 | <bit pos="28">link0 sw retrain</bit> |
| 300 | <bit pos="29">link1 sw retrain</bit> |
| 301 | <bit pos="30">link0 ack queue overflow</bit> |
| 302 | <bit pos="31">link1 ack queue overflow</bit> |
| 303 | <bit pos="32">link0 ack queue underflow</bit> |
| 304 | <bit pos="33">link1 ack queue underflow</bit> |
| 305 | <bit pos="34">link0 num replay</bit> |
| 306 | <bit pos="35">link1 num replay</bit> |
| 307 | <bit pos="36">link0 training set received</bit> |
| 308 | <bit pos="37">link1 training set received</bit> |
| 309 | <bit pos="38">link0 prbs select error</bit> |
| 310 | <bit pos="39">link1 prbs select error</bit> |
| 311 | <bit pos="40">link0 tcomplete bad</bit> |
| 312 | <bit pos="41">link1 tcomplete bad</bit> |
| 313 | <bit pos="42">link0 no spare lane available</bit> |
| 314 | <bit pos="43">link1 no spare lane available</bit> |
| 315 | <bit pos="44">link0 spare done</bit> |
| 316 | <bit pos="45">link1 spare done</bit> |
| 317 | <bit pos="46">link0 too many crc errors</bit> |
| 318 | <bit pos="47">link1 too many crc errors</bit> |
| 319 | <bit pos="48">unused</bit> |
| 320 | <bit pos="49">unused</bit> |
| 321 | <bit pos="50">link0 osc switch</bit> |
| 322 | <bit pos="51">link1 osc switch</bit> |
| 323 | <bit pos="52">link0 correctable array error</bit> |
| 324 | <bit pos="53">link1 correctable array error</bit> |
| 325 | <bit pos="54">link0 uncorrectable array error</bit> |
| 326 | <bit pos="55">link1 uncorrectable array error</bit> |
| 327 | <bit pos="56">link0 training failed</bit> |
| 328 | <bit pos="57">link1 training failed</bit> |
| 329 | <bit pos="58">link0 unrecoverable error</bit> |
| 330 | <bit pos="59">link1 unrecoverable error</bit> |
| 331 | <bit pos="60">link0 internal error</bit> |
| 332 | <bit pos="61">link1 internal error</bit> |
| 333 | </attn_node> |