| Zane Shelley | 11b8994 | 2019-11-07 11:07:28 -0600 | [diff] [blame] | 1 | #include "simulator.hpp" |
| 2 | |
| 3 | START_TEST_CASE(SampleTestSet1) |
| 4 | |
| Zane Shelley | 1be4c3c | 2020-04-17 15:55:07 -0500 | [diff] [blame] | 5 | CHIP(proc0, SAMPLE) |
| Zane Shelley | 11b8994 | 2019-11-07 11:07:28 -0600 | [diff] [blame] | 6 | |
| 7 | START_ITERATION |
| 8 | |
| Zane Shelley | aadf3bf | 2020-04-30 21:25:29 -0500 | [diff] [blame] | 9 | REG_SCOM(proc0, 0xf0000000, 0x0000000000000000) // GFIR_CS |
| 10 | REG_SCOM(proc0, 0xf0000001, 0x0000000000000000) // GFIR_RE |
| 11 | |
| 12 | REG_SCOM(proc0, 0x00f00000, 0x0000000000000000) // CFIR0_CS inst 0 |
| 13 | REG_SCOM(proc0, 0x00f00001, 0x0000000000000000) // CFIR0_RE inst 0 |
| 14 | REG_SCOM(proc0, 0x00f00002, 0x0000000000000000) // CFIR0_MASK inst 0 |
| 15 | |
| 16 | REG_SCOM(proc0, 0x00f00010, 0x0000000000000000) // CFIR0_CS inst 1 |
| 17 | REG_SCOM(proc0, 0x00f00011, 0x0000000000000000) // CFIR0_RE inst 1 |
| 18 | REG_SCOM(proc0, 0x00f00012, 0x0000000000000000) // CFIR0_MASK inst 1 |
| 19 | |
| 20 | REG_SCOM(proc0, 0x00f10000, 0x0000000000000000) // CFIR1_CS inst 0 |
| 21 | REG_SCOM(proc0, 0x00f10001, 0x0000000000000000) // CFIR1_RE inst 0 |
| 22 | REG_SCOM(proc0, 0x00f10002, 0x0000000000000000) // CFIR1_MASK inst 0 |
| 23 | |
| 24 | REG_SCOM(proc0, 0x0000f000, 0x0000000000000000) // LFIR0 inst 0 |
| 25 | REG_SCOM(proc0, 0x0000f003, 0x0000000000000000) // LFIR0_MASK inst 0 |
| 26 | REG_SCOM(proc0, 0x0000f006, 0x0000000000000000) // LFIR0_ACT0 inst 0 |
| 27 | REG_SCOM(proc0, 0x0000f007, 0x0000000000000000) // LFIR0_ACT1 inst 0 |
| 28 | |
| 29 | REG_SCOM(proc0, 0x0000f010, 0x0000000000000000) // LFIR0 inst 1 |
| 30 | REG_SCOM(proc0, 0x0000f013, 0x0000000000000000) // LFIR0_MASK inst 1 |
| 31 | REG_SCOM(proc0, 0x0000f016, 0x0000000000000000) // LFIR0_ACT0 inst 1 |
| 32 | REG_SCOM(proc0, 0x0000f017, 0x0000000000000000) // LFIR0_ACT1 inst 1 |
| 33 | |
| 34 | REG_SCOM(proc0, 0x0000f100, 0x0000000000000000) // LFIR1 inst 0 |
| 35 | REG_SCOM(proc0, 0x0000f103, 0x0000000000000000) // LFIR1_MASK inst 0 |
| 36 | REG_SCOM(proc0, 0x0000f106, 0x0000000000000000) // LFIR1_ACT0 inst 0 |
| 37 | REG_SCOM(proc0, 0x0000f107, 0x0000000000000000) // LFIR1_ACT1 inst 0 |
| 38 | |
| 39 | REG_SCOM(proc0, 0x0000f110, 0x0000000000000000) // LFIR1 inst 1 |
| 40 | REG_SCOM(proc0, 0x0000f113, 0x0000000000000000) // LFIR1_MASK inst 1 |
| 41 | REG_SCOM(proc0, 0x0000f116, 0x0000000000000000) // LFIR1_ACT0 inst 1 |
| 42 | REG_SCOM(proc0, 0x0000f117, 0x0000000000000000) // LFIR1_ACT1 inst 1 |
| 43 | |
| 44 | REG_SCOM(proc0, 0x0000f120, 0x0000000000000000) // LFIR1 inst 2 |
| 45 | REG_SCOM(proc0, 0x0000f123, 0x0000000000000000) // LFIR1_MASK inst 2 |
| 46 | REG_SCOM(proc0, 0x0000f126, 0x0000000000000000) // LFIR1_ACT0 inst 2 |
| 47 | REG_SCOM(proc0, 0x0000f127, 0x0000000000000000) // LFIR1_ACT1 inst 2 |
| 48 | |
| 49 | REG_SCOM(proc0, 0x0000f130, 0x0000000000000000) // LFIR1 inst 3 |
| 50 | REG_SCOM(proc0, 0x0000f133, 0x0000000000000000) // LFIR1_MASK inst 3 |
| 51 | REG_SCOM(proc0, 0x0000f136, 0x0000000000000000) // LFIR1_ACT0 inst 3 |
| 52 | REG_SCOM(proc0, 0x0000f137, 0x0000000000000000) // LFIR1_ACT1 inst 3 |
| 53 | |
| 54 | REG_SCOM(proc0, 0x0000f140, 0x0000000000000000) // LFIR1 inst 4 |
| 55 | REG_SCOM(proc0, 0x0000f143, 0x0000000000000000) // LFIR1_MASK inst 4 |
| 56 | REG_SCOM(proc0, 0x0000f146, 0x0000000000000000) // LFIR1_ACT0 inst 4 |
| 57 | REG_SCOM(proc0, 0x0000f147, 0x0000000000000000) // LFIR1_ACT1 inst 4 |
| 58 | |
| 59 | REG_SCOM(proc0, 0x0000f150, 0x0000000000000000) // LFIR1 inst 5 |
| 60 | REG_SCOM(proc0, 0x0000f153, 0x0000000000000000) // LFIR1_MASK inst 5 |
| 61 | REG_SCOM(proc0, 0x0000f156, 0x0000000000000000) // LFIR1_ACT0 inst 5 |
| 62 | REG_SCOM(proc0, 0x0000f157, 0x0000000000000000) // LFIR1_ACT1 inst 5 |
| 63 | |
| 64 | REG_SCOM(proc0, 0x0000f200, 0x0000000000000000) // LFIR2 inst 0 |
| 65 | REG_SCOM(proc0, 0x0000f203, 0x0000000000000000) // LFIR2_MASK inst 0 |
| 66 | REG_SCOM(proc0, 0x0000f206, 0x0000000000000000) // LFIR2_ACT0 inst 0 |
| 67 | REG_SCOM(proc0, 0x0000f207, 0x0000000000000000) // LFIR2_ACT1 inst 0 |
| 68 | |
| 69 | // start temp test case |
| Zane Shelley | 11b8994 | 2019-11-07 11:07:28 -0600 | [diff] [blame] | 70 | REG_IDSCOM(proc0, 0x80000000FF000000, 0x8000) // parent FIR bit 48 |
| 71 | |
| 72 | REG_SCOM(proc0, 0x00FF0000, 0x8800000000000000) // child FIR bits 0 and 4 |
| 73 | |
| 74 | EXP_SIG(proc0, 0x2222, 0, 0, CHECKSTOP) |
| 75 | EXP_SIG(proc0, 0x2222, 0, 4, CHECKSTOP) |
| Zane Shelley | aadf3bf | 2020-04-30 21:25:29 -0500 | [diff] [blame] | 76 | // end temp test case |
| Zane Shelley | 11b8994 | 2019-11-07 11:07:28 -0600 | [diff] [blame] | 77 | |
| 78 | END_ITERATION |
| 79 | |
| 80 | END_TEST_CASE |