Zane Shelley | d83e346 | 2021-09-28 17:35:01 -0500 | [diff] [blame] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
| 2 | <attn_node model_ec="P10_10,P10_20" name="PB_DOB01_DIB01_INT_ERR" reg_type="SCOM"> |
| 3 | <register name="PB_DOB01_DIB01_INT_ERR"> |
| 4 | <instance reg_inst="0" addr="0x10011828" /> |
| 5 | <instance reg_inst="1" addr="0x11011828" /> |
| 6 | <instance reg_inst="2" addr="0x12011828" /> |
| 7 | <instance reg_inst="3" addr="0x13011828" /> |
| 8 | </register> |
| 9 | <rule attn_type="CS" node_inst="0:3"> |
| 10 | <expr type="reg" value1="PB_DOB01_DIB01_INT_ERR"/> |
| 11 | </rule> |
| 12 | <rule attn_type="RE" node_inst="0:3"> |
| 13 | <expr type="reg" value1="PB_DOB01_DIB01_INT_ERR"/> |
| 14 | </rule> |
| 15 | <rule attn_type="SPA" node_inst="0:3"> |
| 16 | <expr type="reg" value1="PB_DOB01_DIB01_INT_ERR"/> |
| 17 | </rule> |
| 18 | <bit pos="0">dob01_rtag_pbiterr</bit> |
| 19 | <bit pos="1">dob01_rtag_perr</bit> |
| 20 | <bit pos="2">dob01_misc_perr</bit> |
| 21 | <bit pos="3">dob01_f0vc0_evenperr</bit> |
| 22 | <bit pos="4">dob01_f0vc0_oddperr</bit> |
| 23 | <bit pos="5">dob01_f0vc1_evenperr</bit> |
| 24 | <bit pos="6">dob01_f0vc1_oddperr</bit> |
| 25 | <bit pos="7">dob01_f1vc0_evenperr</bit> |
| 26 | <bit pos="8">dob01_f1vc0_oddperr</bit> |
| 27 | <bit pos="9">dob01_f1vc1_evenperr</bit> |
| 28 | <bit pos="10">dob01_f1vc1_oddperr</bit> |
| 29 | <bit pos="11">dob01_f0_underflow</bit> |
| 30 | <bit pos="12">dob01_f0_overflow</bit> |
| 31 | <bit pos="13">dob01_f1_underflow</bit> |
| 32 | <bit pos="14">dob01_f1_overflow</bit> |
| 33 | <bit pos="15">dob01_vc0_underflow</bit> |
| 34 | <bit pos="16">dob01_vc0_overflow</bit> |
| 35 | <bit pos="17">dob01_vc1_underflow</bit> |
| 36 | <bit pos="18">dob01_vc1_overflow</bit> |
| 37 | <bit pos="19">dob01_f0vc0_underflow</bit> |
| 38 | <bit pos="20">dob01_f0vc0_overflow</bit> |
| 39 | <bit pos="21">dob01_f0vc1_underflow</bit> |
| 40 | <bit pos="22">dob01_f0vc1_overflow</bit> |
| 41 | <bit pos="23">dob01_f1vc0_underflow</bit> |
| 42 | <bit pos="24">dob01_f1vc0_overflow</bit> |
| 43 | <bit pos="25">dob01_f1vc1_underflow</bit> |
| 44 | <bit pos="26">dob01_f1vc1_overflow</bit> |
| 45 | <bit pos="27">dob01_vc0_prefetch_overflow</bit> |
| 46 | <bit pos="28">dob01_vc1_prefetch_overflow</bit> |
| 47 | <bit pos="29">dib01_evn0_underflow</bit> |
| 48 | <bit pos="30">dib01_evn0_overflow</bit> |
| 49 | <bit pos="31">dib01_evn1_underflow</bit> |
| 50 | <bit pos="32">dib01_evn1_overflow</bit> |
| 51 | <bit pos="33">dib01_rtag_pbiterr</bit> |
| 52 | <bit pos="34">dib01_rtag_perr</bit> |
| 53 | <bit pos="35">dib01_misc_perr</bit> |
| 54 | <bit pos="36">dib01_odd0_underflow</bit> |
| 55 | <bit pos="37">dib01_odd0_overflow</bit> |
| 56 | <bit pos="38">dib01_odd1_underflow</bit> |
| 57 | <bit pos="39">dib01_odd1_overflow</bit> |
| 58 | <bit pos="40">dib01_rtag_underflow</bit> |
| 59 | <bit pos="41">dib01_rtag_overflow</bit> |
| 60 | <bit pos="42">dib01_data_underflow</bit> |
| 61 | <bit pos="43">dib01_data_overflow</bit> |
| 62 | <bit pos="44">dib01_vc0_underflow</bit> |
| 63 | <bit pos="45">dib01_vc0_overflow</bit> |
| 64 | <bit pos="46">dib01_vc1_underflow</bit> |
| 65 | <bit pos="47">dib01_vc1_overflow</bit> |
| 66 | <bit pos="48">dib01_f0vc0_over_underflow</bit> |
| 67 | <bit pos="49">dib01_f0vc1_over_underflow</bit> |
| 68 | <bit pos="50">dib01_f1vc0_over_underflow</bit> |
| 69 | <bit pos="51">dib01_f1vc1_over_underflow</bit> |
| 70 | </attn_node> |