| Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
| Zane Shelley | f8a726b | 2020-12-16 21:29:32 -0600 | [diff] [blame^] | 2 | <attn_node model_ec="P10_10,P10_20" name="CFIR_EQ_CS" reg_type="SCOM"> |
| Zane Shelley | abc51c2 | 2020-11-09 21:35:35 -0600 | [diff] [blame] | 3 | <register name="CFIR_EQ_XSTOP"> |
| 4 | <instance addr="0x20040000" reg_inst="0"/> |
| 5 | <instance addr="0x21040000" reg_inst="1"/> |
| 6 | <instance addr="0x22040000" reg_inst="2"/> |
| 7 | <instance addr="0x23040000" reg_inst="3"/> |
| 8 | <instance addr="0x24040000" reg_inst="4"/> |
| 9 | <instance addr="0x25040000" reg_inst="5"/> |
| 10 | <instance addr="0x26040000" reg_inst="6"/> |
| 11 | <instance addr="0x27040000" reg_inst="7"/> |
| 12 | </register> |
| 13 | <register name="CFIR_EQ_XSTOP_MASK"> |
| 14 | <instance addr="0x20040040" reg_inst="0"/> |
| 15 | <instance addr="0x21040040" reg_inst="1"/> |
| 16 | <instance addr="0x22040040" reg_inst="2"/> |
| 17 | <instance addr="0x23040040" reg_inst="3"/> |
| 18 | <instance addr="0x24040040" reg_inst="4"/> |
| 19 | <instance addr="0x25040040" reg_inst="5"/> |
| 20 | <instance addr="0x26040040" reg_inst="6"/> |
| 21 | <instance addr="0x27040040" reg_inst="7"/> |
| 22 | </register> |
| 23 | <rule attn_type="CS" node_inst="0:7"> |
| 24 | <expr type="and"> |
| 25 | <expr type="reg" value1="CFIR_EQ_XSTOP"/> |
| 26 | <expr type="not"> |
| 27 | <expr type="reg" value1="CFIR_EQ_XSTOP_MASK"/> |
| 28 | </expr> |
| 29 | <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/> |
| 30 | </expr> |
| 31 | </rule> |
| 32 | <bit child_node="EQ_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Local FIR</bit> |
| 33 | <bit child_node="EQ_L2_FIR" node_inst="0,4,8,12,16,20,24,28" pos="9">L2 FIR Register</bit> |
| 34 | <bit child_node="EQ_L2_FIR" node_inst="1,5,9,13,17,21,25,29" pos="10">L2 FIR Register</bit> |
| 35 | <bit child_node="EQ_L2_FIR" node_inst="2,6,10,14,18,22,26,30" pos="11">L2 FIR Register</bit> |
| 36 | <bit child_node="EQ_L2_FIR" node_inst="3,7,11,15,19,23,27,31" pos="12">L2 FIR Register</bit> |
| 37 | <bit child_node="EQ_L3_FIR" node_inst="0,4,8,12,16,20,24,28" pos="13">L3 FIR Register</bit> |
| 38 | <bit child_node="EQ_L3_FIR" node_inst="1,5,9,13,17,21,25,29" pos="14">L3 FIR Register</bit> |
| 39 | <bit child_node="EQ_L3_FIR" node_inst="2,6,10,14,18,22,26,30" pos="15">L3 FIR Register</bit> |
| 40 | <bit child_node="EQ_L3_FIR" node_inst="3,7,11,15,19,23,27,31" pos="16">L3 FIR Register</bit> |
| 41 | <bit child_node="EQ_NCU_FIR" node_inst="0,4,8,12,16,20,24,28" pos="17">NCU FIR Register</bit> |
| 42 | <bit child_node="EQ_NCU_FIR" node_inst="1,5,9,13,17,21,25,29" pos="18">NCU FIR Register</bit> |
| 43 | <bit child_node="EQ_NCU_FIR" node_inst="2,6,10,14,18,22,26,30" pos="19">NCU FIR Register</bit> |
| 44 | <bit child_node="EQ_NCU_FIR" node_inst="3,7,11,15,19,23,27,31" pos="20">NCU FIR Register</bit> |
| 45 | <bit child_node="EQ_QME_FIR" node_inst="0,1,2,3,4,5,6,7" pos="21">QME Local Fault Isolation Register</bit> |
| 46 | <bit child_node="EQ_CORE_FIR" node_inst="0,4,8,12,16,20,24,28" pos="5">Core Fault Isolation Register</bit> |
| 47 | <bit child_node="EQ_CORE_FIR" node_inst="1,5,9,13,17,21,25,29" pos="6">Core Fault Isolation Register</bit> |
| 48 | <bit child_node="EQ_CORE_FIR" node_inst="2,6,10,14,18,22,26,30" pos="7">Core Fault Isolation Register</bit> |
| 49 | <bit child_node="EQ_CORE_FIR" node_inst="3,7,11,15,19,23,27,31" pos="8">Core Fault Isolation Register</bit> |
| 50 | </attn_node> |