| Vishwanatha Subbanna | 41490f2 | 2020-10-14 05:04:37 -0500 | [diff] [blame] | 1 | description: > |
| 2 | This defines a PCIe slot to be exposed for system management. |
| 3 | It includes the slot properties. |
| 4 | |
| 5 | properties: |
| 6 | - name: Generation |
| 7 | type: enum[self.Generations] |
| 8 | default: 'Unknown' |
| 9 | description: > |
| 10 | The PCIe generation of the slot |
| 11 | |
| 12 | - name: Lanes |
| 13 | type: size |
| 14 | description: > |
| 15 | The maximum number of PCIe lanes supported by the slot |
| 16 | |
| 17 | - name: SlotType |
| 18 | type: enum[self.SlotTypes] |
| 19 | default: 'Unknown' |
| 20 | description: > |
| 21 | The type of the slot |
| 22 | |
| 23 | - name: HotPluggable |
| 24 | type: boolean |
| 25 | description: > |
| 26 | Whether this PCIe slot supports hotplug |
| 27 | |
| 28 | enumerations: |
| 29 | - name: Generations |
| 30 | description: > |
| 31 | Possible PCIe generations |
| 32 | values: |
| 33 | - name: 'Gen1' |
| 34 | description: > |
| 35 | PCIe v1.0 slot |
| 36 | |
| 37 | - name: 'Gen2' |
| 38 | description: > |
| 39 | PCIe v2.0 slot |
| 40 | |
| 41 | - name: 'Gen3' |
| 42 | description: > |
| 43 | PCIe v3.0 slot |
| 44 | |
| 45 | - name: 'Gen4' |
| 46 | description: > |
| 47 | PCIe v4.0 slot |
| 48 | |
| 49 | - name: 'Gen5' |
| 50 | description: > |
| 51 | PCIe v5.0 slot |
| 52 | |
| 53 | - name: 'Unknown' |
| 54 | description: > |
| 55 | Version of the PCIe slot is unknown |
| 56 | |
| 57 | - name: SlotTypes |
| 58 | description: > |
| 59 | Possible types of a PCIe slot |
| 60 | values: |
| 61 | - name: 'FullLength' |
| 62 | description: > |
| 63 | Full-Length PCIe slot |
| 64 | |
| 65 | - name: 'HalfLength' |
| 66 | description: > |
| 67 | Half-Length PCIe slot |
| 68 | |
| 69 | - name: 'LowProfile' |
| 70 | description: > |
| 71 | Low-Profile or Slim PCIe slot |
| 72 | |
| 73 | - name: 'Mini' |
| 74 | description: > |
| 75 | Mini PCIe slot |
| 76 | |
| 77 | - name: 'M_2' |
| 78 | description: > |
| 79 | PCIe M.2 slot |
| 80 | |
| 81 | - name: 'OEM' |
| 82 | description: > |
| 83 | An OEM-specific PCIe slot |
| 84 | |
| 85 | - name: 'OCP3Small' |
| 86 | description: > |
| 87 | Open Compute Project 3.0 small form factor PCIe slot |
| 88 | |
| 89 | - name: 'OCP3Large' |
| 90 | description: > |
| 91 | Open Compute Project 3.0 large form factor PCIe slot |
| 92 | |
| 93 | - name: 'U_2' |
| 94 | description: > |
| 95 | U.2 / SFF-8639 PCIe slot or bay |
| 96 | |
| 97 | - name: 'Unknown' |
| 98 | description: > |
| 99 | Type of the PCIe slot is unknown |
| Brad Bishop | df55704 | 2021-10-04 15:51:11 -0400 | [diff] [blame^] | 100 | |
| 101 | associations: |
| 102 | - name: upstream_processor |
| 103 | description: > |
| 104 | Objects that implement PCIeSlot can optionally implement the |
| 105 | upstream_processor association to provide a link back to a PCIe host |
| 106 | bridge or on-processor PCIe root complexes. |
| 107 | reverse_name: associated_pcie_slots |
| 108 | required_endpoint_interfaces: |
| 109 | - xyz.openbmc_project.Inventory.Item.Cpu |