| Brad Bishop | a948d26 | 2016-10-05 19:51:48 -0400 | [diff] [blame] | 1 | description: > |
| 2 | Implement to provide DIMM attributes. |
| Cheng C Yang | 9bf62f1 | 2019-10-27 00:24:55 +0800 | [diff] [blame] | 3 | properties: |
| 4 | - name: MemoryDataWidth |
| 5 | type: uint16 |
| 6 | description: > |
| 7 | Data width of Memory. |
| 8 | - name: MemorySizeInKB |
| 9 | type: uint32 |
| 10 | description: > |
| 11 | Memory size of DIMM in Kilobyte. |
| 12 | - name: MemoryDeviceLocator |
| 13 | type: string |
| 14 | description: > |
| 15 | Socket on base board where Memory located, for example CPU1_DIMM_B1. |
| 16 | - name: MemoryType |
| 17 | type: enum[self.DeviceType] |
| 18 | description: > |
| 19 | Type of memory. |
| 20 | - name: MemoryTypeDetail |
| 21 | type: string |
| 22 | description: > |
| 23 | Additional detail on Memory, such as Synchronous, Static column, etc. |
| 24 | - name: MaxMemorySpeedInMhz |
| 25 | type: uint16 |
| 26 | description: > |
| 27 | The maximum capable clock speed of Memory, in megahertz. |
| 28 | - name: MemoryAttributes |
| 29 | type: byte |
| 30 | description: > |
| 31 | Rank attributes of Memory. Means how many groups of memory chips on |
| 32 | the dimm. |
| 33 | - name: MemoryConfiguredSpeedInMhz |
| 34 | type: uint16 |
| 35 | description: > |
| 36 | Configured clock speed to Memory, in megahertz. |
| 37 | - name: ECC |
| 38 | type: enum[self.Ecc] |
| 39 | description: > |
| 40 | Error-Correcting Code. |
| 41 | - name: CASLatencies |
| 42 | type: uint16 |
| 43 | description: > |
| 44 | CAS Latency (CL) values are supported. The CAS latency is the delay |
| 45 | between the time at which the column address and the column address |
| 46 | strobe signal are presented to the memory module and the time at which |
| 47 | the corresponding data is made available by the memory module. |
| 48 | - name: RevisionCode |
| 49 | type: uint16 |
| 50 | description: > |
| 51 | Revision code provided by the individual manufacturer. |
| Brad Bishop | a948d26 | 2016-10-05 19:51:48 -0400 | [diff] [blame] | 52 | |
| Cheng C Yang | 9bf62f1 | 2019-10-27 00:24:55 +0800 | [diff] [blame] | 53 | enumerations: |
| 54 | - name: Ecc |
| 55 | description: > |
| 56 | Error-Correcting Code. |
| 57 | values: |
| 58 | - name: NoECC |
| 59 | description: > |
| 60 | No ECC support. |
| 61 | - name: SingleBitECC |
| 62 | description: > |
| 63 | Single bit data errors can be corrected by ECC. |
| 64 | - name: MultiBitECC |
| 65 | description: > |
| 66 | Multibit data errors can be corrected by ECC. |
| 67 | - name: AddressParit |
| 68 | description: > |
| 69 | Address parity errors can be corrected. |
| 70 | - name: Type |
| 71 | description: > |
| 72 | This property shall contain the type ofmemory that this Resource |
| 73 | represents. |
| 74 | values: |
| 75 | - name: DRAM |
| 76 | description: > |
| 77 | The memory module is comprised of volatile memory. |
| 78 | - name: NVDIMM_N |
| 79 | description: > |
| 80 | The memory module is comprised of volatile memory backed by |
| 81 | non-volatile memory. |
| 82 | - name: NVDIMM_F |
| 83 | description: > |
| 84 | The memory module is comprised of non-volatile memory. |
| 85 | - name: NVDIMM_P |
| 86 | description: > |
| 87 | The memory module is comprised of a combination of non-volatile |
| 88 | and volatile memory. |
| 89 | - name: IntelOptane |
| 90 | description: > |
| 91 | The memory module is an Intel Optane DC Persistent Memory Module. |
| 92 | - name: DeviceType |
| 93 | description: > |
| 94 | This property shall contain the Memory Device Type as defined by |
| 95 | SMBIOS. |
| 96 | values: |
| Cheng C Yang | e59bc11 | 2019-11-11 23:15:50 +0800 | [diff] [blame^] | 97 | - name: Other |
| 98 | description: > |
| 99 | Some devices which are not defined in this table. |
| 100 | - name: Unknown |
| 101 | description: > |
| 102 | Unknown device. |
| 103 | - name: DRAM |
| 104 | description: > |
| 105 | Dynamic Random Access Memory. |
| 106 | - name: EDRAM |
| 107 | description: > |
| 108 | Enhanced Dynamic Random Access Memory. |
| 109 | - name: VRAM |
| 110 | description: > |
| 111 | Video Random Access Memory. |
| 112 | - name: SRAM |
| 113 | description: > |
| 114 | Static Random Access Memory. |
| 115 | - name: RAM |
| 116 | description: > |
| 117 | Random Access Memory. |
| 118 | - name: ROM |
| 119 | description: > |
| 120 | Read Only Memory. |
| 121 | - name: FLASH |
| 122 | description: > |
| 123 | Flash Memory. |
| 124 | - name: EEPROM |
| 125 | description: > |
| 126 | Electrically Erasable Programmable Read Only Memory. |
| 127 | - name: FEPROM |
| 128 | description: > |
| 129 | Flash Erasable Programmable Read Only Memory. |
| 130 | - name: EPROM |
| 131 | description: > |
| 132 | Erasable Programmable Read Only Memory. |
| 133 | - name: CDRAM |
| 134 | description: > |
| 135 | Cached Dynamic Random Access Memory. |
| 136 | - name: ThreeDRAM |
| 137 | description: > |
| 138 | Three Dimensional Random Access Memory. |
| 139 | - name: SDRAM |
| 140 | description: > |
| 141 | Synchronous Dynamic Random Access Memory. |
| 142 | - name: DDR_SGRAM |
| 143 | description: > |
| 144 | Double Data Rate Synchronous Graphics Random-Access Memory. |
| 145 | - name: RDRAM |
| 146 | description: > |
| 147 | Direct Rambus Dynamic Random Access Memory. |
| Cheng C Yang | 9bf62f1 | 2019-10-27 00:24:55 +0800 | [diff] [blame] | 148 | - name: DDR |
| 149 | description: > |
| 150 | Double Data Rate SDRAM. |
| 151 | - name: DDR2 |
| 152 | description: > |
| 153 | Double Data Rate 2 SDRAM. |
| Cheng C Yang | 9bf62f1 | 2019-10-27 00:24:55 +0800 | [diff] [blame] | 154 | - name: DDR2_SDRAM_FB_DIMM |
| 155 | description: > |
| 156 | DDR2 SDRAM Fully Buffered DIMM. |
| Cheng C Yang | 9bf62f1 | 2019-10-27 00:24:55 +0800 | [diff] [blame] | 157 | - name: EDO |
| 158 | description: > |
| 159 | Extended Data Output Memory. |
| 160 | - name: FastPageMode |
| 161 | description: > |
| 162 | Fast Page Mode Memory. |
| 163 | - name: PipelinedNibble |
| 164 | description: > |
| 165 | Pipelined Nibble Memory. |
| Cheng C Yang | e59bc11 | 2019-11-11 23:15:50 +0800 | [diff] [blame^] | 166 | - name: DDR3 |
| 167 | description: > |
| 168 | Double Data Rate 3 SDRAM. |
| 169 | - name: FBD2 |
| 170 | description: > |
| 171 | Fully Buffered DIMM 2. |
| 172 | - name: DDR4 |
| 173 | description: > |
| 174 | Double Data Rate 4 SDRAM. |
| 175 | - name: LPDDR_SDRAM |
| 176 | description: > |
| 177 | Low-Power Double Data Rate SDRAM. |
| 178 | - name: LPDDR2_SDRAM |
| 179 | description: > |
| 180 | Low-Power Double Data Rate 2 SDRAM. |
| 181 | - name: LPDDR3_SDRAM |
| 182 | description: > |
| 183 | Low-Power Double Data Rate 3 SDRAM. |
| 184 | - name: LPDDR4_SDRAM |
| 185 | description: > |
| 186 | Low-Power Double Data Rate 4 SDRAM. |
| Cheng C Yang | 9bf62f1 | 2019-10-27 00:24:55 +0800 | [diff] [blame] | 187 | - name: Logical |
| 188 | description: > |
| 189 | Logical Non-volatile device. |
| 190 | - name: HBM |
| 191 | description: > |
| 192 | High Bandwidth Memory |
| 193 | - name: HBM2 |
| 194 | description: > |
| 195 | High Bandwidth Memory Generation 2. |
| Cheng C Yang | e59bc11 | 2019-11-11 23:15:50 +0800 | [diff] [blame^] | 196 | - name: DDR2_SDRAM_FB_DIMM_PROB |
| 197 | description: > |
| 198 | DDR2 SDRAM Fully Buffered DIMM PROBE. |
| 199 | - name: DDR4E_SDRAM |
| 200 | description: > |
| 201 | Double Data Rate 4 Extended Compliant SDRAM. |
| Brad Bishop | a948d26 | 2016-10-05 19:51:48 -0400 | [diff] [blame] | 202 | # vim: tabstop=8 expandtab shiftwidth=4 softtabstop=4 |