James Feist | 7136a5a | 2018-07-19 09:52:05 -0700 | [diff] [blame] | 1 | /* |
| 2 | // Copyright (c) 2018 Intel Corporation |
| 3 | // |
| 4 | // Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | // you may not use this file except in compliance with the License. |
| 6 | // You may obtain a copy of the License at |
| 7 | // |
| 8 | // http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | // |
| 10 | // Unless required by applicable law or agreed to in writing, software |
| 11 | // distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | // See the License for the specific language governing permissions and |
| 14 | // limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #pragma once |
| 18 | |
Patrick Venture | da4a5dd | 2018-08-31 09:42:48 -0700 | [diff] [blame] | 19 | #include "interfaces.hpp" |
James Feist | 0c8223b | 2019-05-08 15:33:33 -0700 | [diff] [blame] | 20 | #include "util.hpp" |
James Feist | 7136a5a | 2018-07-19 09:52:05 -0700 | [diff] [blame] | 21 | |
Patrick Venture | f5e770b | 2018-10-30 12:28:53 -0700 | [diff] [blame] | 22 | #include <memory> |
James Feist | 7136a5a | 2018-07-19 09:52:05 -0700 | [diff] [blame] | 23 | #include <sdbusplus/bus.hpp> |
Patrick Venture | da4a5dd | 2018-08-31 09:42:48 -0700 | [diff] [blame] | 24 | #include <string> |
James Feist | 7136a5a | 2018-07-19 09:52:05 -0700 | [diff] [blame] | 25 | |
James Feist | 7136a5a | 2018-07-19 09:52:05 -0700 | [diff] [blame] | 26 | class DbusWritePercent : public WriteInterface |
| 27 | { |
| 28 | public: |
Patrick Venture | f5e770b | 2018-10-30 12:28:53 -0700 | [diff] [blame] | 29 | static std::unique_ptr<WriteInterface> |
| 30 | createDbusWrite(const std::string& path, int64_t min, int64_t max, |
| 31 | DbusHelperInterface& helper); |
| 32 | |
Patrick Venture | e2ec0f6 | 2018-09-04 12:30:27 -0700 | [diff] [blame] | 33 | DbusWritePercent(const std::string& path, int64_t min, int64_t max, |
Patrick Venture | f5e770b | 2018-10-30 12:28:53 -0700 | [diff] [blame] | 34 | const std::string& connectionName) : |
James Feist | 7136a5a | 2018-07-19 09:52:05 -0700 | [diff] [blame] | 35 | WriteInterface(min, max), |
Patrick Venture | f5e770b | 2018-10-30 12:28:53 -0700 | [diff] [blame] | 36 | path(path), connectionName(connectionName) |
James Feist | 7136a5a | 2018-07-19 09:52:05 -0700 | [diff] [blame] | 37 | { |
James Feist | 7136a5a | 2018-07-19 09:52:05 -0700 | [diff] [blame] | 38 | } |
| 39 | |
| 40 | void write(double value) override; |
| 41 | |
| 42 | private: |
| 43 | std::string path; |
| 44 | std::string connectionName; |
James Feist | cd9e109 | 2018-10-08 13:06:41 -0700 | [diff] [blame] | 45 | int64_t oldValue = -1; |
James Feist | 7136a5a | 2018-07-19 09:52:05 -0700 | [diff] [blame] | 46 | }; |
| 47 | |
| 48 | class DbusWrite : public WriteInterface |
| 49 | { |
| 50 | public: |
Patrick Venture | f5e770b | 2018-10-30 12:28:53 -0700 | [diff] [blame] | 51 | static std::unique_ptr<WriteInterface> |
| 52 | createDbusWrite(const std::string& path, int64_t min, int64_t max, |
| 53 | DbusHelperInterface& helper); |
| 54 | |
Patrick Venture | e2ec0f6 | 2018-09-04 12:30:27 -0700 | [diff] [blame] | 55 | DbusWrite(const std::string& path, int64_t min, int64_t max, |
Patrick Venture | f5e770b | 2018-10-30 12:28:53 -0700 | [diff] [blame] | 56 | const std::string& connectionName) : |
James Feist | 7136a5a | 2018-07-19 09:52:05 -0700 | [diff] [blame] | 57 | WriteInterface(min, max), |
Patrick Venture | f5e770b | 2018-10-30 12:28:53 -0700 | [diff] [blame] | 58 | path(path), connectionName(connectionName) |
James Feist | 7136a5a | 2018-07-19 09:52:05 -0700 | [diff] [blame] | 59 | { |
James Feist | 7136a5a | 2018-07-19 09:52:05 -0700 | [diff] [blame] | 60 | } |
| 61 | |
| 62 | void write(double value) override; |
| 63 | |
| 64 | private: |
| 65 | std::string path; |
| 66 | std::string connectionName; |
James Feist | cd9e109 | 2018-10-08 13:06:41 -0700 | [diff] [blame] | 67 | int64_t oldValue = -1; |
James Feist | 7136a5a | 2018-07-19 09:52:05 -0700 | [diff] [blame] | 68 | }; |