| Norman James | 9e9eba1 | 2015-11-19 16:05:57 -0600 | [diff] [blame] | 1 | /* Copyright 2013-2014 IBM Corp. |
| 2 | * |
| 3 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | * you may not use this file except in compliance with the License. |
| 5 | * You may obtain a copy of the License at |
| 6 | * |
| 7 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | * |
| 9 | * Unless required by applicable law or agreed to in writing, software |
| 10 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or |
| 12 | * implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | #ifndef __AST_H |
| 17 | #define __AST_H |
| 18 | |
| 19 | /* |
| 20 | * AHB bus registers |
| 21 | */ |
| 22 | |
| 23 | /* SPI Flash controller #1 (BMC) */ |
| 24 | #define BMC_SPI_FCTL_BASE 0x1E620000 |
| 25 | #define BMC_SPI_FCTL_CE_CTRL (BMC_SPI_FCTL_BASE + 0x04) |
| 26 | #define BMC_SPI_FCTL_CTRL (BMC_SPI_FCTL_BASE + 0x10) |
| 27 | #define BMC_SPI_FREAD_TIMING (BMC_SPI_FCTL_BASE + 0x94) |
| 28 | #define BMC_FLASH_BASE 0x20000000 |
| 29 | |
| 30 | /* SPI Flash controller #2 (PNOR) */ |
| 31 | #define PNOR_SPI_FCTL_BASE 0x1E630000 |
| 32 | #define PNOR_SPI_FCTL_CONF (PNOR_SPI_FCTL_BASE + 0x00) |
| 33 | #define PNOR_SPI_FCTL_CTRL (PNOR_SPI_FCTL_BASE + 0x04) |
| 34 | #define PNOR_SPI_FREAD_TIMING (PNOR_SPI_FCTL_BASE + 0x14) |
| 35 | #define PNOR_FLASH_BASE 0x30000000 |
| 36 | |
| 37 | /* LPC registers */ |
| 38 | #define LPC_BASE 0x1e789000 |
| 39 | #define LPC_HICR6 (LPC_BASE + 0x80) |
| 40 | #define LPC_HICR7 (LPC_BASE + 0x88) |
| 41 | #define LPC_HICR8 (LPC_BASE + 0x8c) |
| 42 | #define LPC_iBTCR0 (LPC_BASE + 0x140) |
| 43 | |
| 44 | /* VUART1 */ |
| 45 | #define VUART1_BASE 0x1e787000 |
| 46 | #define VUART1_GCTRLA (VUART1_BASE + 0x20) |
| 47 | #define VUART1_GCTRLB (VUART1_BASE + 0x24) |
| 48 | #define VUART1_ADDRL (VUART1_BASE + 0x28) |
| 49 | #define VUART1_ADDRH (VUART1_BASE + 0x2c) |
| 50 | |
| 51 | /* SCU registers */ |
| 52 | #define SCU_BASE 0x1e6e2000 |
| 53 | #define SCU_HW_STRAPPING (SCU_BASE + 0x70) |
| 54 | |
| 55 | /* |
| 56 | * AHB Accessors |
| 57 | */ |
| 58 | #ifndef __SKIBOOT__ |
| 59 | #include "io.h" |
| 60 | #else |
| 61 | |
| 62 | /* |
| 63 | * Register accessors, return byteswapped values |
| 64 | * (IE. LE registers) |
| 65 | */ |
| 66 | void ast_ahb_writel(uint32_t val, uint32_t reg); |
| 67 | uint32_t ast_ahb_readl(uint32_t reg); |
| 68 | |
| 69 | /* |
| 70 | * copy to/from accessors. Cannot cross IDSEL boundaries (256M) |
| 71 | */ |
| 72 | int ast_copy_to_ahb(uint32_t reg, const void *src, uint32_t len); |
| 73 | int ast_copy_from_ahb(void *dst, uint32_t reg, uint32_t len); |
| 74 | |
| 75 | void ast_io_init(void); |
| 76 | bool ast_is_ahb_lpc_pnor(void); |
| 77 | |
| 78 | /* UART configuration */ |
| 79 | |
| 80 | bool ast_is_vuart1_enabled(void); |
| 81 | void ast_setup_vuart1(uint16_t io_base, uint8_t irq); |
| 82 | void ast_setup_sio_uart1(uint16_t io_base, uint8_t irq); |
| 83 | void ast_disable_sio_uart1(void); |
| 84 | |
| 85 | /* BT configuration */ |
| 86 | void ast_setup_ibt(uint16_t io_base, uint8_t irq); |
| 87 | |
| 88 | #endif /* __SKIBOOT__ */ |
| 89 | |
| 90 | /* |
| 91 | * SPI Flash controllers |
| 92 | */ |
| 93 | #define AST_SF_TYPE_PNOR 0 |
| 94 | #define AST_SF_TYPE_BMC 1 |
| 95 | #define AST_SF_TYPE_MEM 2 |
| 96 | |
| 97 | struct spi_flash_ctrl; |
| 98 | int ast_sf_open(uint8_t type, struct spi_flash_ctrl **ctrl); |
| 99 | void ast_sf_close(struct spi_flash_ctrl *ctrl); |
| 100 | |
| 101 | |
| 102 | #endif /* __AST_H */ |