| Norman James | 6a58a27 | 2015-10-07 14:34:16 -0500 | [diff] [blame] | 1 | #ifndef __AST_H
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| 2 | #define __AST_H
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| 3 |
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| 4 | /*
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| 5 | * AHB bus registers
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| 6 | */
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| 7 |
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| 8 | /* SPI Flash controller #1 (BMC) */
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| 9 | #define BMC_SPI_FCTL_BASE 0x1E620000
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| 10 | #define BMC_SPI_FCTL_CTRL (BMC_SPI_FCTL_BASE + 0x10)
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| 11 | #define BMC_SPI_FREAD_TIMING (BMC_SPI_FCTL_BASE + 0x94)
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| 12 | #define BMC_FLASH_BASE 0x20000000
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| 13 |
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| 14 | /* SPI Flash controller #2 (PNOR) */
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| 15 | #define PNOR_SPI_FCTL_BASE 0x1E630000
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| 16 | #define PNOR_SPI_FCTL_CONF (PNOR_SPI_FCTL_BASE + 0x00)
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| 17 | #define PNOR_SPI_FCTL_CTRL (PNOR_SPI_FCTL_BASE + 0x04)
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| 18 | #define PNOR_SPI_FREAD_TIMING (PNOR_SPI_FCTL_BASE + 0x14)
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| 19 | #define PNOR_FLASH_BASE 0x30000000
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| 20 |
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| 21 | /* LPC registers */
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| 22 | #define LPC_BASE 0x1e789000
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| 23 | #define LPC_HICR6 (LPC_BASE + 0x80)
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| 24 | #define LPC_HICR7 (LPC_BASE + 0x88)
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| 25 | #define LPC_HICR8 (LPC_BASE + 0x8c)
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| 26 |
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| 27 | /* SCU registers */
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| 28 | #define SCU_BASE 0x1e6e2000
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| 29 | #define SCU_HW_STRAPPING (SCU_BASE + 0x70)
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| 30 |
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| 31 | /*
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| 32 | * AHB Accessors
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| 33 | */
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| 34 | #ifndef __SKIBOOT__
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| 35 | #include "io.h"
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| 36 | #else
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| 37 |
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| 38 | /*
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| 39 | * Register accessors, return byteswapped values
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| 40 | * (IE. LE registers)
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| 41 | */
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| 42 | void ast_ahb_writel(uint32_t val, uint32_t reg);
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| 43 | uint32_t ast_ahb_readl(uint32_t reg);
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| 44 |
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| 45 | /*
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| 46 | * copy to/from accessors. Cannot cross IDSEL boundaries (256M)
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| 47 | */
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| 48 | int ast_copy_to_ahb(uint32_t reg, const void *src, uint32_t len);
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| 49 | int ast_copy_from_ahb(void *dst, uint32_t reg, uint32_t len);
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| 50 |
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| 51 | void ast_io_init(void);
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| 52 |
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| 53 | #endif /* __SKIBOOT__ */
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| 54 |
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| 55 | /*
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| 56 | * SPI Flash controllers
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| 57 | */
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| 58 | #define AST_SF_TYPE_PNOR 0
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| 59 | #define AST_SF_TYPE_BMC 1
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| 60 |
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| 61 | struct spi_flash_ctrl;
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| 62 | int ast_sf_open(uint8_t type, struct spi_flash_ctrl **ctrl);
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| 63 | void ast_sf_close(struct spi_flash_ctrl *ctrl);
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| 64 |
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| 65 |
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| 66 | #endif /* __AST_H */
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