| commit | 22e0bec01e283819c13310640918c89f4a74fb56 | [log] [tgz] |
|---|---|---|
| author | Jason M. Bills <jason.m.bills@linux.intel.com> | Thu Mar 04 12:54:04 2021 -0800 |
| committer | Jason M. Bills <jason.m.bills@linux.intel.com> | Mon Mar 08 12:29:03 2021 -0800 |
| tree | c7ed907b1ee2c4a0723c096a8be8d2a3a8dae3ff | |
| parent | 41a49aa647a3c7458b2c9c5fe90ca26ec79e2b4e [diff] |
Improve graceful power state handling The current timeout of 1 minute for an OS to respond to a graceful shutdown, is not enough for some situations. Extending this to 5 minutes to allow enough time for an OS to gracefully shut down. This causes an issue with the current code which ignores further power change requests during the graceful timeout, which would now block forced shutdown and reset commands for 5 minutes. So, this change also adds support for shutdown and reset commands to be accepted during a graceful shutdown timeout. Tested: Triggered a graceful shutdown and confirmed that it will time out after 5 minutes and that shutdown and reset commands can be issued during that time. Change-Id: Ie88207cbc754a34642b4e1bc9636a257475cdee6 Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>
This repository contains an OpenBMC compliant implementation of power control for x86 servers. It relies on a number of features to do its job. It has several intentional design goals.
At this point in time, this daemon targets Lewisburg based, dual socket x86 server platforms, such as S2600WFT. It is likely that other platforms will work as well.
Because this relies on the hardware passthrough support in the AST2500 to function, it requires a few patches to work correctly.
This patch adds support to UBOOT to keep the passthrough enabled https://github.com/Intel-BMC/openbmc/blob/intel/meta-openbmc-mods/meta-common/ recipes-bsp/u-boot/files/0005-enable-passthrough-in-uboot.patch
The DTS file for your platform will need the following GPIO definitions RESET_BUTTON RESET_OUT POWER_BUTTON POWER_OUT
On an aspeed, these are generally connected to E0, E1, E2, and E3 respectively. An example of this is available in the s2600WF config.
This patch allows the passthrough to be reenabled to the default condition when the appropriate pin is released. This allows power control to take control when needed by a user power action, but leave the hardware in control a majority of the time, reducing the possibility of bricking a system due to a failed BMC.
https://github.com/Intel-BMC/openbmc/blob/intel/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0002-Enable-pass-through-on-GPIOE1-and-GPIOE3-free.patch https://github.com/Intel-BMC/openbmc/blob/intel/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0003-Enable-GPIOE0-and-GPIOE2-pass-through-by-default.patch https://github.com/Intel-BMC/openbmc/blob/intel/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0006-Allow-monitoring-of-power-control-input-GPIOs.patch
Caveats: This implementation does not currently implement the common targets that other implementations do. There were several attempts to, but all ended in timing issues and boot inconsistencies during stress operations.
The POST Complete GPIO is usually held asserted by BIOS after POST complete and de-asserts on reset. This de-assert behavior is currently used to detect warm resets.
Some systems are adding support for a PLT_RST eSPI signal that can be used to more accurately detect warm resets. When this option is enabled, x86-power-control will use PLT_RST to detect warm resets instead of POST Complete.