| From 114bf3bb36fffe6c3c9c5894ebaae5772edb35ff Mon Sep 17 00:00:00 2001 |
| From: Andrew Geissler <andrewg@us.ibm.com> |
| Date: Sat, 28 Feb 2015 12:28:05 -0600 |
| Subject: [PATCH] Revert "SW294127:INITPROC: FSP&Hostboot - fast exit power down" |
| |
| This reverts commit bffe97031429bd5656930f7453c496ce2594e5e6. |
| --- |
| .../mss_draminit_mc/mss_draminit_mc.C | 19 +- |
| src/usr/hwpf/hwp/initfiles/mba_def.initfile | 423 +++++--------------- |
| 2 files changed, 118 insertions(+), 324 deletions(-) |
| |
| diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C |
| index 53f3132..350efb7 100644 |
| --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C |
| +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C |
| @@ -5,7 +5,7 @@ |
| /* */ |
| /* OpenPOWER HostBoot Project */ |
| /* */ |
| -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ |
| +/* Contributors Listed Below - COPYRIGHT 2012,2014 */ |
| /* [+] International Business Machines Corp. */ |
| /* */ |
| /* */ |
| @@ -22,7 +22,7 @@ |
| /* permissions and limitations under the License. */ |
| /* */ |
| /* IBM_PROLOG_END_TAG */ |
| -// $Id: mss_draminit_mc.C,v 1.48 2014/12/05 15:37:43 dcadiga Exp $ |
| +// $Id: mss_draminit_mc.C,v 1.47 2014/09/24 14:48:18 dcadiga Exp $ |
| //------------------------------------------------------------------------------ |
| // *! (C) Copyright International Business Machines Corp. 2011 |
| // *! All Rights Reserved -- Property of IBM |
| @@ -46,7 +46,6 @@ |
| //------------------------------------------------------------------------------ |
| // Version:| Author: | Date: | Comment: |
| //---------|----------|---------|----------------------------------------------- |
| -// 1.48 | dcadiga |05-DEC-14| Powerdown control at initfile |
| // 1.47 | dcadiga |09-SEP-14| Removed SPARE cke disable step |
| // 1.46 | gollub |07-APR-14| Removed call to mss_unmask_inband_errors (moved it to proc_cen_framelock) |
| // 1.45 | dcadiga |14-FEB-14| Periodic Cal Fix for DD2 |
| @@ -255,14 +254,12 @@ ReturnCode mss_draminit_mc_cloned(Target& i_target) |
| |
| // Step Five: Setup Power Management |
| FAPI_INF( "+++ Setting Up Power Management +++"); |
| - FAPI_INF( "+++ POWER MANAGEMENT HANDLED AT INITFILE +++"); |
| - //Procedure commented out because domain reduction enablement now handled at the initfile |
| - //rc = mss_enable_power_management(l_mbaChiplets[i]); |
| - //if(rc) |
| - //{ |
| - // FAPI_ERR("---Error During Power Management Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); |
| - // return rc; |
| - //} |
| + rc = mss_enable_power_management(l_mbaChiplets[i]); |
| + if(rc) |
| + { |
| + FAPI_ERR("---Error During Power Management Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); |
| + return rc; |
| + } |
| |
| } |
| |
| diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile |
| index 61eba9e..88aafb9 100644 |
| --- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile |
| +++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile |
| @@ -1,9 +1,9 @@ |
| -#-- $Id: mba_def.initfile,v 1.70 2014/12/05 16:21:33 yctschan Exp $ |
| + |
| +#-- $Id: mba_def.initfile,v 1.69 2014/09/24 14:44:15 asaetow Exp $ |
| #-- CHANGE HISTORY: |
| #-------------------------------------------------------------------------------- |
| #-- Version:|Author: | Date: | Comment: |
| #-- --------|--------|--------|-------------------------------------------------- |
| -#-- 1.70|yctschan|12/05/14| Updated settings for fast exit power down |
| #-- 1.69|asaetow | 9/24/14| Force SpareCKE sync. Spare DRAM workaround. |
| #-- 1.68|jdsloat | 4/04/14| Turned off Power controls for GA1 concerns - Turn back on at a later date |
| #-- 1.67|tschang | 4/01/14| Adjusted the PUP Avail and SEPD/FEPD time. |
| @@ -144,12 +144,93 @@ define def_equal_test = (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT |
| # <valueType>uint32</valueType> |
| # <enum>DISABLE = 0</enum> |
| |
| +#<attribute> |
| +# <id>ATTR_EFF_DIMM_RANKS_CONFIGED</id> |
| +# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> |
| +# <description>Bit wise representation of master ranks in each DIMM that are used for reads and writes. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. |
| +#Dimensions are [port][dimm] A/B=Mba_0 C/D=Mba_1 There are only two DIMM ranks: DIMM0 and DIMM1 where DIMM0 is the furthest from the centaur. |
| +#creator: mss_eff_cnfg |
| +#consumer: various |
| +#firmware notes: none</description> |
| +# <valueType>uint8</valueType> |
| +# <writeable/> |
| +# <odmVisable/> |
| +# <odmChangeable/> |
| +# <array> 2 2</array> |
| +# <persistRuntime/> |
| +#</attribute> |
| +# |
| +#<attribute> |
| +# <id>ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM</id> |
| +# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> |
| +# <description>Specifies the number of master ranks per DIMM.</description> |
| +# <valueType>uint8</valueType> |
| +# <writeable/> |
| +# <odmVisable/> |
| +# <odmChangeable/> |
| +# <array> 2 2</array> |
| +#</attribute> |
| +# |
| +#<attribute> |
| +# <id>ATTR_EFF_NUM_RANKS_PER_DIMM</id> |
| +# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> |
| +# <description>Number of ranks in each DIMM. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. |
| +#values are 0,1,2, 4 up to 32 |
| +#creator: mss_eff_cnfg |
| +#consumer: various |
| +#firmware notes: none</description> |
| +# <valueType>uint8</valueType> |
| +# <writeable/> |
| +# <odmVisable/> |
| +# <odmChangeable/> |
| +# <array> 2 2</array> |
| +# <persistRuntime/> |
| +#</attribute> |
| +# |
| +#<attribute> |
| +# <id>ATTR_EFF_DRAM_BANKS</id> |
| +# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> |
| +# <description>Number of DRAM banks. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. |
| +#creator: mss_eff_cnfg |
| +#consumer: various |
| +#firmware notes: none</description> |
| +# <valueType>uint8</valueType> |
| +# <writeable/> |
| +# <odmVisable/> |
| +# <odmChangeable/> |
| +#</attribute> |
| +# |
| +#<attribute> |
| +# <id>ATTR_EFF_DRAM_ROWS</id> |
| +# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> |
| +# <description>Number of DRAM rows. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. |
| +#creator: mss_eff_cnfg |
| +#consumer: various |
| +#firmware notes: none</description> |
| +# <valueType>uint8</valueType> |
| +# <writeable/> |
| +# <odmVisable/> |
| +# <odmChangeable/> |
| +#</attribute> |
| +# |
| +#<attribute> |
| +# <id>ATTR_EFF_DRAM_COLS</id> |
| +# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> |
| +# <description>Number of DRAM columns. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. |
| +#creator: mss_eff_cnfg |
| +#consumer: various |
| +#firmware notes: none</description> |
| +# <valueType>uint8</valueType> |
| +# <writeable/> |
| +# <odmVisable/> |
| +# <odmChangeable/> |
| +#</attribute |
| |
| |
| # mba tmr0 register timings are added to the value below |
| define def_margin1 = (1); |
| define def_margin2 = (0); |
| -define def_margin_pup_fast = (0); |
| +define def_margin_pup_fast = (7); |
| define def_margin_pup_slow = (0); |
| define def_margin_rdtag = (4); |
| |
| @@ -263,22 +344,6 @@ define def_C3c_C4C_ddr4 = ((def_2b_1socket_ddr4)||(def_2b_ |
| define def_C4A_ddr4 = ((def_2a_1socket_ddr4)||(def_2a_2socket_ddr4)||(def_3a_ddr4_cdimm )||(def_7a_1socket_ddr4)||(def_7a_2socket_ddr4)||(def_3a_1socket_ddr4)||(def_3a_2socket_ddr4)||(def_4a_ddr4_cdimm)); |
| define def_IS5D = ((def_5d_1socket )||(def_5d_2socket)); |
| |
| -# ODT Mappings |
| -define def_odt_mapping_1a = (def_1a_1socket); |
| -define def_odt_mapping_1b1dimm = (def_1b_1socket ||def_3a_1socket ||def_3a_1socket_ddr4 ||def_3b_1socket ||def_3c_1socket_ddr4); |
| -define def_odt_mapping_1b2dimm = (def_3c_2socket_ddr4 ||def_1b_2socket ||def_3a_2socket ||def_3a_2socket_ddr4 ||def_3b_2socket); |
| -#define def_odt_mapping_1bcdimm = (def_1a_2socket ||def_1b_cdimm ||def_3a_cdimm ||def_3a_ddr4_cdimm ||def_3b_cdimm ||def_3b_ddr4_cdimm ||def_3c_cdimm ||def_3c_ddr4_cdimm); |
| -define def_odt_mapping_1bcdimm = (def_1a_2socket ||def_3a_cdimm ||def_3a_ddr4_cdimm ||def_3b_cdimm ||def_3b_ddr4_cdimm ||def_3c_cdimm ||def_3c_ddr4_cdimm); |
| -define def_odt_mapping_1c2dimm = (def_1c_2socket_odt); |
| -define def_odt_mapping_1c1dimm = (def_1c_1socket_odt); |
| -define def_odt_mapping_1ccdimm = (def_1c_cdimm ||def_4a_cdimm ||def_4a_ddr4_cdimm ||def_4b_ddr4_cdimm ||def_4c_ddr4_cdimm); |
| -define def_odt_mapping_1dx82dimm = (def_1d_2socket); |
| -define def_odt_mapping_1dx4 = (def_1d_1socket); |
| -define def_odt_mapping_2abc = (def_2a_1socket ||def_2a_2socket ||def_2a_1socket_ddr4 ||def_2a_2socket_ddr4 ||def_2a_cdimm ||def_2a_ddr4_cdimm ||def_2b_1socket ||def_2b_2socket ||def_2b_1socket_ddr4 ||def_2b_2socket_ddr4 ||def_2b_cdimm ||def_2b_ddr4_cdimm ||def_2c_1socket ||def_2c_2socket ||def_2c_1socket_ddr4 ||def_2c_2socket_ddr4 ||def_2c_ddr4_cdimm); |
| -define def_odt_mapping_56781lrdm = (def_5b_1socket ||def_5c_1socket ||def_7a_1socket ||def_7a_1socket_ddr4 ||def_7b_1socket ||def_7b_1socket_ddr4 ||def_7c_1socket ||def_7c_1socket_ddr4); |
| -define def_odt_mapping_56782lrdm = (def_5b_2socket ||def_5c_2socket ||def_7a_2socket ||def_7a_2socket_ddr4 ||def_7b_2socket ||def_7b_2socket_ddr4 ||def_7c_2socket ||def_7c_2socket_ddr4); |
| -define def_odt_mapping_5d1dimm = (def_5d_1socket); |
| -define def_odt_mapping_5d2dimm = (def_5d_2socket); |
| |
| |
| #gdial std_size ( MBA_SRQ.mba_tmr1q_cfg_tfaw, MBA_SRQ.pc.MBAREF0Q_cfg_trfc, MBA_SRQ.pc.MBAREF0Q_cfg_refr_tsv_stack, MBA_SRQ.pc.MBARPC0Q_cfg_pup_pdn, MBA_SRQ.pc.MBARPC0Q_cfg_pdn_pup, MBA_SRQ.pc.MBARPC0Q_cfg_pup_avail, MBA_SRQ.mba_tmr0q_RRSMSR_dly , MBA_SRQ.mba_tmr0q_RRSMDR_dly, MBA_SRQ.mba_tmr0q_WWSMSR_dly, MBA_SRQ.mba_tmr0q_WWSMDR_dly , MBA_SRQ.MBA_TMR0Q_Trrd, MBA_SRQ.srqdbg.cfg_std_size_id)= |
| @@ -1944,31 +2009,29 @@ scom 0x03010432 { |
| # |
| scom 0x03010434 { |
| bits , scom_data , ATTR_FUNCTIONAL, expr; |
| - 2 , 0b0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 0); # cfg_min_max_domains 36 |
| - 2 , 0b1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED != 0); # cfg_min_max_domains 36 |
| -# 3:5 , 0b001 , 1 , any; # cfg_min_max_domains 36 |
| - 6:10 , 0b00100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail - performance enhancemnt |
| - 6:10 , 0b00011 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail - performance enhancemnt |
| - 6:10 , 0b00101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b00100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b00110 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b00101 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b00111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b00110 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b01000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b00111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b01101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b01100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b10000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b01111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b10100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b10011 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b10111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b10110 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b11010 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b11001 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b11101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| - 6:10 , 0b11100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 |
| +# 3:5 , 0b010 , 1 , any; # cfg_min_max_domains 36 |
| + 6:10 , 0b00100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail - performance enhancemnt |
| + 6:10 , 0b00100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail - performance enhancemnt |
| + 6:10 , 0b00101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b00101 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b00110 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b00110 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b00111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b00111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b01000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b01000 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b01101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b01101 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b10000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b10000 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b10100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b10100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b10111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b10111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b11010 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b11010 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b11101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36 |
| + 6:10 , 0b11101 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36 |
| 11:15 , 0b00011 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly3 == 1); # MBARPC0Q_cfg_pup_pup 37 |
| 11:15 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly4 == 1); # MBARPC0Q_cfg_pup_pup 37 |
| 11:15 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly5 == 1); # MBARPC0Q_cfg_pup_pup 37 |
| @@ -1977,286 +2040,20 @@ scom 0x03010434 { |
| 16:20 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly4 == 1); # MBARPC0Q_cfg_pup_pdn 38 |
| 16:20 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly5 == 1); # MBARPC0Q_cfg_pup_pdn 38 |
| 16:20 , 0b00110 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly6 == 1); # MBARPC0Q_cfg_pup_pdn 38 |
| - 22 , 0b0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 0); |
| - 22 , 0b1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED != 0); |
| + 22 , 0b0 , 1 , any; # cfg_min_domain_reduction_enable set to 1 to enable power controls |
| 23:32 , 0b0000000011, 1 , any; # Set min doman reduction time to 30.7 us (10.245us * 3) |
| 42 , 0b1 , 1 , any; # Force SpareCKE sync |
| - 43 , 0b1 , 1 , any; # Use 1 in 8k 2:1 cycle pulses for min domain reduction time interval |
| + 43 , 0b0 , 1 , any; # Use 1 in 8k 2:1 cycle pulses for min domain reduction time interval |
| } |
| |
| -# had to shifts the data to be able to get it into the proper positions |
| -define shift_pwr_map1 = (ATTR_VPD_CKE_PWR_MAP >> 60); |
| -define shift_pwr_map2 = (ATTR_VPD_CKE_PWR_MAP >> 56); |
| -define shift_pwr_map3 = (ATTR_VPD_CKE_PWR_MAP >> 52); |
| -define shift_pwr_map4 = (ATTR_VPD_CKE_PWR_MAP >> 48); |
| -define shift_pwr_map5 = (ATTR_VPD_CKE_PWR_MAP >> 44); |
| -define shift_pwr_map6 = (ATTR_VPD_CKE_PWR_MAP >> 40); |
| -define shift_pwr_map7 = (ATTR_VPD_CKE_PWR_MAP >> 36); |
| -define shift_pwr_map8 = (ATTR_VPD_CKE_PWR_MAP >> 32); |
| -define shift_pwr_map9 = (ATTR_VPD_CKE_PWR_MAP >> 28); |
| -define shift_pwr_map10 = (ATTR_VPD_CKE_PWR_MAP >> 24); |
| -define shift_pwr_map11 = (ATTR_VPD_CKE_PWR_MAP >> 20); |
| -define shift_pwr_map12 = (ATTR_VPD_CKE_PWR_MAP >> 16); |
| -define shift_pwr_map13 = (ATTR_VPD_CKE_PWR_MAP >> 12); |
| -define shift_pwr_map14 = (ATTR_VPD_CKE_PWR_MAP >> 8); |
| -define shift_pwr_map15 = (ATTR_VPD_CKE_PWR_MAP >> 4); |
| - |
| # MBAPC1Q power control settings reg 1 |
| # |
| scom 0x03010435 { |
| bits , scom_data , ATTR_FUNCTIONAL, expr; |
| - 0:3 , shift_pwr_map1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk0_rd_cke 36 |
| - 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 0:3 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 0:3 , 0x9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 0:3 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 0:3 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); # cfg_mrnk0_rd_cke 36 |
| - 4:7 , shift_pwr_map2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 4:7 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk1_rd_cke 36 |
| - 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 4:7 , 0xE , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 4:7 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 4:7 , 0x5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 4:7 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 4:7 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 4:7 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 4:7 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 4:7 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| - 8:11 , shift_pwr_map3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk2_rd_cke 36 |
| - 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 8:11 , 0x9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 8:11 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 8:11 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 8:11 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 8:11 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 8:11 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| - 12:15 , shift_pwr_map4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk3_rd_cke 36 |
| - 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 12:15 , 0x5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 12:15 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 12:15 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 12:15 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 12:15 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 12:15 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| - 16:19 , shift_pwr_map5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk4_rd_cke 36 |
| - 16:19 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 16:19 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 16:19 , 0xA , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 16:19 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 16:19 , 0x3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 16:19 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 16:19 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 16:19 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 16:19 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| - 20:23 , shift_pwr_map6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk5_rd_cke 36 |
| - 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 20:23 , 0xB , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 20:23 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 20:23 , 0x9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 20:23 , 0x3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 20:23 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 20:23 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 20:23 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 20:23 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| -} |
| - |
| - |
| -scom 0x03010435 { |
| - bits , scom_data , ATTR_FUNCTIONAL, expr; |
| - 24:27 , shift_pwr_map7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk6_rd_cke 37 |
| - 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 24:27 , 0xA , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 24:27 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 24:27 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 24:27 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| - 28:31 , shift_pwr_map8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk7_rd_cke 37 |
| - 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 28:31 , 0x9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 28:31 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 28:31 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 28:31 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| - 32:35 , shift_pwr_map9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk0_wr_cke 38 |
| - 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 32:35 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 32:35 , 0xA , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 32:35 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 32:35 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 32:35 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 32:35 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 32:35 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 36:39 , shift_pwr_map10, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 32:35 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); # cfg_mrnk0_wr_cke 38 |
| - 36:39 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); |
| - 36:39 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 36:39 , 0xE , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 36:39 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 36:39 , 0x6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 36:39 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 36:39 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 36:39 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 36:39 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 36:39 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 36:39 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 36:39 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 36:39 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 36:39 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| - 40:43 , shift_pwr_map11, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk2_wr_cke 38 |
| - 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 40:43 , 0xA , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 40:43 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 40:43 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 40:43 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 40:43 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 40:43 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| - 44:47 , shift_pwr_map12, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk3_wr_cke 38 |
| - 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 44:47 , 0x6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 44:47 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 44:47 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 44:47 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 44:47 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 44:47 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| + 0:63 , ATTR_VPD_CKE_PWR_MAP , 1 , any; # data from VP now |
| } |
| |
| |
| -scom 0x03010435 { |
| - bits , scom_data , ATTR_FUNCTIONAL, expr; |
| - 48:51 , shift_pwr_map13, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk4_wr_cke 38 |
| - 48:51 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 48:51 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 48:51 , 0x6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 48:51 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 48:51 , 0x3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 48:51 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 48:51 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 48:51 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 48:51 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| - 52:55 , shift_pwr_map14, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk5_wr_cke 38 |
| - 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 52:55 , 0xB , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 52:55 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 52:55 , 0x5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 52:55 , 0x3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 52:55 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 52:55 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 52:55 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 52:55 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| - 56:59 , shift_pwr_map15, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk6_wr_cke 38 |
| - 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 56:59 , 0x6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 56:59 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 56:59 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 56:59 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| - 60:63 , ATTR_VPD_CKE_PWR_MAP, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown |
| - 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk7_wr_cke 38 |
| - 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1); |
| - 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1); |
| - 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1); |
| - 60:63 , 0x5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1); |
| - 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1); |
| - 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1); |
| - 60:63 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1); |
| - 60:63 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1); |
| - 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1); |
| - 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1); |
| - 60:63 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1); |
| - 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1); |
| - 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); |
| -} |
| |
| ########################### |
| # MBA CKE mapping tables # |
| -- |
| 1.7.4.1 |
| |