openpower/patches/vesnin-patches/occ/occ-0001-Add-DIMM-temperature-sensors.patch

From 7d9fc8ec22199e7fc7eca6079cb42f25554851f7 Mon Sep 17 00:00:00 2001
From: Artem Senichev <a.senichev@yadro.com>
Date: Tue, 13 Mar 2018 14:17:00 +0300
Subject: [PATCH] Add DIMM temperature sensors

Customize/override 0xFF temp_sid based on the different CPU/Cen/DIMM index
which can be decoded by OpenBMC accordingly.
See also: hostboot-0005-Fill-empty-sensor-id-to-reserved-id-0xFF.patch.

Originally created by MSI (S188)

Signed-off-by: Artem Senichev <a.senichev@yadro.com>
---
 src/occ/cmdh/cmdh_fsp_cmds.c | 54 ++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 52 insertions(+), 2 deletions(-)

diff --git a/src/occ/cmdh/cmdh_fsp_cmds.c b/src/occ/cmdh/cmdh_fsp_cmds.c
index 74e45da..fb2f72d 100755
--- a/src/occ/cmdh/cmdh_fsp_cmds.c
+++ b/src/occ/cmdh/cmdh_fsp_cmds.c
@@ -355,10 +355,40 @@ ERRL_RC cmdh_poll_v10(cmdh_fsp_rsp_t * o_rsp_ptr)
     l_sensorHeader.length = sizeof(cmdh_poll_temp_sensor_t);
     l_sensorHeader.count  = 0;
 
+    uint16_t CpuIpmiId = 0;
+
+    //Check the current OCC
+    if (l_poll_rsp->occ_pres_mask == 0x02)
+    {
+        CpuIpmiId = 0x0D;  //CPU1
+    }
+    else if (l_poll_rsp->occ_pres_mask == 0x04)
+    {
+        CpuIpmiId = 0x02;  //CPU2
+    }
+    else if (l_poll_rsp->occ_pres_mask == 0x08)
+    {
+        CpuIpmiId = 0x0A;  //CPU3
+    }
+    else
+    {
+        CpuIpmiId = 0x0B;  //CPU0
+    }
+
     //Initialize to max number of possible temperature sensors.
-    cmdh_poll_temp_sensor_t l_tempSensorList[MAX_NUM_CORES + MAX_NUM_MEM_CONTROLLERS + (MAX_NUM_MEM_CONTROLLERS * NUM_DIMMS_PER_CENTAUR)];
+    cmdh_poll_temp_sensor_t l_tempSensorList[MAX_NUM_CORES + MAX_NUM_MEM_CONTROLLERS + (MAX_NUM_MEM_CONTROLLERS * NUM_DIMMS_PER_CENTAUR) + 2]; //Add two items for peak/average core temperature.
     memset(l_tempSensorList, 0x00, sizeof(l_tempSensorList));
 
+    //The average value of core temperature. Currently not used.
+    l_tempSensorList[l_sensorHeader.count].id = G_amec_sensor_list[TEMP2MSP0]->ipmi_sid;
+    l_tempSensorList[l_sensorHeader.count].value = G_amec_sensor_list[TEMP2MSP0]->sample;
+    l_sensorHeader.count++;
+
+    //The peak value of core temperature
+    l_tempSensorList[l_sensorHeader.count].id = CpuIpmiId;
+    l_tempSensorList[l_sensorHeader.count].value = G_amec_sensor_list[TEMP2MSP0PEAK]->sample;
+    l_sensorHeader.count++;
+
     for (k=0; k<MAX_NUM_CORES; k++)
     {
         if(CORE_PRESENT(k))
@@ -370,6 +400,26 @@ ERRL_RC cmdh_poll_v10(cmdh_fsp_rsp_t * o_rsp_ptr)
     }
 
     uint8_t l_cent, l_dimm = 0;
+    uint16_t CpuId = 0;
+
+    //Check the current OCC
+    if(l_poll_rsp->occ_pres_mask == 0x02)
+    {
+        CpuId = 0x0200;  //CPU1
+    }
+    else if (l_poll_rsp->occ_pres_mask == 0x04)
+    {
+        CpuId = 0x0300;  //CPU2
+    }
+    else if (l_poll_rsp->occ_pres_mask == 0x08)
+    {
+        CpuId = 0x0400;  //CPU3
+    }
+    else
+    {
+        CpuId = 0x0100;  //CPU0
+    }
+
     for (l_cent=0; l_cent < MAX_NUM_MEM_CONTROLLERS; l_cent++)
     {
         if (CENTAUR_PRESENT(l_cent))
@@ -391,7 +441,7 @@ ERRL_RC cmdh_poll_v10(cmdh_fsp_rsp_t * o_rsp_ptr)
             {
                 if (g_amec->proc[0].memctl[l_cent].centaur.dimm_temps[l_dimm].temp_sid != 0)
                 {
-                    l_tempSensorList[l_sensorHeader.count].id = g_amec->proc[0].memctl[l_cent].centaur.dimm_temps[l_dimm].temp_sid;
+                    l_tempSensorList[l_sensorHeader.count].id = CpuId + (l_cent * 8) + l_dimm;  //Add extra temperature IDs for all DIMMs.
                     //If a dimm timed out long enough, we should return 0xFFFF for that sensor.
                     if (G_dimm_temp_expired_bitmap.bytes[l_cent] & (DIMM_SENSOR0 >> l_dimm))
                     {
-- 
2.14.1