blob: da515871bb59f24d71aabccc67849a2aaaf0e1de [file] [log] [blame]
Sachin Guptaa0848b72017-07-12 00:43:03 -05001From bee7283419489e911b3e2f44ca96bf1ac12264e5 Mon Sep 17 00:00:00 2001
2From: Sachin Gupta <sgupta2m@in.ibm.com>
3Date: Thu, 6 Jul 2017 12:33:32 -0500
4Subject: [PATCH] Restore backward compatibilty of SBE image with HB/HWSV
5
6Change-Id: I2eba38a5d5a254c9595ee49e56f65b6c7ded67a6
7Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42819
8Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
9Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
10Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
11Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
12Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42822
13Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
14---
15 .../p9/procedures/hwp/perv/p9_sbe_attr_setup.C | 24 ++++++++++++++++++++++
16 1 file changed, 24 insertions(+)
17
18diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
19index 03f1530..bf7b129 100644
20--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
21+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
22@@ -233,6 +233,30 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
23 l_read_scratch_reg.extractToRight<ATTR_OB2_PLL_BUCKET_STARTBIT, ATTR_OB2_PLL_BUCKET_LENGTH>(l_ob2_pll_bucket);
24 l_read_scratch_reg.extractToRight<ATTR_OB3_PLL_BUCKET_STARTBIT, ATTR_OB3_PLL_BUCKET_LENGTH>(l_ob3_pll_bucket);
25
26+ // Workaround to handle backward compatibilty
27+ // Old drivers will keep MBX OBUS PLL bucket value as zero. So
28+ // change it to 1 to make old drivers compatible with new SBE
29+ // image
30+ if( 0 == l_ob0_pll_bucket )
31+ {
32+ l_ob0_pll_bucket = 1;
33+ }
34+
35+ if( 0 == l_ob1_pll_bucket )
36+ {
37+ l_ob1_pll_bucket = 1;
38+ }
39+
40+ if( 0 == l_ob2_pll_bucket )
41+ {
42+ l_ob2_pll_bucket = 1;
43+ }
44+
45+ if( 0 == l_ob3_pll_bucket )
46+ {
47+ l_ob3_pll_bucket = 1;
48+ }
49+
50 FAPI_DBG("Setting up ATTR_I2C_BUS_DIV_REF");
51 FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4));
52
53--
541.8.2.2
55