Gitiles
Code Review Sign In
gerrit.openbmc.org / premsjha / op-build / 9c27790d49149ff54828b5252881e7f3812f1c84 / . / openpower / package / hostboot-p10 / 0001-Ring-Table-Update-v23.patch
blob: 49145ccd69a9ca9af749e7fee7104765c40a1610 [file] [log] [blame]
Bill Hoffa50b31f42020-06-19 14:04:55 -0500[diff] [blame]1From 6cffa855d0d8160ea8a38e57fc226374d648a10b Mon Sep 17 00:00:00 2001
2From: Joe McGill <jmcgill@us.ibm.com>
3Date: Thu, 4 Jun 2020 23:40:01 -0400
4Subject: [PATCH] Ring Table Update (v23)
5
6split fure ring definitions into separate func, regf definitions
7
8add PLL bucket rings with minimal changes to support build,
9subsequent commits will add mailbox infrastructure support
10- mc_pll_bndy, total of 8
11- iohs_pll_bndy, total of 16
12- perv_pll_bndy, total of 4
13- pci_pll_bndy, total of 4
14
15remove unused ring definitions (NDL, retime only rings)
16
17Infrastructure adds:
18- Removed "root" *_bndy ring from the RingOffset list since it's
19 never used (only it's derivative _buckets are used)
20- Detection and filtering out of Mvpd rings, like ec_cl2_gptr,
21 which accidentally end up in the raw base ring folders for
22 SBE and QME (note this should be a fail since it indicates
23 a fundamental mislocation of the ring),
24- Implemented a check to verify that the Rs4 header's ringId
25 matches the requested ringId when retrieving a ring in TOR API.
26
27Change-Id: Iaef7ad51af363c0bb50eeb9a4bb3aeb2cc20efc3
28CQ: HW531549
29Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/98051
30Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
31Dev-Ready: Joseph J McGill <jmcgill@us.ibm.com>
32Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
33Reviewed-by: Claus M Olsen <cmolsen@us.ibm.com>
34Reviewed-by: Kahn C Evans <kahnevan@us.ibm.com>
35Reviewed-by: Joseph J McGill <jmcgill@us.ibm.com>
36---
37 .../chips/common/utils/imageProcs/common_ringId.H | 1 +
38 .../p10/common/include/p10_frequency_buckets.H | 39 +-
39 .../procedures/hwp/lib/p10_hcode_image_defines.H | 3 +-
40 .../xml/attribute_info/p10_freq_attributes.xml | 3 +
41 .../attribute_info/p10_pervasive_attributes.xml | 18 +
42 .../xml/attribute_info/p10_sbe_attributes.xml | 8 +
43 .../chips/p10/utils/imageProcs/p10_ring_id.H | 226 +++---
44 .../p10/utils/imageProcs/p10_ring_properties.H | 838 ++++++++++++---------
45 src/import/chips/p10/utils/imageProcs/p10_tor.C | 11 +
46 9 files changed, 684 insertions(+), 463 deletions(-)
47
48diff --git a/src/import/chips/common/utils/imageProcs/common_ringId.H b/src/import/chips/common/utils/imageProcs/common_ringId.H
49index e9cbad5..1b875e2 100644
50--- a/src/import/chips/common/utils/imageProcs/common_ringId.H
51+++ b/src/import/chips/common/utils/imageProcs/common_ringId.H
52@@ -351,6 +351,7 @@ typedef struct
53 #define TOR_INVALID_RS4_MAGIC INFRASTRUCT_NOOF_RCS + 24
54 #define TOR_INVALID_RS4_VERSION INFRASTRUCT_NOOF_RCS + 25
55 #define TOR_INVALID_RS4_TYPE INFRASTRUCT_NOOF_RCS + 26
56+#define TOR_RING_ID_MISMATCH INFRASTRUCT_NOOF_RCS + 27 //ringId and Rs4 mismatch
57
58 // This function returns the main ring properties list associated w/the chip ID.
59 int ringid_get_ringProps( ChipId_t i_chipId,
60diff --git a/src/import/chips/p10/common/include/p10_frequency_buckets.H b/src/import/chips/p10/common/include/p10_frequency_buckets.H
61index 05204fd..b91680e 100644
62--- a/src/import/chips/p10/common/include/p10_frequency_buckets.H
63+++ b/src/import/chips/p10/common/include/p10_frequency_buckets.H
64@@ -42,6 +42,41 @@ enum p10_refclock_freq_t
65
66
67 //
68+// PCI
69+//
70+
71+// constant defining number of PCI PLL frequency options ('buckets')
72+// to be built into unsigned HW image (currently used/max)
73+const uint8_t P10_NUM_PCI_PLL_BUCKETS = 1;
74+const uint8_t P10_MAX_PCI_PLL_BUCKETS = 4;
75+
76+// PCI PLL bucket descriptor, defines bucket properties in terms of:
77+// - required input reference clock freqeuncy (KHz)
78+// - resultant output grid frequency (MHz)
79+// - resultant output link frequency (MHz)
80+struct p10_pci_pll_bucket_descriptor_t
81+{
82+ p10_refclock_freq_t refclock_freq_khz; // PLL input frequency (KHz)
83+ uint32_t freq_grid_mhz; // PCI chiplet grid frequency (MHz) ATTR_FREQ_PCIE_MHZ
84+};
85+
86+const p10_pci_pll_bucket_descriptor_t P10_PCI_PLL_BUCKETS[P10_NUM_PCI_PLL_BUCKETS] =
87+{
88+ { REFCLOCK_FREQ_100, 2000 },
89+};
90+
91+
92+//
93+// filter PLLs
94+//
95+
96+// constant defining number of filter PLL frequency options ('buckets')
97+// to be built into unsigned HW image (currently used/max)
98+const uint8_t P10_NUM_FILTER_PLL_BUCKETS = 1;
99+const uint8_t P10_MAX_FILTER_PLL_BUCKETS = 4;
100+
101+
102+//
103 // MC
104 //
105
106@@ -51,7 +86,7 @@ const uint8_t P10_NUM_MC_PLL_BUCKETS = 4;
107 const uint8_t P10_MAX_MC_PLL_BUCKETS = 8;
108
109 // MC PLL bucket descriptor, defines bucket properties in terms of:
110-// - required input referecnce clock freqeuncy (KHz)
111+// - required input reference clock freqeuncy (KHz)
112 // - resultant output grid frequency (MHz)
113 // - resultant output link frequency (MHz)
114 struct p10_mc_pll_bucket_descriptor_t
115@@ -78,7 +113,7 @@ const p10_mc_pll_bucket_descriptor_t P10_MC_PLL_BUCKETS[P10_NUM_MC_PLL_BUCKETS]
116 // constant definining number of IOHS PLL frequency options ('buckets')
117 // to be built into unsigned HW image (currently used/max)
118 const uint8_t P10_NUM_IOHS_PLL_BUCKETS = 6;
119-const uint8_t P10_MAX_IOHS_PLL_BUCKETS = 8;
120+const uint8_t P10_MAX_IOHS_PLL_BUCKETS = 16;
121
122 // IOHS PLL bucket descriptor, defines bucket properties in terms of:
123 // - required input reference clock frequency (KHz)
124diff --git a/src/import/chips/p10/procedures/hwp/lib/p10_hcode_image_defines.H b/src/import/chips/p10/procedures/hwp/lib/p10_hcode_image_defines.H
125index dc7cc4b..ae2b8c0 100644
126--- a/src/import/chips/p10/procedures/hwp/lib/p10_hcode_image_defines.H
127+++ b/src/import/chips/p10/procedures/hwp/lib/p10_hcode_image_defines.H
128@@ -346,8 +346,7 @@ enum ImgBldRetCode_t
129 XGPE_SRAM_IMG_SIZE_ERR = 32,
130 PGPE_SRAM_IMG_SIZE_ERR = 33,
131 BUILD_FAIL_PGPE_PPMR = 34,
132- BUILD_FAIL_RING_SEL_EQ_INEX = 35,
133- BUILD_FAIL_XIP_CUST_ERR = 36,
134+ BUILD_FAIL_XIP_CUST_ERR = 35,
135 BUILD_ERR_INTERNAL = 0xffff,
136 };
137
138diff --git a/src/import/chips/p10/procedures/xml/attribute_info/p10_freq_attributes.xml b/src/import/chips/p10/procedures/xml/attribute_info/p10_freq_attributes.xml
139index 72ce8ba..7d3e625 100644
140--- a/src/import/chips/p10/procedures/xml/attribute_info/p10_freq_attributes.xml
141+++ b/src/import/chips/p10/procedures/xml/attribute_info/p10_freq_attributes.xml
142@@ -245,6 +245,9 @@
143 Provided by the MRW.
144 </description>
145 <valueType>uint32</valueType>
146+ <enum>
147+ 2000 = 2000
148+ </enum>
149 <platInit/>
150 </attribute>
151 <!-- ********************************************************************** -->
152diff --git a/src/import/chips/p10/procedures/xml/attribute_info/p10_pervasive_attributes.xml b/src/import/chips/p10/procedures/xml/attribute_info/p10_pervasive_attributes.xml
153index fda1662..1787680 100755
154--- a/src/import/chips/p10/procedures/xml/attribute_info/p10_pervasive_attributes.xml
155+++ b/src/import/chips/p10/procedures/xml/attribute_info/p10_pervasive_attributes.xml
156@@ -117,6 +117,24 @@
157 </attribute>
158 <!-- ********************************************************************** -->
159 <attribute>
160+ <id>ATTR_FILTER_PLL_BUCKET</id>
161+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
162+ <description>Filter pll bucket selection</description>
163+ <valueType>uint8</valueType>
164+ <writeable/>
165+ <initToZero/>
166+</attribute>
167+<!-- ********************************************************************** -->
168+<attribute>
169+ <id>ATTR_PCI_PLL_BUCKET</id>
170+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
171+ <description>PCI pll bucket selection</description>
172+ <valueType>uint8</valueType>
173+ <writeable/>
174+ <initToZero/>
175+</attribute>
176+<!-- ********************************************************************** -->
177+<attribute>
178 <id>ATTR_CP_PLLTODFLT_BYPASS</id>
179 <targetType>TARGET_TYPE_PROC_CHIP</targetType>
180 <description>
181diff --git a/src/import/chips/p10/procedures/xml/attribute_info/p10_sbe_attributes.xml b/src/import/chips/p10/procedures/xml/attribute_info/p10_sbe_attributes.xml
182index d3ee1ab..8a573b0 100644
183--- a/src/import/chips/p10/procedures/xml/attribute_info/p10_sbe_attributes.xml
184+++ b/src/import/chips/p10/procedures/xml/attribute_info/p10_sbe_attributes.xml
185@@ -284,6 +284,14 @@
186 </entry>
187 <!-- sampled: mailbox 6 -->
188 <entry>
189+ <name>ATTR_FILTER_PLL_BUCKET</name>
190+ <value>0x0</value>
191+ </entry>
192+ <entry>
193+ <name>ATTR_PCI_PLL_BUCKET</name>
194+ <value>0x0</value>
195+ </entry>
196+ <entry>
197 <name>ATTR_CP_PLLTODFLT_BYPASS</name>
198 <value>0x0</value>
199 </entry>
200diff --git a/src/import/chips/p10/utils/imageProcs/p10_ring_id.H b/src/import/chips/p10/utils/imageProcs/p10_ring_id.H
201index 8f695bc..0224d79 100644
202--- a/src/import/chips/p10/utils/imageProcs/p10_ring_id.H
203+++ b/src/import/chips/p10/utils/imageProcs/p10_ring_id.H
204@@ -39,8 +39,8 @@ enum RingID
205 perv_occ_time = 2, //0x02
206 pib_repr = 3, //0x03
207 sbe_gptr = 4, //0x04
208- sbe_repr = 5, //0x05
209- sbe_time = 6, //0x06
210+ // hole_ring: 5, //0x05
211+ // hole_ring: 6, //0x06
212 // hole_ring: 7, //0x07
213 perv_dpll_gptr = 8, //0x08
214 perv_pll_gptr = 9, //0x09
215@@ -94,9 +94,9 @@ enum RingID
216 iohs0_gptr = 57, //0x39
217 iohs0_repr = 58, //0x3A
218 iohs0_time = 59, //0x3B
219- iohs0_ndl_gptr = 60, //0x3C
220- iohs0_ndl_repr = 61, //0x3D
221- iohs0_ndl_time = 62, //0x3E
222+ // hole_ring: 60, //0x3C
223+ // hole_ring: 61, //0x3D
224+ // hole_ring: 62, //0x3E
225 iohs0_pdl_gptr = 63, //0x3F
226 iohs0_pdl_repr = 64, //0x40
227 iohs0_pdl_time = 65, //0x41
228@@ -104,9 +104,9 @@ enum RingID
229 iohs1_gptr = 67, //0x43
230 iohs1_repr = 68, //0x44
231 iohs1_time = 69, //0x45
232- iohs1_ndl_gptr = 70, //0x46
233- iohs1_ndl_repr = 71, //0x47
234- iohs1_ndl_time = 72, //0x48
235+ // hole_ring: 70, //0x46
236+ // hole_ring: 71, //0x47
237+ // hole_ring: 72, //0x48
238 iohs1_pdl_gptr = 73, //0x49
239 iohs1_pdl_repr = 74, //0x4A
240 iohs1_pdl_time = 75, //0x4B
241@@ -114,9 +114,9 @@ enum RingID
242 iohs2_gptr = 77, //0x4D
243 iohs2_repr = 78, //0x4E
244 iohs2_time = 79, //0x4F
245- iohs2_ndl_gptr = 80, //0x50
246- iohs2_ndl_repr = 81, //0x51
247- iohs2_ndl_time = 82, //0x52
248+ // hole_ring: 80, //0x50
249+ // hole_ring: 81, //0x51
250+ // hole_ring: 82, //0x52
251 iohs2_pdl_gptr = 83, //0x53
252 iohs2_pdl_repr = 84, //0x54
253 iohs2_pdl_time = 85, //0x55
254@@ -124,9 +124,9 @@ enum RingID
255 iohs3_gptr = 87, //0x57
256 iohs3_repr = 88, //0x58
257 iohs3_time = 89, //0x59
258- iohs3_ndl_gptr = 90, //0x5A
259- iohs3_ndl_repr = 91, //0x5B
260- iohs3_ndl_time = 92, //0x5C
261+ // hole_ring: 90, //0x5A
262+ // hole_ring: 91, //0x5B
263+ // hole_ring: 92, //0x5C
264 iohs3_pdl_gptr = 93, //0x5D
265 iohs3_pdl_repr = 94, //0x5E
266 iohs3_pdl_time = 95, //0x5F
267@@ -134,9 +134,9 @@ enum RingID
268 iohs4_gptr = 97, //0x61
269 iohs4_repr = 98, //0x62
270 iohs4_time = 99, //0x63
271- iohs4_ndl_gptr = 100, //0x64
272- iohs4_ndl_repr = 101, //0x65
273- iohs4_ndl_time = 102, //0x66
274+ // hole_ring: 100, //0x64
275+ // hole_ring: 101, //0x65
276+ // hole_ring: 102, //0x66
277 iohs4_pdl_gptr = 103, //0x67
278 iohs4_pdl_repr = 104, //0x68
279 iohs4_pdl_time = 105, //0x69
280@@ -144,9 +144,9 @@ enum RingID
281 iohs5_gptr = 107, //0x6B
282 iohs5_repr = 108, //0x6C
283 iohs5_time = 109, //0x6D
284- iohs5_ndl_gptr = 110, //0x6E
285- iohs5_ndl_repr = 111, //0x6F
286- iohs5_ndl_time = 112, //0x70
287+ // hole_ring: 110, //0x6E
288+ // hole_ring: 111, //0x6F
289+ // hole_ring: 112, //0x70
290 iohs5_pdl_gptr = 113, //0x71
291 iohs5_pdl_repr = 114, //0x72
292 iohs5_pdl_time = 115, //0x73
293@@ -154,9 +154,9 @@ enum RingID
294 iohs6_gptr = 117, //0x75
295 iohs6_repr = 118, //0x76
296 iohs6_time = 119, //0x77
297- iohs6_ndl_gptr = 120, //0x78
298- iohs6_ndl_repr = 121, //0x79
299- iohs6_ndl_time = 122, //0x7A
300+ // hole_ring: 120, //0x78
301+ // hole_ring: 121, //0x79
302+ // hole_ring: 122, //0x7A
303 iohs6_pdl_gptr = 123, //0x7B
304 iohs6_pdl_repr = 124, //0x7C
305 iohs6_pdl_time = 125, //0x7D
306@@ -164,9 +164,9 @@ enum RingID
307 iohs7_gptr = 127, //0x7F
308 iohs7_repr = 128, //0x80
309 iohs7_time = 129, //0x81
310- iohs7_ndl_gptr = 130, //0x82
311- iohs7_ndl_repr = 131, //0x83
312- iohs7_ndl_time = 132, //0x84
313+ // hole_ring: 130, //0x82
314+ // hole_ring: 131, //0x83
315+ // hole_ring: 132, //0x84
316 iohs7_pdl_gptr = 133, //0x85
317 iohs7_pdl_repr = 134, //0x86
318 iohs7_pdl_time = 135, //0x87
319@@ -175,8 +175,8 @@ enum RingID
320 eq_repr = 138, //0x8A
321 eq_time = 139, //0x8B
322 eq_clkadj_gptr = 140, //0x8C
323- eq_clkadj_repr = 141, //0x8D
324- eq_clkadj_time = 142, //0x8E
325+ // hole_ring: 141, //0x8D
326+ // hole_ring: 142, //0x8E
327 ec_cl2_gptr = 143, //0x8F
328 ec_cl2_repr = 144, //0x90
329 ec_cl2_time = 145, //0x91
330@@ -184,7 +184,7 @@ enum RingID
331 ec2_cl2_repr = 147, //0x93
332 ec3_cl2_repr = 148, //0x94
333 ec_mma_gptr = 149, //0x95
334- ec_mma_repr = 150, //0x96
335+ // hole_ring: 150, //0x96
336 ec_mma_time = 151, //0x97
337 ec1_mma_repr = 152, //0x98
338 ec2_mma_repr = 153, //0x99
339@@ -205,21 +205,21 @@ enum RingID
340 NUM_RING_IDS_MVPD = 168,
341
342 // EKB Rings:
343- perv_fure = 256, //0x100
344- sbe_fure = 257, //0x101
345- occ_fure = 258, //0x102
346+ // hole_ring: 256, //0x100
347+ // hole_ring: 257, //0x101
348+ // hole_ring: 258, //0x102
349 perv_dpll_func = 259, //0x103
350- perv_dpll_bndy = 260, //0x104
351+ // hole_ring: 260, //0x104
352 perv_dpll_time = 261, //0x105
353 perv_pll_func = 262, //0x106
354 perv_pll_bndy = 263, //0x107
355- n0_fure = 264, //0x108
356- n1_fure = 265, //0x109
357- n1_nmmu1_fure = 266, //0x10A
358- pci_fure = 267, //0x10B
359+ // hole_ring: 264, //0x108
360+ // hole_ring: 265, //0x109
361+ // hole_ring: 266, //0x10A
362+ // hole_ring: 267, //0x10B
363 pci_pll_func = 268, //0x10C
364 pci_pll_bndy = 269, //0x10D
365- mc_fure = 270, //0x10E
366+ // hole_ring: 270, //0x10E
367 mc_pll_func = 271, //0x10F
368 mc_pll_bndy = 272, //0x110
369 mc_pll_bndy_bucket_0 = 273, //0x111
370@@ -227,19 +227,19 @@ enum RingID
371 mc_pll_bndy_bucket_2 = 275, //0x113
372 mc_pll_bndy_bucket_3 = 276, //0x114
373 mc_pll_bndy_bucket_4 = 277, //0x115
374- pau0_fure = 278, //0x116
375- pau0_pau0_fure = 279, //0x117
376- pau1_fure = 280, //0x118
377- pau1_pau3_fure = 281, //0x119
378- pau2_fure = 282, //0x11A
379- pau2_pau4_fure = 283, //0x11B
380- pau2_pau5_fure = 284, //0x11C
381- pau3_fure = 285, //0x11D
382- pau3_pau6_fure = 286, //0x11E
383- pau3_pau7_fure = 287, //0x11F
384- iohs0_fure = 288, //0x120
385- iohs0_ndl_fure = 289, //0x121
386- iohs0_pdl_fure = 290, //0x122
387+ // hole_ring: 278, //0x116
388+ // hole_ring: 279, //0x117
389+ // hole_ring: 280, //0x118
390+ // hole_ring: 281, //0x119
391+ // hole_ring: 282, //0x11A
392+ // hole_ring: 283, //0x11B
393+ // hole_ring: 284, //0x11C
394+ // hole_ring: 285, //0x11D
395+ // hole_ring: 286, //0x11E
396+ // hole_ring: 287, //0x11F
397+ // hole_ring: 288, //0x120
398+ // hole_ring: 289, //0x121
399+ // hole_ring: 290, //0x122
400 iohs0_pll_func = 291, //0x123
401 iohs0_pll_bndy = 292, //0x124
402 iohs0_pll_bndy_bucket_0 = 293, //0x125
403@@ -250,61 +250,119 @@ enum RingID
404 iohs0_pll_bndy_bucket_5 = 298, //0x12A
405 iohs0_pll_bndy_bucket_6 = 299, //0x12B
406 iohs0_pll_bndy_bucket_7 = 300, //0x12C
407- iohs1_fure = 301, //0x12D
408- iohs1_ndl_fure = 302, //0x12E
409- iohs1_pdl_fure = 303, //0x12F
410+ // hole_ring: 301, //0x12D
411+ // hole_ring: 302, //0x12E
412+ // hole_ring: 303, //0x12F
413 iohs1_pll_func = 304, //0x130
414- iohs2_fure = 305, //0x131
415- iohs2_ndl_fure = 306, //0x132
416- iohs2_pdl_fure = 307, //0x133
417+ // hole_ring: 305, //0x131
418+ // hole_ring: 306, //0x132
419+ // hole_ring: 307, //0x133
420 iohs2_pll_func = 308, //0x134
421- iohs3_fure = 309, //0x135
422- iohs3_ndl_fure = 310, //0x136
423- iohs3_pdl_fure = 311, //0x137
424+ // hole_ring: 309, //0x135
425+ // hole_ring: 310, //0x136
426+ // hole_ring: 311, //0x137
427 iohs3_pll_func = 312, //0x138
428- iohs4_fure = 313, //0x139
429- iohs4_ndl_fure = 314, //0x13A
430- iohs4_pdl_fure = 315, //0x13B
431+ // hole_ring: 313, //0x139
432+ // hole_ring: 314, //0x13A
433+ // hole_ring: 315, //0x13B
434 iohs4_pll_func = 316, //0x13C
435- iohs5_fure = 317, //0x13D
436- iohs5_ndl_fure = 318, //0x13E
437- iohs5_pdl_fure = 319, //0x13F
438+ // hole_ring: 317, //0x13D
439+ // hole_ring: 318, //0x13E
440+ // hole_ring: 319, //0x13F
441 iohs5_pll_func = 320, //0x140
442- iohs6_fure = 321, //0x141
443- iohs6_ndl_fure = 322, //0x142
444- iohs6_pdl_fure = 323, //0x143
445+ // hole_ring: 321, //0x141
446+ // hole_ring: 322, //0x142
447+ // hole_ring: 323, //0x143
448 iohs6_pll_func = 324, //0x144
449- iohs7_fure = 325, //0x145
450- iohs7_ndl_fure = 326, //0x146
451- iohs7_pdl_fure = 327, //0x147
452+ // hole_ring: 325, //0x145
453+ // hole_ring: 326, //0x146
454+ // hole_ring: 327, //0x147
455 iohs7_pll_func = 328, //0x148
456- eq_fure = 329, //0x149
457+ // hole_ring: 329, //0x149
458 eq_cmsk = 330, //0x14A
459- eq_inex = 331, //0x14B
460+ // hole_ring: 331, //0x14B
461 eq_mode = 332, //0x14C
462- eq_clkadj_fure = 333, //0x14D
463+ // hole_ring: 333, //0x14D
464 eq_clkadj_cmsk = 334, //0x14E
465- eq_clkadj_inex = 335, //0x14F
466- eq_clkadj_mode = 336, //0x150
467- ec_cl2_fure = 337, //0x151
468+ // hole_ring: 335, //0x14F
469+ // hole_ring: 336, //0x150
470+ // hole_ring: 337, //0x151
471 ec_cl2_cmsk = 338, //0x152
472 ec_cl2_inex = 339, //0x153
473 ec_cl2_mode = 340, //0x154
474- ec_mma_fure = 341, //0x155
475+ // hole_ring: 341, //0x155
476 ec_mma_cmsk = 342, //0x156
477- ec_mma_inex = 343, //0x157
478- ec_l3_fure = 344, //0x158
479+ // hole_ring: 343, //0x157
480+ // hole_ring: 344, //0x158
481 ec_l3_cmsk = 345, //0x159
482 ec_l3_inex = 346, //0x15A
483- ec_l3_mode = 347, //0x15B
484+ // hole_ring: 347, //0x15B
485 n0_abst = 348, //0x15C
486 n1_abst = 349, //0x15D
487 n1_nmmu1_abst = 350, //0x15E
488 ec_cl2_abst = 351, //0x15F
489 ec_mma_abst = 352, //0x160
490- NUM_RING_IDS_EKB = 97,
491+ perv_func = 353, //0x161
492+ sbe_func = 354, //0x162
493+ occ_func = 355, //0x163
494+ perv_pll_bndy_bucket_0 = 356, //0x164
495+ perv_pll_bndy_bucket_1 = 357, //0x165
496+ perv_pll_bndy_bucket_2 = 358, //0x166
497+ perv_pll_bndy_bucket_3 = 359, //0x167
498+ n0_func = 360, //0x168
499+ n1_func = 361, //0x169
500+ n1_nmmu1_func = 362, //0x16A
501+ pci_func = 363, //0x16B
502+ pci_pll_bndy_bucket_0 = 364, //0x16C
503+ pci_pll_bndy_bucket_1 = 365, //0x16D
504+ pci_pll_bndy_bucket_2 = 366, //0x16E
505+ pci_pll_bndy_bucket_3 = 367, //0x16F
506+ mc_func = 368, //0x170
507+ mc_pll_bndy_bucket_5 = 369, //0x171
508+ mc_pll_bndy_bucket_6 = 370, //0x172
509+ mc_pll_bndy_bucket_7 = 371, //0x173
510+ pau0_func = 372, //0x174
511+ pau0_pau0_func = 373, //0x175
512+ pau1_func = 374, //0x176
513+ pau1_pau3_func = 375, //0x177
514+ pau2_func = 376, //0x178
515+ pau2_pau4_func = 377, //0x179
516+ pau2_pau5_func = 378, //0x17A
517+ pau3_func = 379, //0x17B
518+ pau3_pau6_func = 380, //0x17C
519+ pau3_pau7_func = 381, //0x17D
520+ iohs0_func = 382, //0x17E
521+ iohs0_pdl_func = 383, //0x17F
522+ iohs0_pll_bndy_bucket_8 = 384, //0x180
523+ iohs0_pll_bndy_bucket_9 = 385, //0x181
524+ iohs0_pll_bndy_bucket_10 = 386, //0x182
525+ iohs0_pll_bndy_bucket_11 = 387, //0x183
526+ iohs0_pll_bndy_bucket_12 = 388, //0x184
527+ iohs0_pll_bndy_bucket_13 = 389, //0x185
528+ iohs0_pll_bndy_bucket_14 = 390, //0x186
529+ iohs0_pll_bndy_bucket_15 = 391, //0x187
530+ iohs1_func = 392, //0x188
531+ iohs1_pdl_func = 393, //0x189
532+ iohs2_func = 394, //0x18A
533+ iohs2_pdl_func = 395, //0x18B
534+ iohs3_func = 396, //0x18C
535+ iohs3_pdl_func = 397, //0x18D
536+ iohs4_func = 398, //0x18E
537+ iohs4_pdl_func = 399, //0x18F
538+ iohs5_func = 400, //0x190
539+ iohs5_pdl_func = 401, //0x191
540+ iohs6_func = 402, //0x192
541+ iohs6_pdl_func = 403, //0x193
542+ iohs7_func = 404, //0x194
543+ iohs7_pdl_func = 405, //0x195
544+ eq_func = 406, //0x196
545+ eq_clkadj_func = 407, //0x197
546+ ec_cl2_func = 408, //0x198
547+ ec_mma_func = 409, //0x199
548+ ec_l3_func = 410, //0x19A
549+ NUM_RING_IDS_EKB = 155,
550
551- NUM_RING_IDS = 265, // = NUM_RING_IDS_MVPD + NUM_RING_IDS_EKB
552+ NUM_RING_IDS = 323, // = NUM_RING_IDS_MVPD + NUM_RING_IDS_EKB
553 }; // enum RingID
554
555 #endif // _P10_RING_ID_H_
556diff --git a/src/import/chips/p10/utils/imageProcs/p10_ring_properties.H b/src/import/chips/p10/utils/imageProcs/p10_ring_properties.H
557index 4d2ea10..2c3e786 100644
558--- a/src/import/chips/p10/utils/imageProcs/p10_ring_properties.H
559+++ b/src/import/chips/p10/utils/imageProcs/p10_ring_properties.H
560@@ -25,14 +25,14 @@
561 #ifndef _P10_RING_PROPERTIES_H_
562 #define _P10_RING_PROPERTIES_H_
563
564-static const uint8_t RING_TABLE_VERSION_DOC = 22;
565+static const uint8_t RING_TABLE_VERSION_DOC = 23;
566 static const uint8_t RING_TABLE_VERSION_MVPD = 22;
567-static const uint8_t RING_TABLE_VERSION_EKB = 22;
568+static const uint8_t RING_TABLE_VERSION_EKB = 23;
569
570 #define RINGID_START_MVPD (RingId_t)0
571 #define RINGID_END_MVPD (RingId_t)167
572 #define RINGID_START_EKB (RingId_t)256
573-#define RINGID_END_EKB (RingId_t)352
574+#define RINGID_END_EKB (RingId_t)410
575
576 #define RING_INDEX_START_MVPD (RingId_t)0
577 #define RING_INDEX_START_EKB (RingId_t)168
578@@ -45,29 +45,29 @@ enum RingOffset
579 perv_occ_gptr = 0,
580 perv_occ_time = 1,
581 sbe_gptr = 2,
582- sbe_time = 3,
583- perv_dpll_gptr = 4,
584- perv_pll_gptr = 5,
585- perv_fure = 6,
586- sbe_fure = 7,
587- occ_fure = 8,
588- perv_dpll_func = 9,
589- perv_dpll_bndy = 10,
590- perv_dpll_time = 11,
591- perv_pll_func = 12,
592- perv_pll_bndy = 13,
593+ perv_dpll_gptr = 3,
594+ perv_pll_gptr = 4,
595+ perv_dpll_func = 5,
596+ perv_dpll_time = 6,
597+ perv_pll_func = 7,
598+ perv_func = 8,
599+ sbe_func = 9,
600+ occ_func = 10,
601+ perv_pll_bndy_bucket_0 = 11,
602+ perv_pll_bndy_bucket_1 = 12,
603+ perv_pll_bndy_bucket_2 = 13,
604+ perv_pll_bndy_bucket_3 = 14,
605 // Instance Rings
606 perv_occ_repr = (0 | INSTANCE_RING_MARK),
607 pib_repr = (1 | INSTANCE_RING_MARK),
608- sbe_repr = (2 | INSTANCE_RING_MARK),
609 };
610
611 static const ChipletData_t g_chipletData =
612 {
613 0x01, // Base chiplet/instance ID.
614 1, // Number of chiplet instances
615- 14, // 14 common rings for PERV Chiplet
616- 3, // 3 instance specific rings for PERV Chiplet
617+ 15, // 15 common rings for PERV Chiplet
618+ 2, // 2 instance specific rings for PERV Chiplet
619 };
620 }; // end of namespace PERV
621
622@@ -78,8 +78,8 @@ enum RingOffset
623 // Common Rings
624 n0_gptr = 0,
625 n0_time = 1,
626- n0_fure = 2,
627- n0_abst = 3,
628+ n0_abst = 2,
629+ n0_func = 3,
630 // Instance Rings
631 n0_repr = (0 | INSTANCE_RING_MARK),
632 n0_gptr_ovly = (1 | INSTANCE_RING_MARK),
633@@ -103,10 +103,10 @@ enum RingOffset
634 n1_time = 1,
635 n1_nmmu1_gptr = 2,
636 n1_nmmu1_time = 3,
637- n1_fure = 4,
638- n1_nmmu1_fure = 5,
639- n1_abst = 6,
640- n1_nmmu1_abst = 7,
641+ n1_abst = 4,
642+ n1_nmmu1_abst = 5,
643+ n1_func = 6,
644+ n1_nmmu1_func = 7,
645 // Instance Rings
646 n1_repr = (0 | INSTANCE_RING_MARK),
647 n1_nmmu1_repr = (1 | INSTANCE_RING_MARK),
648@@ -130,9 +130,12 @@ enum RingOffset
649 pci_gptr = 0,
650 pci_time = 1,
651 pci_pll_gptr = 2,
652- pci_fure = 3,
653- pci_pll_func = 4,
654- pci_pll_bndy = 5,
655+ pci_pll_func = 3,
656+ pci_func = 4,
657+ pci_pll_bndy_bucket_0 = 5,
658+ pci_pll_bndy_bucket_1 = 6,
659+ pci_pll_bndy_bucket_2 = 7,
660+ pci_pll_bndy_bucket_3 = 8,
661 // Instance Rings
662 pci_repr = (0 | INSTANCE_RING_MARK),
663 };
664@@ -141,7 +144,7 @@ static const ChipletData_t g_chipletData =
665 {
666 0x08, // Base chiplet/instance ID.
667 2, // Number of chiplet instances
668- 6, // 6 common rings for PCI Chiplet
669+ 9, // 9 common rings for PCI Chiplet
670 1, // 1 instance specific rings for PCI Chiplet
671 };
672 }; // end of namespace PCI
673@@ -154,14 +157,16 @@ enum RingOffset
674 mc_gptr = 0,
675 mc_time = 1,
676 mc_pll_gptr = 2,
677- mc_fure = 3,
678- mc_pll_func = 4,
679- mc_pll_bndy = 5,
680- mc_pll_bndy_bucket_0 = 5,
681- mc_pll_bndy_bucket_1 = 6,
682- mc_pll_bndy_bucket_2 = 7,
683- mc_pll_bndy_bucket_3 = 8,
684- mc_pll_bndy_bucket_4 = 9,
685+ mc_pll_func = 3,
686+ mc_pll_bndy_bucket_0 = 4,
687+ mc_pll_bndy_bucket_1 = 5,
688+ mc_pll_bndy_bucket_2 = 6,
689+ mc_pll_bndy_bucket_3 = 7,
690+ mc_pll_bndy_bucket_4 = 8,
691+ mc_func = 9,
692+ mc_pll_bndy_bucket_5 = 10,
693+ mc_pll_bndy_bucket_6 = 11,
694+ mc_pll_bndy_bucket_7 = 12,
695 // Instance Rings
696 mc_repr = (0 | INSTANCE_RING_MARK),
697 };
698@@ -170,7 +175,7 @@ static const ChipletData_t g_chipletData =
699 {
700 0x0C, // Base chiplet/instance ID.
701 4, // Number of chiplet instances
702- 10, // 10 common rings for MC Chiplet
703+ 13, // 13 common rings for MC Chiplet
704 1, // 1 instance specific rings for MC Chiplet
705 };
706 }; // end of namespace MC
707@@ -184,8 +189,8 @@ enum RingOffset
708 pau0_time = 1,
709 pau0_pau0_gptr = 2,
710 pau0_pau0_time = 3,
711- pau0_fure = 4,
712- pau0_pau0_fure = 5,
713+ pau0_func = 4,
714+ pau0_pau0_func = 5,
715 // Instance Rings
716 pau0_repr = (0 | INSTANCE_RING_MARK),
717 pau0_pau0_repr = (1 | INSTANCE_RING_MARK),
718@@ -210,8 +215,8 @@ enum RingOffset
719 pau1_time = 1,
720 pau1_pau3_gptr = 2,
721 pau1_pau3_time = 3,
722- pau1_fure = 4,
723- pau1_pau3_fure = 5,
724+ pau1_func = 4,
725+ pau1_pau3_func = 5,
726 // Instance Rings
727 pau1_repr = (0 | INSTANCE_RING_MARK),
728 pau1_pau3_repr = (1 | INSTANCE_RING_MARK),
729@@ -238,9 +243,9 @@ enum RingOffset
730 pau2_pau4_time = 3,
731 pau2_pau5_gptr = 4,
732 pau2_pau5_time = 5,
733- pau2_fure = 6,
734- pau2_pau4_fure = 7,
735- pau2_pau5_fure = 8,
736+ pau2_func = 6,
737+ pau2_pau4_func = 7,
738+ pau2_pau5_func = 8,
739 // Instance Rings
740 pau2_repr = (0 | INSTANCE_RING_MARK),
741 pau2_pau4_repr = (1 | INSTANCE_RING_MARK),
742@@ -268,9 +273,9 @@ enum RingOffset
743 pau3_pau6_time = 3,
744 pau3_pau7_gptr = 4,
745 pau3_pau7_time = 5,
746- pau3_fure = 6,
747- pau3_pau6_fure = 7,
748- pau3_pau7_fure = 8,
749+ pau3_func = 6,
750+ pau3_pau6_func = 7,
751+ pau3_pau7_func = 8,
752 // Instance Rings
753 pau3_repr = (0 | INSTANCE_RING_MARK),
754 pau3_pau6_repr = (1 | INSTANCE_RING_MARK),
755@@ -294,36 +299,39 @@ enum RingOffset
756 // Common Rings
757 iohs0_gptr = 0,
758 iohs0_time = 1,
759- iohs0_ndl_gptr = 2,
760- iohs0_ndl_time = 3,
761- iohs0_pdl_gptr = 4,
762- iohs0_pdl_time = 5,
763- iohs0_pll_gptr = 6,
764- iohs0_fure = 7,
765- iohs0_ndl_fure = 8,
766- iohs0_pdl_fure = 9,
767- iohs0_pll_func = 10,
768- iohs0_pll_bndy = 11,
769- iohs0_pll_bndy_bucket_0 = 11,
770- iohs0_pll_bndy_bucket_1 = 12,
771- iohs0_pll_bndy_bucket_2 = 13,
772- iohs0_pll_bndy_bucket_3 = 14,
773- iohs0_pll_bndy_bucket_4 = 15,
774- iohs0_pll_bndy_bucket_5 = 16,
775- iohs0_pll_bndy_bucket_6 = 17,
776- iohs0_pll_bndy_bucket_7 = 18,
777+ iohs0_pdl_gptr = 2,
778+ iohs0_pdl_time = 3,
779+ iohs0_pll_gptr = 4,
780+ iohs0_pll_func = 5,
781+ iohs0_pll_bndy_bucket_0 = 6,
782+ iohs0_pll_bndy_bucket_1 = 7,
783+ iohs0_pll_bndy_bucket_2 = 8,
784+ iohs0_pll_bndy_bucket_3 = 9,
785+ iohs0_pll_bndy_bucket_4 = 10,
786+ iohs0_pll_bndy_bucket_5 = 11,
787+ iohs0_pll_bndy_bucket_6 = 12,
788+ iohs0_pll_bndy_bucket_7 = 13,
789+ iohs0_func = 14,
790+ iohs0_pdl_func = 15,
791+ iohs0_pll_bndy_bucket_8 = 16,
792+ iohs0_pll_bndy_bucket_9 = 17,
793+ iohs0_pll_bndy_bucket_10 = 18,
794+ iohs0_pll_bndy_bucket_11 = 19,
795+ iohs0_pll_bndy_bucket_12 = 20,
796+ iohs0_pll_bndy_bucket_13 = 21,
797+ iohs0_pll_bndy_bucket_14 = 22,
798+ iohs0_pll_bndy_bucket_15 = 23,
799 // Instance Rings
800 iohs0_repr = (0 | INSTANCE_RING_MARK),
801- iohs0_ndl_repr = (1 | INSTANCE_RING_MARK),
802- iohs0_pdl_repr = (2 | INSTANCE_RING_MARK),
803+ iohs0_pdl_repr = (1 | INSTANCE_RING_MARK),
804 };
805
806 static const ChipletData_t g_chipletData =
807 {
808 0x18, // Base chiplet/instance ID.
809 1, // Number of chiplet instances
810- 19, // 19 common rings for AXON0 Chiplet
811- 3, // 3 instance specific rings for AXON0 Chiplet
812+ 24, // 24 common rings for AXON0 Chiplet
813+ 2, // 2 instance specific rings for AXON0 Chiplet
814 };
815 }; // end of namespace AXON0
816
817@@ -334,27 +342,23 @@ enum RingOffset
818 // Common Rings
819 iohs1_gptr = 0,
820 iohs1_time = 1,
821- iohs1_ndl_gptr = 2,
822- iohs1_ndl_time = 3,
823- iohs1_pdl_gptr = 4,
824- iohs1_pdl_time = 5,
825- iohs1_pll_gptr = 6,
826- iohs1_fure = 7,
827- iohs1_ndl_fure = 8,
828- iohs1_pdl_fure = 9,
829- iohs1_pll_func = 10,
830+ iohs1_pdl_gptr = 2,
831+ iohs1_pdl_time = 3,
832+ iohs1_pll_gptr = 4,
833+ iohs1_pll_func = 5,
834+ iohs1_func = 6,
835+ iohs1_pdl_func = 7,
836 // Instance Rings
837 iohs1_repr = (0 | INSTANCE_RING_MARK),
838- iohs1_ndl_repr = (1 | INSTANCE_RING_MARK),
839- iohs1_pdl_repr = (2 | INSTANCE_RING_MARK),
840+ iohs1_pdl_repr = (1 | INSTANCE_RING_MARK),
841 };
842
843 static const ChipletData_t g_chipletData =
844 {
845 0x19, // Base chiplet/instance ID.
846 1, // Number of chiplet instances
847- 11, // 11 common rings for AXON1 Chiplet
848- 3, // 3 instance specific rings for AXON1 Chiplet
849+ 8, // 8 common rings for AXON1 Chiplet
850+ 2, // 2 instance specific rings for AXON1 Chiplet
851 };
852 }; // end of namespace AXON1
853
854@@ -365,27 +369,23 @@ enum RingOffset
855 // Common Rings
856 iohs2_gptr = 0,
857 iohs2_time = 1,
858- iohs2_ndl_gptr = 2,
859- iohs2_ndl_time = 3,
860- iohs2_pdl_gptr = 4,
861- iohs2_pdl_time = 5,
862- iohs2_pll_gptr = 6,
863- iohs2_fure = 7,
864- iohs2_ndl_fure = 8,
865- iohs2_pdl_fure = 9,
866- iohs2_pll_func = 10,
867+ iohs2_pdl_gptr = 2,
868+ iohs2_pdl_time = 3,
869+ iohs2_pll_gptr = 4,
870+ iohs2_pll_func = 5,
871+ iohs2_func = 6,
872+ iohs2_pdl_func = 7,
873 // Instance Rings
874 iohs2_repr = (0 | INSTANCE_RING_MARK),
875- iohs2_ndl_repr = (1 | INSTANCE_RING_MARK),
876- iohs2_pdl_repr = (2 | INSTANCE_RING_MARK),
877+ iohs2_pdl_repr = (1 | INSTANCE_RING_MARK),
878 };
879
880 static const ChipletData_t g_chipletData =
881 {
882 0x1A, // Base chiplet/instance ID.
883 1, // Number of chiplet instances
884- 11, // 11 common rings for AXON2 Chiplet
885- 3, // 3 instance specific rings for AXON2 Chiplet
886+ 8, // 8 common rings for AXON2 Chiplet
887+ 2, // 2 instance specific rings for AXON2 Chiplet
888 };
889 }; // end of namespace AXON2
890
891@@ -396,27 +396,23 @@ enum RingOffset
892 // Common Rings
893 iohs3_gptr = 0,
894 iohs3_time = 1,
895- iohs3_ndl_gptr = 2,
896- iohs3_ndl_time = 3,
897- iohs3_pdl_gptr = 4,
898- iohs3_pdl_time = 5,
899- iohs3_pll_gptr = 6,
900- iohs3_fure = 7,
901- iohs3_ndl_fure = 8,
902- iohs3_pdl_fure = 9,
903- iohs3_pll_func = 10,
904+ iohs3_pdl_gptr = 2,
905+ iohs3_pdl_time = 3,
906+ iohs3_pll_gptr = 4,
907+ iohs3_pll_func = 5,
908+ iohs3_func = 6,
909+ iohs3_pdl_func = 7,
910 // Instance Rings
911 iohs3_repr = (0 | INSTANCE_RING_MARK),
912- iohs3_ndl_repr = (1 | INSTANCE_RING_MARK),
913- iohs3_pdl_repr = (2 | INSTANCE_RING_MARK),
914+ iohs3_pdl_repr = (1 | INSTANCE_RING_MARK),
915 };
916
917 static const ChipletData_t g_chipletData =
918 {
919 0x1B, // Base chiplet/instance ID.
920 1, // Number of chiplet instances
921- 11, // 11 common rings for AXON3 Chiplet
922- 3, // 3 instance specific rings for AXON3 Chiplet
923+ 8, // 8 common rings for AXON3 Chiplet
924+ 2, // 2 instance specific rings for AXON3 Chiplet
925 };
926 }; // end of namespace AXON3
927
928@@ -427,27 +423,23 @@ enum RingOffset
929 // Common Rings
930 iohs4_gptr = 0,
931 iohs4_time = 1,
932- iohs4_ndl_gptr = 2,
933- iohs4_ndl_time = 3,
934- iohs4_pdl_gptr = 4,
935- iohs4_pdl_time = 5,
936- iohs4_pll_gptr = 6,
937- iohs4_fure = 7,
938- iohs4_ndl_fure = 8,
939- iohs4_pdl_fure = 9,
940- iohs4_pll_func = 10,
941+ iohs4_pdl_gptr = 2,
942+ iohs4_pdl_time = 3,
943+ iohs4_pll_gptr = 4,
944+ iohs4_pll_func = 5,
945+ iohs4_func = 6,
946+ iohs4_pdl_func = 7,
947 // Instance Rings
948 iohs4_repr = (0 | INSTANCE_RING_MARK),
949- iohs4_ndl_repr = (1 | INSTANCE_RING_MARK),
950- iohs4_pdl_repr = (2 | INSTANCE_RING_MARK),
951+ iohs4_pdl_repr = (1 | INSTANCE_RING_MARK),
952 };
953
954 static const ChipletData_t g_chipletData =
955 {
956 0x1C, // Base chiplet/instance ID.
957 1, // Number of chiplet instances
958- 11, // 11 common rings for AXON4 Chiplet
959- 3, // 3 instance specific rings for AXON4 Chiplet
960+ 8, // 8 common rings for AXON4 Chiplet
961+ 2, // 2 instance specific rings for AXON4 Chiplet
962 };
963 }; // end of namespace AXON4
964
965@@ -458,27 +450,23 @@ enum RingOffset
966 // Common Rings
967 iohs5_gptr = 0,
968 iohs5_time = 1,
969- iohs5_ndl_gptr = 2,
970- iohs5_ndl_time = 3,
971- iohs5_pdl_gptr = 4,
972- iohs5_pdl_time = 5,
973- iohs5_pll_gptr = 6,
974- iohs5_fure = 7,
975- iohs5_ndl_fure = 8,
976- iohs5_pdl_fure = 9,
977- iohs5_pll_func = 10,
978+ iohs5_pdl_gptr = 2,
979+ iohs5_pdl_time = 3,
980+ iohs5_pll_gptr = 4,
981+ iohs5_pll_func = 5,
982+ iohs5_func = 6,
983+ iohs5_pdl_func = 7,
984 // Instance Rings
985 iohs5_repr = (0 | INSTANCE_RING_MARK),
986- iohs5_ndl_repr = (1 | INSTANCE_RING_MARK),
987- iohs5_pdl_repr = (2 | INSTANCE_RING_MARK),
988+ iohs5_pdl_repr = (1 | INSTANCE_RING_MARK),
989 };
990
991 static const ChipletData_t g_chipletData =
992 {
993 0x1D, // Base chiplet/instance ID.
994 1, // Number of chiplet instances
995- 11, // 11 common rings for AXON5 Chiplet
996- 3, // 3 instance specific rings for AXON5 Chiplet
997+ 8, // 8 common rings for AXON5 Chiplet
998+ 2, // 2 instance specific rings for AXON5 Chiplet
999 };
1000 }; // end of namespace AXON5
1001
1002@@ -489,27 +477,23 @@ enum RingOffset
1003 // Common Rings
1004 iohs6_gptr = 0,
1005 iohs6_time = 1,
1006- iohs6_ndl_gptr = 2,
1007- iohs6_ndl_time = 3,
1008- iohs6_pdl_gptr = 4,
1009- iohs6_pdl_time = 5,
1010- iohs6_pll_gptr = 6,
1011- iohs6_fure = 7,
1012- iohs6_ndl_fure = 8,
1013- iohs6_pdl_fure = 9,
1014- iohs6_pll_func = 10,
1015+ iohs6_pdl_gptr = 2,
1016+ iohs6_pdl_time = 3,
1017+ iohs6_pll_gptr = 4,
1018+ iohs6_pll_func = 5,
1019+ iohs6_func = 6,
1020+ iohs6_pdl_func = 7,
1021 // Instance Rings
1022 iohs6_repr = (0 | INSTANCE_RING_MARK),
1023- iohs6_ndl_repr = (1 | INSTANCE_RING_MARK),
1024- iohs6_pdl_repr = (2 | INSTANCE_RING_MARK),
1025+ iohs6_pdl_repr = (1 | INSTANCE_RING_MARK),
1026 };
1027
1028 static const ChipletData_t g_chipletData =
1029 {
1030 0x1E, // Base chiplet/instance ID.
1031 1, // Number of chiplet instances
1032- 11, // 11 common rings for AXON6 Chiplet
1033- 3, // 3 instance specific rings for AXON6 Chiplet
1034+ 8, // 8 common rings for AXON6 Chiplet
1035+ 2, // 2 instance specific rings for AXON6 Chiplet
1036 };
1037 }; // end of namespace AXON6
1038
1039@@ -520,27 +504,23 @@ enum RingOffset
1040 // Common Rings
1041 iohs7_gptr = 0,
1042 iohs7_time = 1,
1043- iohs7_ndl_gptr = 2,
1044- iohs7_ndl_time = 3,
1045- iohs7_pdl_gptr = 4,
1046- iohs7_pdl_time = 5,
1047- iohs7_pll_gptr = 6,
1048- iohs7_fure = 7,
1049- iohs7_ndl_fure = 8,
1050- iohs7_pdl_fure = 9,
1051- iohs7_pll_func = 10,
1052+ iohs7_pdl_gptr = 2,
1053+ iohs7_pdl_time = 3,
1054+ iohs7_pll_gptr = 4,
1055+ iohs7_pll_func = 5,
1056+ iohs7_func = 6,
1057+ iohs7_pdl_func = 7,
1058 // Instance Rings
1059 iohs7_repr = (0 | INSTANCE_RING_MARK),
1060- iohs7_ndl_repr = (1 | INSTANCE_RING_MARK),
1061- iohs7_pdl_repr = (2 | INSTANCE_RING_MARK),
1062+ iohs7_pdl_repr = (1 | INSTANCE_RING_MARK),
1063 };
1064
1065 static const ChipletData_t g_chipletData =
1066 {
1067 0x1F, // Base chiplet/instance ID.
1068 1, // Number of chiplet instances
1069- 11, // 11 common rings for AXON7 Chiplet
1070- 3, // 3 instance specific rings for AXON7 Chiplet
1071+ 8, // 8 common rings for AXON7 Chiplet
1072+ 2, // 2 instance specific rings for AXON7 Chiplet
1073 };
1074 }; // end of namespace AXON7
1075
1076@@ -552,58 +532,50 @@ enum RingOffset
1077 eq_gptr = 0,
1078 eq_time = 1,
1079 eq_clkadj_gptr = 2,
1080- eq_clkadj_time = 3,
1081- ec_cl2_gptr = 4,
1082- ec_cl2_time = 5,
1083- ec_mma_gptr = 6,
1084- ec_mma_time = 7,
1085- ec_l3_gptr = 8,
1086- ec_l3_time = 9,
1087- eq_fure = 10,
1088- eq_cmsk = 11,
1089- eq_inex = 12,
1090- eq_mode = 13,
1091- eq_clkadj_fure = 14,
1092- eq_clkadj_cmsk = 15,
1093- eq_clkadj_inex = 16,
1094- eq_clkadj_mode = 17,
1095- ec_cl2_fure = 18,
1096- ec_cl2_cmsk = 19,
1097- ec_cl2_inex = 20,
1098- ec_cl2_mode = 21,
1099- ec_mma_fure = 22,
1100- ec_mma_cmsk = 23,
1101- ec_mma_inex = 24,
1102- ec_l3_fure = 25,
1103- ec_l3_cmsk = 26,
1104- ec_l3_inex = 27,
1105- ec_l3_mode = 28,
1106- ec_cl2_abst = 29,
1107- ec_mma_abst = 30,
1108+ ec_cl2_gptr = 3,
1109+ ec_cl2_time = 4,
1110+ ec_mma_gptr = 5,
1111+ ec_mma_time = 6,
1112+ ec_l3_gptr = 7,
1113+ ec_l3_time = 8,
1114+ eq_cmsk = 9,
1115+ eq_mode = 10,
1116+ eq_clkadj_cmsk = 11,
1117+ ec_cl2_cmsk = 12,
1118+ ec_cl2_inex = 13,
1119+ ec_cl2_mode = 14,
1120+ ec_mma_cmsk = 15,
1121+ ec_l3_cmsk = 16,
1122+ ec_l3_inex = 17,
1123+ ec_cl2_abst = 18,
1124+ ec_mma_abst = 19,
1125+ eq_func = 20,
1126+ eq_clkadj_func = 21,
1127+ ec_cl2_func = 22,
1128+ ec_mma_func = 23,
1129+ ec_l3_func = 24,
1130 // Instance Rings
1131 eq_repr = (0 | INSTANCE_RING_MARK),
1132- eq_clkadj_repr = (1 | INSTANCE_RING_MARK),
1133- ec_cl2_repr = (2 | INSTANCE_RING_MARK),
1134- ec1_cl2_repr = (3 | INSTANCE_RING_MARK),
1135- ec2_cl2_repr = (4 | INSTANCE_RING_MARK),
1136- ec3_cl2_repr = (5 | INSTANCE_RING_MARK),
1137- ec_mma_repr = (6 | INSTANCE_RING_MARK),
1138- ec1_mma_repr = (7 | INSTANCE_RING_MARK),
1139- ec2_mma_repr = (8 | INSTANCE_RING_MARK),
1140- ec3_mma_repr = (9 | INSTANCE_RING_MARK),
1141- ec_l3_repr = (10 | INSTANCE_RING_MARK),
1142- ec1_l3_repr = (11 | INSTANCE_RING_MARK),
1143- ec2_l3_repr = (12 | INSTANCE_RING_MARK),
1144- ec3_l3_repr = (13 | INSTANCE_RING_MARK),
1145- eq_gptr_ovly = (14 | INSTANCE_RING_MARK),
1146+ ec_cl2_repr = (1 | INSTANCE_RING_MARK),
1147+ ec1_cl2_repr = (2 | INSTANCE_RING_MARK),
1148+ ec2_cl2_repr = (3 | INSTANCE_RING_MARK),
1149+ ec3_cl2_repr = (4 | INSTANCE_RING_MARK),
1150+ ec1_mma_repr = (5 | INSTANCE_RING_MARK),
1151+ ec2_mma_repr = (6 | INSTANCE_RING_MARK),
1152+ ec3_mma_repr = (7 | INSTANCE_RING_MARK),
1153+ ec_l3_repr = (8 | INSTANCE_RING_MARK),
1154+ ec1_l3_repr = (9 | INSTANCE_RING_MARK),
1155+ ec2_l3_repr = (10 | INSTANCE_RING_MARK),
1156+ ec3_l3_repr = (11 | INSTANCE_RING_MARK),
1157+ eq_gptr_ovly = (12 | INSTANCE_RING_MARK),
1158 };
1159
1160 static const ChipletData_t g_chipletData =
1161 {
1162 0x20, // Base chiplet/instance ID.
1163 8, // Number of chiplet instances
1164- 31, // 31 common rings for EQ Chiplet
1165- 15, // 15 instance specific rings for EQ Chiplet
1166+ 25, // 25 common rings for EQ Chiplet
1167+ 13, // 13 instance specific rings for EQ Chiplet
1168 };
1169 }; // end of namespace EQ
1170
1171@@ -617,8 +589,8 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1172 {perv_occ_time , "perv_occ_time" , 0x01034907, PERV::perv_occ_time , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 2
1173 {pib_repr , "pib_repr" , 0x01031006, PERV::pib_repr , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 3
1174 {sbe_gptr , "sbe_gptr" , 0x01032002, PERV::sbe_gptr , PERV_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 4
1175- {sbe_repr , "sbe_repr" , 0x01032006, PERV::sbe_repr , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 5
1176- {sbe_time , "sbe_time" , 0x01032007, PERV::sbe_time , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 6
1177+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 5
1178+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 6
1179 {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 7
1180 {perv_dpll_gptr , "perv_dpll_gptr" , 0x01030062, PERV::perv_dpll_gptr , PERV_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 8
1181 {perv_pll_gptr , "perv_pll_gptr" , 0x01030012, PERV::perv_pll_gptr , PERV_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 9
1182@@ -672,9 +644,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1183 {iohs0_gptr , "iohs0_gptr" , 0x18036002, AXON0::iohs0_gptr , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 57
1184 {iohs0_repr , "iohs0_repr" , 0x18036006, AXON0::iohs0_repr , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 58
1185 {iohs0_time , "iohs0_time" , 0x18036007, AXON0::iohs0_time , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 59
1186- {iohs0_ndl_gptr , "iohs0_ndl_gptr" , 0x18030402, AXON0::iohs0_ndl_gptr , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 60
1187- {iohs0_ndl_repr , "iohs0_ndl_repr" , 0x18030406, AXON0::iohs0_ndl_repr , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 61
1188- {iohs0_ndl_time , "iohs0_ndl_time" , 0x18030407, AXON0::iohs0_ndl_time , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 62
1189+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 60
1190+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 61
1191+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 62
1192 {iohs0_pdl_gptr , "iohs0_pdl_gptr" , 0x18030202, AXON0::iohs0_pdl_gptr , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 63
1193 {iohs0_pdl_repr , "iohs0_pdl_repr" , 0x18030206, AXON0::iohs0_pdl_repr , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 64
1194 {iohs0_pdl_time , "iohs0_pdl_time" , 0x18030207, AXON0::iohs0_pdl_time , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 65
1195@@ -682,9 +654,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1196 {iohs1_gptr , "iohs1_gptr" , 0x19036002, AXON1::iohs1_gptr , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 67
1197 {iohs1_repr , "iohs1_repr" , 0x19036006, AXON1::iohs1_repr , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 68
1198 {iohs1_time , "iohs1_time" , 0x19036007, AXON1::iohs1_time , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 69
1199- {iohs1_ndl_gptr , "iohs1_ndl_gptr" , 0x19030402, AXON1::iohs1_ndl_gptr , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 70
1200- {iohs1_ndl_repr , "iohs1_ndl_repr" , 0x19030406, AXON1::iohs1_ndl_repr , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 71
1201- {iohs1_ndl_time , "iohs1_ndl_time" , 0x19030407, AXON1::iohs1_ndl_time , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 72
1202+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 70
1203+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 71
1204+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 72
1205 {iohs1_pdl_gptr , "iohs1_pdl_gptr" , 0x19030202, AXON1::iohs1_pdl_gptr , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 73
1206 {iohs1_pdl_repr , "iohs1_pdl_repr" , 0x19030206, AXON1::iohs1_pdl_repr , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 74
1207 {iohs1_pdl_time , "iohs1_pdl_time" , 0x19030207, AXON1::iohs1_pdl_time , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 75
1208@@ -692,9 +664,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1209 {iohs2_gptr , "iohs2_gptr" , 0x1A036002, AXON2::iohs2_gptr , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 77
1210 {iohs2_repr , "iohs2_repr" , 0x1A036006, AXON2::iohs2_repr , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 78
1211 {iohs2_time , "iohs2_time" , 0x1A036007, AXON2::iohs2_time , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 79
1212- {iohs2_ndl_gptr , "iohs2_ndl_gptr" , 0x1A030402, AXON2::iohs2_ndl_gptr , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 80
1213- {iohs2_ndl_repr , "iohs2_ndl_repr" , 0x1A030406, AXON2::iohs2_ndl_repr , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 81
1214- {iohs2_ndl_time , "iohs2_ndl_time" , 0x1A030407, AXON2::iohs2_ndl_time , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 82
1215+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 80
1216+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 81
1217+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 82
1218 {iohs2_pdl_gptr , "iohs2_pdl_gptr" , 0x1A030202, AXON2::iohs2_pdl_gptr , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 83
1219 {iohs2_pdl_repr , "iohs2_pdl_repr" , 0x1A030206, AXON2::iohs2_pdl_repr , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 84
1220 {iohs2_pdl_time , "iohs2_pdl_time" , 0x1A030207, AXON2::iohs2_pdl_time , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 85
1221@@ -702,9 +674,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1222 {iohs3_gptr , "iohs3_gptr" , 0x1B036002, AXON3::iohs3_gptr , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 87
1223 {iohs3_repr , "iohs3_repr" , 0x1B036006, AXON3::iohs3_repr , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 88
1224 {iohs3_time , "iohs3_time" , 0x1B036007, AXON3::iohs3_time , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 89
1225- {iohs3_ndl_gptr , "iohs3_ndl_gptr" , 0x1B030402, AXON3::iohs3_ndl_gptr , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 90
1226- {iohs3_ndl_repr , "iohs3_ndl_repr" , 0x1B030406, AXON3::iohs3_ndl_repr , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 91
1227- {iohs3_ndl_time , "iohs3_ndl_time" , 0x1B030407, AXON3::iohs3_ndl_time , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 92
1228+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 90
1229+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 91
1230+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 92
1231 {iohs3_pdl_gptr , "iohs3_pdl_gptr" , 0x1B030202, AXON3::iohs3_pdl_gptr , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 93
1232 {iohs3_pdl_repr , "iohs3_pdl_repr" , 0x1B030206, AXON3::iohs3_pdl_repr , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 94
1233 {iohs3_pdl_time , "iohs3_pdl_time" , 0x1B030207, AXON3::iohs3_pdl_time , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 95
1234@@ -712,9 +684,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1235 {iohs4_gptr , "iohs4_gptr" , 0x1C036002, AXON4::iohs4_gptr , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 97
1236 {iohs4_repr , "iohs4_repr" , 0x1C036006, AXON4::iohs4_repr , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 98
1237 {iohs4_time , "iohs4_time" , 0x1C036007, AXON4::iohs4_time , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 99
1238- {iohs4_ndl_gptr , "iohs4_ndl_gptr" , 0x1C030402, AXON4::iohs4_ndl_gptr , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 100
1239- {iohs4_ndl_repr , "iohs4_ndl_repr" , 0x1C030406, AXON4::iohs4_ndl_repr , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 101
1240- {iohs4_ndl_time , "iohs4_ndl_time" , 0x1C030407, AXON4::iohs4_ndl_time , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 102
1241+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 100
1242+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 101
1243+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 102
1244 {iohs4_pdl_gptr , "iohs4_pdl_gptr" , 0x1C030202, AXON4::iohs4_pdl_gptr , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 103
1245 {iohs4_pdl_repr , "iohs4_pdl_repr" , 0x1C030206, AXON4::iohs4_pdl_repr , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 104
1246 {iohs4_pdl_time , "iohs4_pdl_time" , 0x1C030207, AXON4::iohs4_pdl_time , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 105
1247@@ -722,9 +694,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1248 {iohs5_gptr , "iohs5_gptr" , 0x1D036002, AXON5::iohs5_gptr , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 107
1249 {iohs5_repr , "iohs5_repr" , 0x1D036006, AXON5::iohs5_repr , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 108
1250 {iohs5_time , "iohs5_time" , 0x1D036007, AXON5::iohs5_time , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 109
1251- {iohs5_ndl_gptr , "iohs5_ndl_gptr" , 0x1D030402, AXON5::iohs5_ndl_gptr , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 110
1252- {iohs5_ndl_repr , "iohs5_ndl_repr" , 0x1D030406, AXON5::iohs5_ndl_repr , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 111
1253- {iohs5_ndl_time , "iohs5_ndl_time" , 0x1D030407, AXON5::iohs5_ndl_time , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 112
1254+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 110
1255+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 111
1256+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 112
1257 {iohs5_pdl_gptr , "iohs5_pdl_gptr" , 0x1D030202, AXON5::iohs5_pdl_gptr , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 113
1258 {iohs5_pdl_repr , "iohs5_pdl_repr" , 0x1D030206, AXON5::iohs5_pdl_repr , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 114
1259 {iohs5_pdl_time , "iohs5_pdl_time" , 0x1D030207, AXON5::iohs5_pdl_time , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 115
1260@@ -732,9 +704,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1261 {iohs6_gptr , "iohs6_gptr" , 0x1E036002, AXON6::iohs6_gptr , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 117
1262 {iohs6_repr , "iohs6_repr" , 0x1E036006, AXON6::iohs6_repr , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 118
1263 {iohs6_time , "iohs6_time" , 0x1E036007, AXON6::iohs6_time , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 119
1264- {iohs6_ndl_gptr , "iohs6_ndl_gptr" , 0x1E030402, AXON6::iohs6_ndl_gptr , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 120
1265- {iohs6_ndl_repr , "iohs6_ndl_repr" , 0x1E030406, AXON6::iohs6_ndl_repr , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 121
1266- {iohs6_ndl_time , "iohs6_ndl_time" , 0x1E030407, AXON6::iohs6_ndl_time , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 122
1267+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 120
1268+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 121
1269+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 122
1270 {iohs6_pdl_gptr , "iohs6_pdl_gptr" , 0x1E030202, AXON6::iohs6_pdl_gptr , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 123
1271 {iohs6_pdl_repr , "iohs6_pdl_repr" , 0x1E030206, AXON6::iohs6_pdl_repr , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 124
1272 {iohs6_pdl_time , "iohs6_pdl_time" , 0x1E030207, AXON6::iohs6_pdl_time , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 125
1273@@ -742,9 +714,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1274 {iohs7_gptr , "iohs7_gptr" , 0x1F036002, AXON7::iohs7_gptr , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 127
1275 {iohs7_repr , "iohs7_repr" , 0x1F036006, AXON7::iohs7_repr , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 128
1276 {iohs7_time , "iohs7_time" , 0x1F036007, AXON7::iohs7_time , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 129
1277- {iohs7_ndl_gptr , "iohs7_ndl_gptr" , 0x1F030402, AXON7::iohs7_ndl_gptr , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 130
1278- {iohs7_ndl_repr , "iohs7_ndl_repr" , 0x1F030406, AXON7::iohs7_ndl_repr , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 131
1279- {iohs7_ndl_time , "iohs7_ndl_time" , 0x1F030407, AXON7::iohs7_ndl_time , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 132
1280+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 130
1281+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 131
1282+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 132
1283 {iohs7_pdl_gptr , "iohs7_pdl_gptr" , 0x1F030202, AXON7::iohs7_pdl_gptr , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 133
1284 {iohs7_pdl_repr , "iohs7_pdl_repr" , 0x1F030206, AXON7::iohs7_pdl_repr , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 134
1285 {iohs7_pdl_time , "iohs7_pdl_time" , 0x1F030207, AXON7::iohs7_pdl_time , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 135
1286@@ -753,8 +725,8 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1287 {eq_repr , "eq_repr" , 0x20034026, EQ::eq_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_EQ }, // 138
1288 {eq_time , "eq_time" , 0x20034027, EQ::eq_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 139
1289 {eq_clkadj_gptr , "eq_clkadj_gptr" , 0x20030012, EQ::eq_clkadj_gptr , EQ_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 140
1290- {eq_clkadj_repr , "eq_clkadj_repr" , 0x20030016, EQ::eq_clkadj_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_EQ }, // 141
1291- {eq_clkadj_time , "eq_clkadj_time" , 0x20030017, EQ::eq_clkadj_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 142
1292+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 141
1293+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 142
1294 {ec_cl2_gptr , "ec_cl2_gptr" , 0x20032002, EQ::ec_cl2_gptr , EQ_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY | RMRK_SCAN_BY_QME}, // 143
1295 {ec_cl2_repr , "ec_cl2_repr" , 0x20032006, EQ::ec_cl2_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 144
1296 {ec_cl2_time , "ec_cl2_time" , 0x20032007, EQ::ec_cl2_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME | RMRK_SCAN_BY_QME }, // 145
1297@@ -762,7 +734,7 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1298 {ec2_cl2_repr , "ec2_cl2_repr" , 0x20030806, EQ::ec2_cl2_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 147
1299 {ec3_cl2_repr , "ec3_cl2_repr" , 0x20030406, EQ::ec3_cl2_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 148
1300 {ec_mma_gptr , "ec_mma_gptr" , 0x20830002, EQ::ec_mma_gptr , EQ_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY | RMRK_SCAN_BY_QME}, // 149
1301- {ec_mma_repr , "ec_mma_repr" , 0x20830006, EQ::ec_mma_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 150
1302+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 150
1303 {ec_mma_time , "ec_mma_time" , 0x20830007, EQ::ec_mma_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME | RMRK_SCAN_BY_QME }, // 151
1304 {ec1_mma_repr , "ec1_mma_repr" , 0x20430006, EQ::ec1_mma_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 152
1305 {ec2_mma_repr , "ec2_mma_repr" , 0x20230006, EQ::ec2_mma_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 153
1306@@ -782,43 +754,43 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1307 {eq_gptr_ovly , "eq_gptr_ovly" , 0x20034022, EQ::eq_gptr_ovly , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDS_EQ }, // 167
1308
1309 // EKB Rings:
1310- {perv_fure , "perv_fure" , 0x0103410F, PERV::perv_fure , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 256
1311- {sbe_fure , "sbe_fure" , 0x0103200F, PERV::sbe_fure , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 257
1312- {occ_fure , "occ_fure" , 0x0103080F, PERV::occ_fure , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 258
1313+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 256
1314+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 257
1315+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 258
1316 {perv_dpll_func , "perv_dpll_func" , 0x01030060, PERV::perv_dpll_func , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 259
1317- {perv_dpll_bndy , "perv_dpll_bndy" , 0x01030068, PERV::perv_dpll_bndy , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 260
1318+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 260
1319 {perv_dpll_time , "perv_dpll_time" , 0x01030067, PERV::perv_dpll_time , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 261
1320 {perv_pll_func , "perv_pll_func" , 0x01030010, PERV::perv_pll_func , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 262
1321- {perv_pll_bndy , "perv_pll_bndy" , 0x01030018, PERV::perv_pll_bndy , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 263
1322- {n0_fure , "n0_fure" , 0x0203640F, N0::n0_fure , N0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 264
1323- {n1_fure , "n1_fure" , 0x0303540F, N1::n1_fure , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 265
1324- {n1_nmmu1_fure , "n1_nmmu1_fure" , 0x0303020F, N1::n1_nmmu1_fure , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 266
1325- {pci_fure , "pci_fure" , 0x08037F8F, PCI::pci_fure , PCI_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 267
1326+ {perv_pll_bndy , "perv_pll_bndy" , 0x01030018, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE , RMRK_ROOT | RMRK_HAS_DERIVS | RCLS_EKB_RINGS }, // 263
1327+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 264
1328+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 265
1329+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 266
1330+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 267
1331 {pci_pll_func , "pci_pll_func" , 0x08030010, PCI::pci_pll_func , PCI_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 268
1332- {pci_pll_bndy , "pci_pll_bndy" , 0x08030018, PCI::pci_pll_bndy , PCI_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 269
1333- {mc_fure , "mc_fure" , 0x0C036F0F, MC::mc_fure , MC_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 270
1334+ {pci_pll_bndy , "pci_pll_bndy" , 0x08030018, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE , RMRK_ROOT | RMRK_HAS_DERIVS | RCLS_EKB_RINGS }, // 269
1335+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 270
1336 {mc_pll_func , "mc_pll_func" , 0x0C030010, MC::mc_pll_func , MC_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 271
1337- {mc_pll_bndy , "mc_pll_bndy" , 0x0C030018, MC::mc_pll_bndy , MC_TYPE , RMRK_ROOT | RMRK_HAS_DERIVS | RCLS_EKB_RINGS }, // 272
1338+ {mc_pll_bndy , "mc_pll_bndy" , 0x0C030018, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE , RMRK_ROOT | RMRK_HAS_DERIVS | RCLS_EKB_RINGS }, // 272
1339 {mc_pll_bndy_bucket_0 , "mc_pll_bndy_bucket_0" , 0x0C030018, MC::mc_pll_bndy_bucket_0 , MC_TYPE , RCLS_EKB_RINGS }, // 273
1340 {mc_pll_bndy_bucket_1 , "mc_pll_bndy_bucket_1" , 0x0C030018, MC::mc_pll_bndy_bucket_1 , MC_TYPE , RCLS_EKB_RINGS }, // 274
1341 {mc_pll_bndy_bucket_2 , "mc_pll_bndy_bucket_2" , 0x0C030018, MC::mc_pll_bndy_bucket_2 , MC_TYPE , RCLS_EKB_RINGS }, // 275
1342 {mc_pll_bndy_bucket_3 , "mc_pll_bndy_bucket_3" , 0x0C030018, MC::mc_pll_bndy_bucket_3 , MC_TYPE , RCLS_EKB_RINGS }, // 276
1343 {mc_pll_bndy_bucket_4 , "mc_pll_bndy_bucket_4" , 0x0C030018, MC::mc_pll_bndy_bucket_4 , MC_TYPE , RCLS_EKB_RINGS }, // 277
1344- {pau0_fure , "pau0_fure" , 0x1003430F, PAU0::pau0_fure , PAU0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 278
1345- {pau0_pau0_fure , "pau0_pau0_fure" , 0x1003200F, PAU0::pau0_pau0_fure , PAU0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 279
1346- {pau1_fure , "pau1_fure" , 0x1103430F, PAU1::pau1_fure , PAU1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 280
1347- {pau1_pau3_fure , "pau1_pau3_fure" , 0x1103200F, PAU1::pau1_pau3_fure , PAU1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 281
1348- {pau2_fure , "pau2_fure" , 0x1203430F, PAU2::pau2_fure , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 282
1349- {pau2_pau4_fure , "pau2_pau4_fure" , 0x1203200F, PAU2::pau2_pau4_fure , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 283
1350- {pau2_pau5_fure , "pau2_pau5_fure" , 0x1203100F, PAU2::pau2_pau5_fure , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 284
1351- {pau3_fure , "pau3_fure" , 0x1303430F, PAU3::pau3_fure , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 285
1352- {pau3_pau6_fure , "pau3_pau6_fure" , 0x1303200F, PAU3::pau3_pau6_fure , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 286
1353- {pau3_pau7_fure , "pau3_pau7_fure" , 0x1303100F, PAU3::pau3_pau7_fure , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 287
1354- {iohs0_fure , "iohs0_fure" , 0x1803600F, AXON0::iohs0_fure , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 288
1355- {iohs0_ndl_fure , "iohs0_ndl_fure" , 0x1803040F, AXON0::iohs0_ndl_fure , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 289
1356- {iohs0_pdl_fure , "iohs0_pdl_fure" , 0x1803020F, AXON0::iohs0_pdl_fure , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 290
1357+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 278
1358+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 279
1359+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 280
1360+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 281
1361+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 282
1362+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 283
1363+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 284
1364+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 285
1365+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 286
1366+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 287
1367+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 288
1368+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 289
1369+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 290
1370 {iohs0_pll_func , "iohs0_pll_func" , 0x18030010, AXON0::iohs0_pll_func , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 291
1371- {iohs0_pll_bndy , "iohs0_pll_bndy" , 0x18030018, AXON0::iohs0_pll_bndy , AXON0_TYPE, RMRK_ROOT | RMRK_HAS_DERIVS | RCLS_EKB_RINGS }, // 292
1372+ {iohs0_pll_bndy , "iohs0_pll_bndy" , 0x18030018, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE , RMRK_ROOT | RMRK_HAS_DERIVS | RCLS_EKB_RINGS }, // 292
1373 {iohs0_pll_bndy_bucket_0 , "iohs0_pll_bndy_bucket_0" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_0, AXON0_TYPE, RCLS_EKB_RINGS }, // 293
1374 {iohs0_pll_bndy_bucket_1 , "iohs0_pll_bndy_bucket_1" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_1, AXON0_TYPE, RCLS_EKB_RINGS }, // 294
1375 {iohs0_pll_bndy_bucket_2 , "iohs0_pll_bndy_bucket_2" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_2, AXON0_TYPE, RCLS_EKB_RINGS }, // 295
1376@@ -827,58 +799,116 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1377 {iohs0_pll_bndy_bucket_5 , "iohs0_pll_bndy_bucket_5" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_5, AXON0_TYPE, RCLS_EKB_RINGS }, // 298
1378 {iohs0_pll_bndy_bucket_6 , "iohs0_pll_bndy_bucket_6" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_6, AXON0_TYPE, RCLS_EKB_RINGS }, // 299
1379 {iohs0_pll_bndy_bucket_7 , "iohs0_pll_bndy_bucket_7" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_7, AXON0_TYPE, RCLS_EKB_RINGS }, // 300
1380- {iohs1_fure , "iohs1_fure" , 0x1903600F, AXON1::iohs1_fure , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 301
1381- {iohs1_ndl_fure , "iohs1_ndl_fure" , 0x1903040F, AXON1::iohs1_ndl_fure , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 302
1382- {iohs1_pdl_fure , "iohs1_pdl_fure" , 0x1903020F, AXON1::iohs1_pdl_fure , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 303
1383+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 301
1384+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 302
1385+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 303
1386 {iohs1_pll_func , "iohs1_pll_func" , 0x19030010, AXON1::iohs1_pll_func , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 304
1387- {iohs2_fure , "iohs2_fure" , 0x1A03600F, AXON2::iohs2_fure , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 305
1388- {iohs2_ndl_fure , "iohs2_ndl_fure" , 0x1A03040F, AXON2::iohs2_ndl_fure , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 306
1389- {iohs2_pdl_fure , "iohs2_pdl_fure" , 0x1A03020F, AXON2::iohs2_pdl_fure , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 307
1390+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 305
1391+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 306
1392+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 307
1393 {iohs2_pll_func , "iohs2_pll_func" , 0x1A030010, AXON2::iohs2_pll_func , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 308
1394- {iohs3_fure , "iohs3_fure" , 0x1B03600F, AXON3::iohs3_fure , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 309
1395- {iohs3_ndl_fure , "iohs3_ndl_fure" , 0x1B03040F, AXON3::iohs3_ndl_fure , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 310
1396- {iohs3_pdl_fure , "iohs3_pdl_fure" , 0x1B03020F, AXON3::iohs3_pdl_fure , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 311
1397+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 309
1398+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 310
1399+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 311
1400 {iohs3_pll_func , "iohs3_pll_func" , 0x1B030010, AXON3::iohs3_pll_func , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 312
1401- {iohs4_fure , "iohs4_fure" , 0x1C03600F, AXON4::iohs4_fure , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 313
1402- {iohs4_ndl_fure , "iohs4_ndl_fure" , 0x1C03040F, AXON4::iohs4_ndl_fure , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 314
1403- {iohs4_pdl_fure , "iohs4_pdl_fure" , 0x1C03020F, AXON4::iohs4_pdl_fure , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 315
1404+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 313
1405+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 314
1406+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 315
1407 {iohs4_pll_func , "iohs4_pll_func" , 0x1C030010, AXON4::iohs4_pll_func , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 316
1408- {iohs5_fure , "iohs5_fure" , 0x1D03600F, AXON5::iohs5_fure , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 317
1409- {iohs5_ndl_fure , "iohs5_ndl_fure" , 0x1D03040F, AXON5::iohs5_ndl_fure , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 318
1410- {iohs5_pdl_fure , "iohs5_pdl_fure" , 0x1D03020F, AXON5::iohs5_pdl_fure , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 319
1411+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 317
1412+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 318
1413+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 319
1414 {iohs5_pll_func , "iohs5_pll_func" , 0x1D030010, AXON5::iohs5_pll_func , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 320
1415- {iohs6_fure , "iohs6_fure" , 0x1E03600F, AXON6::iohs6_fure , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 321
1416- {iohs6_ndl_fure , "iohs6_ndl_fure" , 0x1E03040F, AXON6::iohs6_ndl_fure , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 322
1417- {iohs6_pdl_fure , "iohs6_pdl_fure" , 0x1E03020F, AXON6::iohs6_pdl_fure , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 323
1418+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 321
1419+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 322
1420+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 323
1421 {iohs6_pll_func , "iohs6_pll_func" , 0x1E030010, AXON6::iohs6_pll_func , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 324
1422- {iohs7_fure , "iohs7_fure" , 0x1F03600F, AXON7::iohs7_fure , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 325
1423- {iohs7_ndl_fure , "iohs7_ndl_fure" , 0x1F03040F, AXON7::iohs7_ndl_fure , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 326
1424- {iohs7_pdl_fure , "iohs7_pdl_fure" , 0x1F03020F, AXON7::iohs7_pdl_fure , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 327
1425+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 325
1426+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 326
1427+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 327
1428 {iohs7_pll_func , "iohs7_pll_func" , 0x1F030010, AXON7::iohs7_pll_func , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 328
1429- {eq_fure , "eq_fure" , 0x2003402F, EQ::eq_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 329
1430+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 329
1431 {eq_cmsk , "eq_cmsk" , 0x2003402A, EQ::eq_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 330
1432- {eq_inex , "eq_inex" , 0x2003402B, EQ::eq_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 331
1433+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 331
1434 {eq_mode , "eq_mode" , 0x20034021, EQ::eq_mode , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 332
1435- {eq_clkadj_fure , "eq_clkadj_fure" , 0x2003001F, EQ::eq_clkadj_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 333
1436+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 333
1437 {eq_clkadj_cmsk , "eq_clkadj_cmsk" , 0x2003001A, EQ::eq_clkadj_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 334
1438- {eq_clkadj_inex , "eq_clkadj_inex" , 0x2003001B, EQ::eq_clkadj_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 335
1439- {eq_clkadj_mode , "eq_clkadj_mode" , 0x20030011, EQ::eq_clkadj_mode , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 336
1440- {ec_cl2_fure , "ec_cl2_fure" , 0x2003200F, EQ::ec_cl2_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 337
1441+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 335
1442+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 336
1443+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 337
1444 {ec_cl2_cmsk , "ec_cl2_cmsk" , 0x2003200A, EQ::ec_cl2_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 338
1445 {ec_cl2_inex , "ec_cl2_inex" , 0x2003200B, EQ::ec_cl2_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 339
1446 {ec_cl2_mode , "ec_cl2_mode" , 0x20032001, EQ::ec_cl2_mode , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 340
1447- {ec_mma_fure , "ec_mma_fure" , 0x2083000F, EQ::ec_mma_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 341
1448+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 341
1449 {ec_mma_cmsk , "ec_mma_cmsk" , 0x2083000A, EQ::ec_mma_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 342
1450- {ec_mma_inex , "ec_mma_inex" , 0x2083000B, EQ::ec_mma_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 343
1451- {ec_l3_fure , "ec_l3_fure" , 0x2003020F, EQ::ec_l3_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 344
1452+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 343
1453+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 344
1454 {ec_l3_cmsk , "ec_l3_cmsk" , 0x2003020A, EQ::ec_l3_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 345
1455 {ec_l3_inex , "ec_l3_inex" , 0x2003020B, EQ::ec_l3_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 346
1456- {ec_l3_mode , "ec_l3_mode" , 0x20030201, EQ::ec_l3_mode , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 347
1457+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 347
1458 {n0_abst , "n0_abst" , 0x02036405, N0::n0_abst , N0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 348
1459 {n1_abst , "n1_abst" , 0x03035405, N1::n1_abst , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 349
1460 {n1_nmmu1_abst , "n1_nmmu1_abst" , 0x03030205, N1::n1_nmmu1_abst , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 350
1461 {ec_cl2_abst , "ec_cl2_abst" , 0x20032005, EQ::ec_cl2_abst , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 351
1462 {ec_mma_abst , "ec_mma_abst" , 0x20830005, EQ::ec_mma_abst , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 352
1463+ {perv_func , "perv_func" , 0x01034100, PERV::perv_func , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 353
1464+ {sbe_func , "sbe_func" , 0x01032000, PERV::sbe_func , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 354
1465+ {occ_func , "occ_func" , 0x01030800, PERV::occ_func , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 355
1466+ {perv_pll_bndy_bucket_0 , "perv_pll_bndy_bucket_0" , 0x01030018, PERV::perv_pll_bndy_bucket_0 , PERV_TYPE , RCLS_EKB_RINGS }, // 356
1467+ {perv_pll_bndy_bucket_1 , "perv_pll_bndy_bucket_1" , 0x01030018, PERV::perv_pll_bndy_bucket_1 , PERV_TYPE , RCLS_EKB_RINGS }, // 357
1468+ {perv_pll_bndy_bucket_2 , "perv_pll_bndy_bucket_2" , 0x01030018, PERV::perv_pll_bndy_bucket_2 , PERV_TYPE , RCLS_EKB_RINGS }, // 358
1469+ {perv_pll_bndy_bucket_3 , "perv_pll_bndy_bucket_3" , 0x01030018, PERV::perv_pll_bndy_bucket_3 , PERV_TYPE , RCLS_EKB_RINGS }, // 359
1470+ {n0_func , "n0_func" , 0x02036400, N0::n0_func , N0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 360
1471+ {n1_func , "n1_func" , 0x03035400, N1::n1_func , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 361
1472+ {n1_nmmu1_func , "n1_nmmu1_func" , 0x03030200, N1::n1_nmmu1_func , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 362
1473+ {pci_func , "pci_func" , 0x08037F80, PCI::pci_func , PCI_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 363
1474+ {pci_pll_bndy_bucket_0 , "pci_pll_bndy_bucket_0" , 0x08030018, PCI::pci_pll_bndy_bucket_0 , PCI_TYPE , RCLS_EKB_RINGS }, // 364
1475+ {pci_pll_bndy_bucket_1 , "pci_pll_bndy_bucket_1" , 0x08030018, PCI::pci_pll_bndy_bucket_1 , PCI_TYPE , RCLS_EKB_RINGS }, // 365
1476+ {pci_pll_bndy_bucket_2 , "pci_pll_bndy_bucket_2" , 0x08030018, PCI::pci_pll_bndy_bucket_2 , PCI_TYPE , RCLS_EKB_RINGS }, // 366
1477+ {pci_pll_bndy_bucket_3 , "pci_pll_bndy_bucket_3" , 0x08030018, PCI::pci_pll_bndy_bucket_3 , PCI_TYPE , RCLS_EKB_RINGS }, // 367
1478+ {mc_func , "mc_func" , 0x0C036F00, MC::mc_func , MC_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 368
1479+ {mc_pll_bndy_bucket_5 , "mc_pll_bndy_bucket_5" , 0x0C030018, MC::mc_pll_bndy_bucket_5 , MC_TYPE , RCLS_EKB_RINGS }, // 369
1480+ {mc_pll_bndy_bucket_6 , "mc_pll_bndy_bucket_6" , 0x0C030018, MC::mc_pll_bndy_bucket_6 , MC_TYPE , RCLS_EKB_RINGS }, // 370
1481+ {mc_pll_bndy_bucket_7 , "mc_pll_bndy_bucket_7" , 0x0C030018, MC::mc_pll_bndy_bucket_7 , MC_TYPE , RCLS_EKB_RINGS }, // 371
1482+ {pau0_func , "pau0_func" , 0x10034300, PAU0::pau0_func , PAU0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 372
1483+ {pau0_pau0_func , "pau0_pau0_func" , 0x10032000, PAU0::pau0_pau0_func , PAU0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 373
1484+ {pau1_func , "pau1_func" , 0x11034300, PAU1::pau1_func , PAU1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 374
1485+ {pau1_pau3_func , "pau1_pau3_func" , 0x11032000, PAU1::pau1_pau3_func , PAU1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 375
1486+ {pau2_func , "pau2_func" , 0x12034300, PAU2::pau2_func , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 376
1487+ {pau2_pau4_func , "pau2_pau4_func" , 0x12032000, PAU2::pau2_pau4_func , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 377
1488+ {pau2_pau5_func , "pau2_pau5_func" , 0x12031000, PAU2::pau2_pau5_func , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 378
1489+ {pau3_func , "pau3_func" , 0x13034300, PAU3::pau3_func , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 379
1490+ {pau3_pau6_func , "pau3_pau6_func" , 0x13032000, PAU3::pau3_pau6_func , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 380
1491+ {pau3_pau7_func , "pau3_pau7_func" , 0x13031000, PAU3::pau3_pau7_func , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 381
1492+ {iohs0_func , "iohs0_func" , 0x18036000, AXON0::iohs0_func , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 382
1493+ {iohs0_pdl_func , "iohs0_pdl_func" , 0x18030200, AXON0::iohs0_pdl_func , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 383
1494+ {iohs0_pll_bndy_bucket_8 , "iohs0_pll_bndy_bucket_8" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_8, AXON0_TYPE, RCLS_EKB_RINGS }, // 384
1495+ {iohs0_pll_bndy_bucket_9 , "iohs0_pll_bndy_bucket_9" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_9, AXON0_TYPE, RCLS_EKB_RINGS }, // 385
1496+ {iohs0_pll_bndy_bucket_10, "iohs0_pll_bndy_bucket_10", 0x18030018, AXON0::iohs0_pll_bndy_bucket_10, AXON0_TYPE, RCLS_EKB_RINGS }, // 386
1497+ {iohs0_pll_bndy_bucket_11, "iohs0_pll_bndy_bucket_11", 0x18030018, AXON0::iohs0_pll_bndy_bucket_11, AXON0_TYPE, RCLS_EKB_RINGS }, // 387
1498+ {iohs0_pll_bndy_bucket_12, "iohs0_pll_bndy_bucket_12", 0x18030018, AXON0::iohs0_pll_bndy_bucket_12, AXON0_TYPE, RCLS_EKB_RINGS }, // 388
1499+ {iohs0_pll_bndy_bucket_13, "iohs0_pll_bndy_bucket_13", 0x18030018, AXON0::iohs0_pll_bndy_bucket_13, AXON0_TYPE, RCLS_EKB_RINGS }, // 389
1500+ {iohs0_pll_bndy_bucket_14, "iohs0_pll_bndy_bucket_14", 0x18030018, AXON0::iohs0_pll_bndy_bucket_14, AXON0_TYPE, RCLS_EKB_RINGS }, // 390
1501+ {iohs0_pll_bndy_bucket_15, "iohs0_pll_bndy_bucket_15", 0x18030018, AXON0::iohs0_pll_bndy_bucket_15, AXON0_TYPE, RCLS_EKB_RINGS }, // 391
1502+ {iohs1_func , "iohs1_func" , 0x19036000, AXON1::iohs1_func , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 392
1503+ {iohs1_pdl_func , "iohs1_pdl_func" , 0x19030200, AXON1::iohs1_pdl_func , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 393
1504+ {iohs2_func , "iohs2_func" , 0x1A036000, AXON2::iohs2_func , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 394
1505+ {iohs2_pdl_func , "iohs2_pdl_func" , 0x1A030200, AXON2::iohs2_pdl_func , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 395
1506+ {iohs3_func , "iohs3_func" , 0x1B036000, AXON3::iohs3_func , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 396
1507+ {iohs3_pdl_func , "iohs3_pdl_func" , 0x1B030200, AXON3::iohs3_pdl_func , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 397
1508+ {iohs4_func , "iohs4_func" , 0x1C036000, AXON4::iohs4_func , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 398
1509+ {iohs4_pdl_func , "iohs4_pdl_func" , 0x1C030200, AXON4::iohs4_pdl_func , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 399
1510+ {iohs5_func , "iohs5_func" , 0x1D036000, AXON5::iohs5_func , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 400
1511+ {iohs5_pdl_func , "iohs5_pdl_func" , 0x1D030200, AXON5::iohs5_pdl_func , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 401
1512+ {iohs6_func , "iohs6_func" , 0x1E036000, AXON6::iohs6_func , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 402
1513+ {iohs6_pdl_func , "iohs6_pdl_func" , 0x1E030200, AXON6::iohs6_pdl_func , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 403
1514+ {iohs7_func , "iohs7_func" , 0x1F036000, AXON7::iohs7_func , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 404
1515+ {iohs7_pdl_func , "iohs7_pdl_func" , 0x1F030200, AXON7::iohs7_pdl_func , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 405
1516+ {eq_func , "eq_func" , 0x20034020, EQ::eq_func , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 406
1517+ {eq_clkadj_func , "eq_clkadj_func" , 0x20030010, EQ::eq_clkadj_func , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 407
1518+ {ec_cl2_func , "ec_cl2_func" , 0x20032000, EQ::ec_cl2_func , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 408
1519+ {ec_mma_func , "ec_mma_func" , 0x20830000, EQ::ec_mma_func , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 409
1520+ {ec_l3_func , "ec_l3_func" , 0x20030200, EQ::ec_l3_func , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 410
1521 };
1522 #endif
1523
1524@@ -891,8 +921,8 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1525 {PERV::perv_occ_time , PERV_TYPE }, // 2
1526 {PERV::pib_repr , PERV_TYPE }, // 3
1527 {PERV::sbe_gptr , PERV_TYPE }, // 4
1528- {PERV::sbe_repr , PERV_TYPE }, // 5
1529- {PERV::sbe_time , PERV_TYPE }, // 6
1530+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 5
1531+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 6
1532 {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 7
1533 {PERV::perv_dpll_gptr , PERV_TYPE }, // 8
1534 {PERV::perv_pll_gptr , PERV_TYPE }, // 9
1535@@ -946,9 +976,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1536 {AXON0::iohs0_gptr , AXON0_TYPE}, // 57
1537 {AXON0::iohs0_repr , AXON0_TYPE}, // 58
1538 {AXON0::iohs0_time , AXON0_TYPE}, // 59
1539- {AXON0::iohs0_ndl_gptr , AXON0_TYPE}, // 60
1540- {AXON0::iohs0_ndl_repr , AXON0_TYPE}, // 61
1541- {AXON0::iohs0_ndl_time , AXON0_TYPE}, // 62
1542+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 60
1543+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 61
1544+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 62
1545 {AXON0::iohs0_pdl_gptr , AXON0_TYPE}, // 63
1546 {AXON0::iohs0_pdl_repr , AXON0_TYPE}, // 64
1547 {AXON0::iohs0_pdl_time , AXON0_TYPE}, // 65
1548@@ -956,9 +986,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1549 {AXON1::iohs1_gptr , AXON1_TYPE}, // 67
1550 {AXON1::iohs1_repr , AXON1_TYPE}, // 68
1551 {AXON1::iohs1_time , AXON1_TYPE}, // 69
1552- {AXON1::iohs1_ndl_gptr , AXON1_TYPE}, // 70
1553- {AXON1::iohs1_ndl_repr , AXON1_TYPE}, // 71
1554- {AXON1::iohs1_ndl_time , AXON1_TYPE}, // 72
1555+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 70
1556+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 71
1557+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 72
1558 {AXON1::iohs1_pdl_gptr , AXON1_TYPE}, // 73
1559 {AXON1::iohs1_pdl_repr , AXON1_TYPE}, // 74
1560 {AXON1::iohs1_pdl_time , AXON1_TYPE}, // 75
1561@@ -966,9 +996,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1562 {AXON2::iohs2_gptr , AXON2_TYPE}, // 77
1563 {AXON2::iohs2_repr , AXON2_TYPE}, // 78
1564 {AXON2::iohs2_time , AXON2_TYPE}, // 79
1565- {AXON2::iohs2_ndl_gptr , AXON2_TYPE}, // 80
1566- {AXON2::iohs2_ndl_repr , AXON2_TYPE}, // 81
1567- {AXON2::iohs2_ndl_time , AXON2_TYPE}, // 82
1568+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 80
1569+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 81
1570+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 82
1571 {AXON2::iohs2_pdl_gptr , AXON2_TYPE}, // 83
1572 {AXON2::iohs2_pdl_repr , AXON2_TYPE}, // 84
1573 {AXON2::iohs2_pdl_time , AXON2_TYPE}, // 85
1574@@ -976,9 +1006,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1575 {AXON3::iohs3_gptr , AXON3_TYPE}, // 87
1576 {AXON3::iohs3_repr , AXON3_TYPE}, // 88
1577 {AXON3::iohs3_time , AXON3_TYPE}, // 89
1578- {AXON3::iohs3_ndl_gptr , AXON3_TYPE}, // 90
1579- {AXON3::iohs3_ndl_repr , AXON3_TYPE}, // 91
1580- {AXON3::iohs3_ndl_time , AXON3_TYPE}, // 92
1581+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 90
1582+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 91
1583+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 92
1584 {AXON3::iohs3_pdl_gptr , AXON3_TYPE}, // 93
1585 {AXON3::iohs3_pdl_repr , AXON3_TYPE}, // 94
1586 {AXON3::iohs3_pdl_time , AXON3_TYPE}, // 95
1587@@ -986,9 +1016,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1588 {AXON4::iohs4_gptr , AXON4_TYPE}, // 97
1589 {AXON4::iohs4_repr , AXON4_TYPE}, // 98
1590 {AXON4::iohs4_time , AXON4_TYPE}, // 99
1591- {AXON4::iohs4_ndl_gptr , AXON4_TYPE}, // 100
1592- {AXON4::iohs4_ndl_repr , AXON4_TYPE}, // 101
1593- {AXON4::iohs4_ndl_time , AXON4_TYPE}, // 102
1594+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 100
1595+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 101
1596+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 102
1597 {AXON4::iohs4_pdl_gptr , AXON4_TYPE}, // 103
1598 {AXON4::iohs4_pdl_repr , AXON4_TYPE}, // 104
1599 {AXON4::iohs4_pdl_time , AXON4_TYPE}, // 105
1600@@ -996,9 +1026,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1601 {AXON5::iohs5_gptr , AXON5_TYPE}, // 107
1602 {AXON5::iohs5_repr , AXON5_TYPE}, // 108
1603 {AXON5::iohs5_time , AXON5_TYPE}, // 109
1604- {AXON5::iohs5_ndl_gptr , AXON5_TYPE}, // 110
1605- {AXON5::iohs5_ndl_repr , AXON5_TYPE}, // 111
1606- {AXON5::iohs5_ndl_time , AXON5_TYPE}, // 112
1607+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 110
1608+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 111
1609+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 112
1610 {AXON5::iohs5_pdl_gptr , AXON5_TYPE}, // 113
1611 {AXON5::iohs5_pdl_repr , AXON5_TYPE}, // 114
1612 {AXON5::iohs5_pdl_time , AXON5_TYPE}, // 115
1613@@ -1006,9 +1036,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1614 {AXON6::iohs6_gptr , AXON6_TYPE}, // 117
1615 {AXON6::iohs6_repr , AXON6_TYPE}, // 118
1616 {AXON6::iohs6_time , AXON6_TYPE}, // 119
1617- {AXON6::iohs6_ndl_gptr , AXON6_TYPE}, // 120
1618- {AXON6::iohs6_ndl_repr , AXON6_TYPE}, // 121
1619- {AXON6::iohs6_ndl_time , AXON6_TYPE}, // 122
1620+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 120
1621+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 121
1622+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 122
1623 {AXON6::iohs6_pdl_gptr , AXON6_TYPE}, // 123
1624 {AXON6::iohs6_pdl_repr , AXON6_TYPE}, // 124
1625 {AXON6::iohs6_pdl_time , AXON6_TYPE}, // 125
1626@@ -1016,9 +1046,9 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1627 {AXON7::iohs7_gptr , AXON7_TYPE}, // 127
1628 {AXON7::iohs7_repr , AXON7_TYPE}, // 128
1629 {AXON7::iohs7_time , AXON7_TYPE}, // 129
1630- {AXON7::iohs7_ndl_gptr , AXON7_TYPE}, // 130
1631- {AXON7::iohs7_ndl_repr , AXON7_TYPE}, // 131
1632- {AXON7::iohs7_ndl_time , AXON7_TYPE}, // 132
1633+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 130
1634+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 131
1635+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 132
1636 {AXON7::iohs7_pdl_gptr , AXON7_TYPE}, // 133
1637 {AXON7::iohs7_pdl_repr , AXON7_TYPE}, // 134
1638 {AXON7::iohs7_pdl_time , AXON7_TYPE}, // 135
1639@@ -1027,8 +1057,8 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1640 {EQ::eq_repr , EQ_TYPE }, // 138
1641 {EQ::eq_time , EQ_TYPE }, // 139
1642 {EQ::eq_clkadj_gptr , EQ_TYPE }, // 140
1643- {EQ::eq_clkadj_repr , EQ_TYPE }, // 141
1644- {EQ::eq_clkadj_time , EQ_TYPE }, // 142
1645+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 141
1646+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 142
1647 {EQ::ec_cl2_gptr , EQ_TYPE }, // 143
1648 {EQ::ec_cl2_repr , EQ_TYPE }, // 144
1649 {EQ::ec_cl2_time , EQ_TYPE }, // 145
1650@@ -1036,7 +1066,7 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1651 {EQ::ec2_cl2_repr , EQ_TYPE }, // 147
1652 {EQ::ec3_cl2_repr , EQ_TYPE }, // 148
1653 {EQ::ec_mma_gptr , EQ_TYPE }, // 149
1654- {EQ::ec_mma_repr , EQ_TYPE }, // 150
1655+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 150
1656 {EQ::ec_mma_time , EQ_TYPE }, // 151
1657 {EQ::ec1_mma_repr , EQ_TYPE }, // 152
1658 {EQ::ec2_mma_repr , EQ_TYPE }, // 153
1659@@ -1056,43 +1086,43 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1660 {EQ::eq_gptr_ovly , EQ_TYPE }, // 167
1661
1662 // EKB Rings:
1663- {PERV::perv_fure , PERV_TYPE }, // 256
1664- {PERV::sbe_fure , PERV_TYPE }, // 257
1665- {PERV::occ_fure , PERV_TYPE }, // 258
1666+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 256
1667+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 257
1668+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 258
1669 {PERV::perv_dpll_func , PERV_TYPE }, // 259
1670- {PERV::perv_dpll_bndy , PERV_TYPE }, // 260
1671+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 260
1672 {PERV::perv_dpll_time , PERV_TYPE }, // 261
1673 {PERV::perv_pll_func , PERV_TYPE }, // 262
1674- {PERV::perv_pll_bndy , PERV_TYPE }, // 263
1675- {N0::n0_fure , N0_TYPE }, // 264
1676- {N1::n1_fure , N1_TYPE }, // 265
1677- {N1::n1_nmmu1_fure , N1_TYPE }, // 266
1678- {PCI::pci_fure , PCI_TYPE }, // 267
1679+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 263
1680+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 264
1681+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 265
1682+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 266
1683+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 267
1684 {PCI::pci_pll_func , PCI_TYPE }, // 268
1685- {PCI::pci_pll_bndy , PCI_TYPE }, // 269
1686- {MC::mc_fure , MC_TYPE }, // 270
1687+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 269
1688+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 270
1689 {MC::mc_pll_func , MC_TYPE }, // 271
1690- {MC::mc_pll_bndy , MC_TYPE }, // 272
1691+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 272
1692 {MC::mc_pll_bndy_bucket_0 , MC_TYPE }, // 273
1693 {MC::mc_pll_bndy_bucket_1 , MC_TYPE }, // 274
1694 {MC::mc_pll_bndy_bucket_2 , MC_TYPE }, // 275
1695 {MC::mc_pll_bndy_bucket_3 , MC_TYPE }, // 276
1696 {MC::mc_pll_bndy_bucket_4 , MC_TYPE }, // 277
1697- {PAU0::pau0_fure , PAU0_TYPE }, // 278
1698- {PAU0::pau0_pau0_fure , PAU0_TYPE }, // 279
1699- {PAU1::pau1_fure , PAU1_TYPE }, // 280
1700- {PAU1::pau1_pau3_fure , PAU1_TYPE }, // 281
1701- {PAU2::pau2_fure , PAU2_TYPE }, // 282
1702- {PAU2::pau2_pau4_fure , PAU2_TYPE }, // 283
1703- {PAU2::pau2_pau5_fure , PAU2_TYPE }, // 284
1704- {PAU3::pau3_fure , PAU3_TYPE }, // 285
1705- {PAU3::pau3_pau6_fure , PAU3_TYPE }, // 286
1706- {PAU3::pau3_pau7_fure , PAU3_TYPE }, // 287
1707- {AXON0::iohs0_fure , AXON0_TYPE}, // 288
1708- {AXON0::iohs0_ndl_fure , AXON0_TYPE}, // 289
1709- {AXON0::iohs0_pdl_fure , AXON0_TYPE}, // 290
1710+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 278
1711+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 279
1712+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 280
1713+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 281
1714+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 282
1715+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 283
1716+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 284
1717+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 285
1718+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 286
1719+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 287
1720+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 288
1721+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 289
1722+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 290
1723 {AXON0::iohs0_pll_func , AXON0_TYPE}, // 291
1724- {AXON0::iohs0_pll_bndy , AXON0_TYPE}, // 292
1725+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 292
1726 {AXON0::iohs0_pll_bndy_bucket_0, AXON0_TYPE}, // 293
1727 {AXON0::iohs0_pll_bndy_bucket_1, AXON0_TYPE}, // 294
1728 {AXON0::iohs0_pll_bndy_bucket_2, AXON0_TYPE}, // 295
1729@@ -1101,58 +1131,116 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
1730 {AXON0::iohs0_pll_bndy_bucket_5, AXON0_TYPE}, // 298
1731 {AXON0::iohs0_pll_bndy_bucket_6, AXON0_TYPE}, // 299
1732 {AXON0::iohs0_pll_bndy_bucket_7, AXON0_TYPE}, // 300
1733- {AXON1::iohs1_fure , AXON1_TYPE}, // 301
1734- {AXON1::iohs1_ndl_fure , AXON1_TYPE}, // 302
1735- {AXON1::iohs1_pdl_fure , AXON1_TYPE}, // 303
1736+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 301
1737+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 302
1738+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 303
1739 {AXON1::iohs1_pll_func , AXON1_TYPE}, // 304
1740- {AXON2::iohs2_fure , AXON2_TYPE}, // 305
1741- {AXON2::iohs2_ndl_fure , AXON2_TYPE}, // 306
1742- {AXON2::iohs2_pdl_fure , AXON2_TYPE}, // 307
1743+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 305
1744+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 306
1745+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 307
1746 {AXON2::iohs2_pll_func , AXON2_TYPE}, // 308
1747- {AXON3::iohs3_fure , AXON3_TYPE}, // 309
1748- {AXON3::iohs3_ndl_fure , AXON3_TYPE}, // 310
1749- {AXON3::iohs3_pdl_fure , AXON3_TYPE}, // 311
1750+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 309
1751+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 310
1752+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 311
1753 {AXON3::iohs3_pll_func , AXON3_TYPE}, // 312
1754- {AXON4::iohs4_fure , AXON4_TYPE}, // 313
1755- {AXON4::iohs4_ndl_fure , AXON4_TYPE}, // 314
1756- {AXON4::iohs4_pdl_fure , AXON4_TYPE}, // 315
1757+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 313
1758+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 314
1759+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 315
1760 {AXON4::iohs4_pll_func , AXON4_TYPE}, // 316
1761- {AXON5::iohs5_fure , AXON5_TYPE}, // 317
1762- {AXON5::iohs5_ndl_fure , AXON5_TYPE}, // 318
1763- {AXON5::iohs5_pdl_fure , AXON5_TYPE}, // 319
1764+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 317
1765+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 318
1766+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 319
1767 {AXON5::iohs5_pll_func , AXON5_TYPE}, // 320
1768- {AXON6::iohs6_fure , AXON6_TYPE}, // 321
1769- {AXON6::iohs6_ndl_fure , AXON6_TYPE}, // 322
1770- {AXON6::iohs6_pdl_fure , AXON6_TYPE}, // 323
1771+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 321
1772+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 322
1773+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 323
1774 {AXON6::iohs6_pll_func , AXON6_TYPE}, // 324
1775- {AXON7::iohs7_fure , AXON7_TYPE}, // 325
1776- {AXON7::iohs7_ndl_fure , AXON7_TYPE}, // 326
1777- {AXON7::iohs7_pdl_fure , AXON7_TYPE}, // 327
1778+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 325
1779+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 326
1780+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 327
1781 {AXON7::iohs7_pll_func , AXON7_TYPE}, // 328
1782- {EQ::eq_fure , EQ_TYPE }, // 329
1783+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 329
1784 {EQ::eq_cmsk , EQ_TYPE }, // 330
1785- {EQ::eq_inex , EQ_TYPE }, // 331
1786+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 331
1787 {EQ::eq_mode , EQ_TYPE }, // 332
1788- {EQ::eq_clkadj_fure , EQ_TYPE }, // 333
1789+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 333
1790 {EQ::eq_clkadj_cmsk , EQ_TYPE }, // 334
1791- {EQ::eq_clkadj_inex , EQ_TYPE }, // 335
1792- {EQ::eq_clkadj_mode , EQ_TYPE }, // 336
1793- {EQ::ec_cl2_fure , EQ_TYPE }, // 337
1794+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 335
1795+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 336
1796+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 337
1797 {EQ::ec_cl2_cmsk , EQ_TYPE }, // 338
1798 {EQ::ec_cl2_inex , EQ_TYPE }, // 339
1799 {EQ::ec_cl2_mode , EQ_TYPE }, // 340
1800- {EQ::ec_mma_fure , EQ_TYPE }, // 341
1801+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 341
1802 {EQ::ec_mma_cmsk , EQ_TYPE }, // 342
1803- {EQ::ec_mma_inex , EQ_TYPE }, // 343
1804- {EQ::ec_l3_fure , EQ_TYPE }, // 344
1805+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 343
1806+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 344
1807 {EQ::ec_l3_cmsk , EQ_TYPE }, // 345
1808 {EQ::ec_l3_inex , EQ_TYPE }, // 346
1809- {EQ::ec_l3_mode , EQ_TYPE }, // 347
1810+ {UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE}, // 347
1811 {N0::n0_abst , N0_TYPE }, // 348
1812 {N1::n1_abst , N1_TYPE }, // 349
1813 {N1::n1_nmmu1_abst , N1_TYPE }, // 350
1814 {EQ::ec_cl2_abst , EQ_TYPE }, // 351
1815 {EQ::ec_mma_abst , EQ_TYPE }, // 352
1816+ {PERV::perv_func , PERV_TYPE }, // 353
1817+ {PERV::sbe_func , PERV_TYPE }, // 354
1818+ {PERV::occ_func , PERV_TYPE }, // 355
1819+ {PERV::perv_pll_bndy_bucket_0 , PERV_TYPE }, // 356
1820+ {PERV::perv_pll_bndy_bucket_1 , PERV_TYPE }, // 357
1821+ {PERV::perv_pll_bndy_bucket_2 , PERV_TYPE }, // 358
1822+ {PERV::perv_pll_bndy_bucket_3 , PERV_TYPE }, // 359
1823+ {N0::n0_func , N0_TYPE }, // 360
1824+ {N1::n1_func , N1_TYPE }, // 361
1825+ {N1::n1_nmmu1_func , N1_TYPE }, // 362
1826+ {PCI::pci_func , PCI_TYPE }, // 363
1827+ {PCI::pci_pll_bndy_bucket_0 , PCI_TYPE }, // 364
1828+ {PCI::pci_pll_bndy_bucket_1 , PCI_TYPE }, // 365
1829+ {PCI::pci_pll_bndy_bucket_2 , PCI_TYPE }, // 366
1830+ {PCI::pci_pll_bndy_bucket_3 , PCI_TYPE }, // 367
1831+ {MC::mc_func , MC_TYPE }, // 368
1832+ {MC::mc_pll_bndy_bucket_5 , MC_TYPE }, // 369
1833+ {MC::mc_pll_bndy_bucket_6 , MC_TYPE }, // 370
1834+ {MC::mc_pll_bndy_bucket_7 , MC_TYPE }, // 371
1835+ {PAU0::pau0_func , PAU0_TYPE }, // 372
1836+ {PAU0::pau0_pau0_func , PAU0_TYPE }, // 373
1837+ {PAU1::pau1_func , PAU1_TYPE }, // 374
1838+ {PAU1::pau1_pau3_func , PAU1_TYPE }, // 375
1839+ {PAU2::pau2_func , PAU2_TYPE }, // 376
1840+ {PAU2::pau2_pau4_func , PAU2_TYPE }, // 377
1841+ {PAU2::pau2_pau5_func , PAU2_TYPE }, // 378
1842+ {PAU3::pau3_func , PAU3_TYPE }, // 379
1843+ {PAU3::pau3_pau6_func , PAU3_TYPE }, // 380
1844+ {PAU3::pau3_pau7_func , PAU3_TYPE }, // 381
1845+ {AXON0::iohs0_func , AXON0_TYPE}, // 382
1846+ {AXON0::iohs0_pdl_func , AXON0_TYPE}, // 383
1847+ {AXON0::iohs0_pll_bndy_bucket_8, AXON0_TYPE}, // 384
1848+ {AXON0::iohs0_pll_bndy_bucket_9, AXON0_TYPE}, // 385
1849+ {AXON0::iohs0_pll_bndy_bucket_10, AXON0_TYPE}, // 386
1850+ {AXON0::iohs0_pll_bndy_bucket_11, AXON0_TYPE}, // 387
1851+ {AXON0::iohs0_pll_bndy_bucket_12, AXON0_TYPE}, // 388
1852+ {AXON0::iohs0_pll_bndy_bucket_13, AXON0_TYPE}, // 389
1853+ {AXON0::iohs0_pll_bndy_bucket_14, AXON0_TYPE}, // 390
1854+ {AXON0::iohs0_pll_bndy_bucket_15, AXON0_TYPE}, // 391
1855+ {AXON1::iohs1_func , AXON1_TYPE}, // 392
1856+ {AXON1::iohs1_pdl_func , AXON1_TYPE}, // 393
1857+ {AXON2::iohs2_func , AXON2_TYPE}, // 394
1858+ {AXON2::iohs2_pdl_func , AXON2_TYPE}, // 395
1859+ {AXON3::iohs3_func , AXON3_TYPE}, // 396
1860+ {AXON3::iohs3_pdl_func , AXON3_TYPE}, // 397
1861+ {AXON4::iohs4_func , AXON4_TYPE}, // 398
1862+ {AXON4::iohs4_pdl_func , AXON4_TYPE}, // 399
1863+ {AXON5::iohs5_func , AXON5_TYPE}, // 400
1864+ {AXON5::iohs5_pdl_func , AXON5_TYPE}, // 401
1865+ {AXON6::iohs6_func , AXON6_TYPE}, // 402
1866+ {AXON6::iohs6_pdl_func , AXON6_TYPE}, // 403
1867+ {AXON7::iohs7_func , AXON7_TYPE}, // 404
1868+ {AXON7::iohs7_pdl_func , AXON7_TYPE}, // 405
1869+ {EQ::eq_func , EQ_TYPE }, // 406
1870+ {EQ::eq_clkadj_func , EQ_TYPE }, // 407
1871+ {EQ::ec_cl2_func , EQ_TYPE }, // 408
1872+ {EQ::ec_mma_func , EQ_TYPE }, // 409
1873+ {EQ::ec_l3_func , EQ_TYPE }, // 410
1874 };
1875 #endif // __PPE__
1876
1877diff --git a/src/import/chips/p10/utils/imageProcs/p10_tor.C b/src/import/chips/p10/utils/imageProcs/p10_tor.C
1878index 7dced57..2baf991 100644
1879--- a/src/import/chips/p10/utils/imageProcs/p10_tor.C
1880+++ b/src/import/chips/p10/utils/imageProcs/p10_tor.C
1881@@ -210,6 +210,17 @@ int _tor_access_ring( void* io_ringSection, // Ring section ptr
1882
1883 if (ringOffset)
1884 {
1885+ RingId_t ringIdRs4 = be16toh( ((CompressedScanData*)
1886+ ((uint8_t*)io_ringSection + ringOffset))->iv_ringId );
1887+
1888+ if (i_ringId != ringIdRs4)
1889+ {
1890+ MY_ERR("ERROR: _tor_access_ring(): Requested ringId(=0x%03x) and RS4 header's"
1891+ " ringId(=0x%03x) don't match for rpIndex=0x%03x\n",
1892+ i_ringId, ringIdRs4, rpIndex);
1893+ return TOR_RING_ID_MISMATCH;
1894+ }
1895+
1896 rs4Size = be16toh( ((CompressedScanData*)
1897 ((uint8_t*)io_ringSection + ringOffset))->iv_size );
1898
1899--
19001.8.2.2
1901