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gerrit.openbmc.org / premsjha / op-build / 9ee6207199bfb7a412d1159a8f8bfd3410e16951 / . / openpower / package / hostboot / p9Patches / hostboot-0002-TOR-Magic-header-support.patch
blob: f13ec7fe600c5b15a618f9fea5fabbe2c4e59b96 [file] [log] [blame]
Bill Hoffaa9b56ff2017-10-04 21:19:42 -0500[diff] [blame]1From 583cf99ed879916632f823444129c21056267d4c Mon Sep 17 00:00:00 2001
2From: Claus Michael Olsen <cmolsen@us.ibm.com>
3Date: Tue, 24 Jan 2017 23:42:50 -0600
4Subject: [PATCH] TOR Magic header support
5
6HW-Image-Coreq=Yes
7SBE-Image-Coreq=No (SBE image is back compatible)
8
9This commit adds an 12-byte header to all TOR ring sections:
10- for improved self-containment of TOR ring sections incl
11 stand-alone ring sections like .overrides which, currently,
12 has no meaningful size info associated with it in the PNOR,
13- to support a more data-driven implementation of TOR API,
14- to eliminate the current usage of XIP_MAGIC ids to inform the
15 TOR APIs which ring section they are dealing with, and
16- to improve debugging binary ring sections.
17
18The TOR header expands on the current TorNumDdLevels field in the
19HW ring section and is added to all other ring sections as well,
20e.g. for the SBE and OVRD ring sections. Most importantly, the
21TOR header adds the TOR magic number which is unique for each
22possible TOR ring section. Also, of quite practical importance,
23a size field has been added so that the size of a true standalone
24section like .overrides can be extracted (since its size in PNOR
25is not indicative of its size).
26
27Further, to support the use of ddLevel and chipType in the TOR
28header fields, these two data points need to be always supplied
29whenever calling ring_apply. Thus, updates have been made to the
30ring_apply.mk file as well as the override .pl script. While
31making these changes, we also decided to change the --type arg
32to the --bOverrides arg to make the arguments being passed less
33confusing in view of the Centaur commit that's coming and its
34demands to make codes less data dependent, incl make and script
35files which should simply inform the functional intent of the
36"user". The user shouldn't presume it knows about which specific
37type of ring section needs to be produced.
38
39Further, the DD level block struct has been increased from 8B
40to 12B to avoid the unnecessarily complex merging of the
41ddLevel and offset into the same 4B field. It's included in
42this commit since this is also going to break the lab and
43because the required code changes are in the same places
44where the code changes needed for the TOR header are.
45
46Further, xip_tool has been updated to support the new TOR
47header so that it can be called by supplying a standalone
48ring section, such as overrides.bin. Various changes have
49been made in xip_tool's dissect section to support overrides
50as well.
51
52This code uses many of the code changes in 33778 except
53changes to p9_tor.C|H are at a bare minimum focusing on the
54functional changes and keeping any cleanups to a minimum changing
55only some variable names associated with the functional changes
56for improved readability of the code.
57
58CMVC-Prereq: 1034144
59CMVC-Prereq: 1035575
60Change-Id: I29ba8905ac55dad5c10878a94fb94468e5580ea0
61Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35372
62Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
63Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
64Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
65Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37994
66Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
67---
68 src/build/citest/etc/bbuild | 2 +-
69 src/build/citest/etc/workarounds.postsimsetup | 23 +-
70 .../p9/procedures/hwp/customize/p9_xip_customize.C | 1 -
71 .../p9/procedures/hwp/pm/p9_hcode_image_build.C | 7 -
72 src/import/chips/p9/utils/imageProcs/p9_ringId.H | 23 +-
73 src/import/chips/p9/utils/imageProcs/p9_tor.C | 362 +++++++++++----------
74 src/import/chips/p9/utils/imageProcs/p9_tor.H | 97 +++---
75 7 files changed, 286 insertions(+), 229 deletions(-)
76
77diff --git a/src/build/citest/etc/bbuild b/src/build/citest/etc/bbuild
78index aaea664..fac4cb6 100644
79--- a/src/build/citest/etc/bbuild
80+++ b/src/build/citest/etc/bbuild
81@@ -1,3 +1,3 @@
82-/esw/fips910/Builds/b0908a_1738.910
83+/esw/fips910/Builds/b0930a_1740.910
84
85
86diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
87index cced000..70d7f20 100755
88--- a/src/build/citest/etc/workarounds.postsimsetup
89+++ b/src/build/citest/etc/workarounds.postsimsetup
90@@ -32,22 +32,29 @@
91 #mkdir -p $sb/simu/data/cec-chip/
92 #cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip
93 #patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $PROJECT_ROOT/src/build/citest/etc/patches/my_patch_File
94-#pull in new actions in p9_memory.act RTC 171066
95-#pull in SBE makefile change for DD2.1
96-sbex -t 1032604
97-cd $sb/sbei/sbfw/
98-mk -a && mk install_all
99-cd -
100+
101
102 #changes needed for Cumulus
103 #@TODO RTC:178949
104 echo "Applying SIMICS workaround to support Cumulus"
105 sbex -t 1031560
106-sbex -t 1032617
107-sbex -t 1033442
108 cd $sb/simu
109 mk -a
110
111 echo "Copying centaur and p9c action files"
112 sbex -t 1032952
113 sbex -t 1033805
114+
115+#pull in href tor
116+sbex -t 1035576
117+#pull in hwsv tor
118+sbex -t 1034144
119+
120+
121+mkdir $sb/../obj/ppc/hwsv/server/buildhwpfimport/hwpf2/tools/x86_binaries -p
122+cp /gsa/rchgsa/home/c/r/crgeddes/documents/hbBuild/p9_ipl_build $sb/../obj/ppc/hwsv/server/buildhwpfimport/hwpf2/tools/x86_binaries/
123+
124+
125+
126+
127+
128diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
129index c30f31e..cd6e494 100644
130--- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
131+++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C
132@@ -302,7 +302,6 @@ fapi2::ReturnCode get_overlays_ring(
133 // Get Gptr overlay ring from overlays section into ringBuf2
134 l_rc = P9_TOR::tor_get_single_ring(
135 i_overlaysSection,
136- P9_XIP_MAGIC_SEEPROM,
137 l_ddLevel,
138 i_ringId,
139 P9_TOR::SBE,
140diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
141index 781208b..e34a97d 100644
142--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
143+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
144@@ -1893,7 +1893,6 @@ uint32_t getPpeScanRings( void* const i_pHwImage,
145 sgpeOvrdRings.getRingName( quadCmnOvrdRingId ) );
146
147 rc = tor_get_single_ring( i_pOverride,
148- P9_XIP_MAGIC_SEEPROM,
149 i_chipState.getChipLevel(),
150 quadCmnOvrdRingId,
151 P9_TOR::SBE,
152@@ -2373,7 +2372,6 @@ fapi2::ReturnCode layoutCmnRingsForCme( Homerlayout_t* i_pHomer,
153 }
154
155 rc = tor_get_single_ring( i_ringData.iv_pRingBuffer,
156- P9_XIP_MAGIC_CME,
157 i_chipState.getChipLevel(),
158 coreCmnRingId,
159 P9_TOR::CME,
160@@ -2491,7 +2489,6 @@ fapi2::ReturnCode layoutInstRingsForCme( Homerlayout_t* i_pHomer,
161
162 tempSize = i_ringData.iv_sizeWorkBuf1;
163 rc = tor_get_single_ring( i_ringData.iv_pRingBuffer,
164- P9_XIP_MAGIC_CME,
165 i_chipState.getChipLevel(),
166 io_cmeRings.getInstRingId(0),
167 P9_TOR::CME,
168@@ -2556,7 +2553,6 @@ fapi2::ReturnCode layoutInstRingsForCme( Homerlayout_t* i_pHomer,
169
170 tempSize = i_ringData.iv_sizeWorkBuf1;
171 rc = tor_get_single_ring( i_ringData.iv_pRingBuffer,
172- P9_XIP_MAGIC_CME,
173 i_chipState.getChipLevel(),
174 io_cmeRings.getInstRingId(0),
175 P9_TOR::CME,
176@@ -2667,7 +2663,6 @@ fapi2::ReturnCode layoutCmeScanOverride( Homerlayout_t* i_pHomer,
177 cmeOvrdRings.getRingName( coreCmnOvrdRingId ) );
178
179 rc = tor_get_single_ring( i_pOverride,
180- P9_XIP_MAGIC_SEEPROM,
181 i_chipState.getChipLevel(),
182 coreCmnOvrdRingId,
183 P9_TOR::SBE,
184@@ -3019,7 +3014,6 @@ fapi2::ReturnCode layoutCmnRingsForSgpe( Homerlayout_t* i_pHomer,
185 l_ringVariant = BASE;
186 }
187 rc = tor_get_single_ring( i_ringData.iv_pRingBuffer,
188- P9_XIP_MAGIC_SGPE,
189 i_chipState.getChipLevel(),
190 torRingId,
191 P9_TOR::SGPE,
192@@ -3138,7 +3132,6 @@ fapi2::ReturnCode layoutInstRingsForSgpe( Homerlayout_t* i_pHomer,
193
194 quadSpecRingId = io_sgpeRings.getInstRingId( ringIndex );
195 rc = tor_get_single_ring( i_ringData.iv_pRingBuffer,
196- P9_XIP_MAGIC_SGPE,
197 i_chipState.getChipLevel(),
198 quadSpecRingId,
199 P9_TOR::SGPE,
200diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.H b/src/import/chips/p9/utils/imageProcs/p9_ringId.H
201index 2c29ba3..d78e52b 100644
202--- a/src/import/chips/p9/utils/imageProcs/p9_ringId.H
203+++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.H
204@@ -68,9 +68,10 @@ typedef enum RingVariant // Base variables
205 NOT_VALID = 0xff
206 } RingVariant_t;
207
208+#define P9_RINGID_VARIANT_ORDER_SIZE 3
209 typedef struct
210 {
211- uint8_t variant[3];
212+ uint8_t variant[P9_RINGID_VARIANT_ORDER_SIZE];
213 } RingVariantOrder;
214
215
216@@ -244,6 +245,7 @@ const uint8_t INSTANCE_RING_MASK = 0x7F;
217
218 namespace PERV
219 {
220+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
221 struct RingVariants
222 {
223 uint16_t iv_base;
224@@ -289,6 +291,7 @@ static const CHIPLET_DATA g_pervData =
225
226 namespace N0
227 {
228+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
229 struct RingVariants
230 {
231 uint16_t iv_base;
232@@ -318,12 +321,13 @@ static const CHIPLET_DATA g_n0Data =
233 2, // N0 Chiplet ID is 2.
234 9, // 9 common rings for N0 Chiplet
235 3, // 3 instance specific rings for N0 chiplet
236- 3
237+ 3 // FIXME: number of variants? doesn't match RingVariants below!
238 };
239 };
240
241 namespace N1
242 {
243+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
244 struct RingVariants
245 {
246 uint16_t iv_base;
247@@ -363,6 +367,7 @@ static const CHIPLET_DATA g_n1Data =
248
249 namespace N2
250 {
251+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
252 struct RingVariants
253 {
254 uint16_t iv_base;
255@@ -398,6 +403,7 @@ static const CHIPLET_DATA g_n2Data =
256
257 namespace N3
258 {
259+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
260 struct RingVariants
261 {
262 uint16_t iv_base;
263@@ -434,6 +440,7 @@ static const CHIPLET_DATA g_n3Data =
264
265 namespace XB
266 {
267+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
268 struct RingVariants
269 {
270 uint16_t iv_base;
271@@ -476,6 +483,7 @@ static const CHIPLET_DATA g_xbData =
272
273 namespace MC
274 {
275+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
276 struct RingVariants
277 {
278 uint16_t iv_base;
279@@ -519,6 +527,7 @@ static const CHIPLET_DATA g_mcData =
280
281 namespace OB0
282 {
283+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
284 struct RingVariants
285 {
286 uint16_t iv_base;
287@@ -551,6 +560,7 @@ static const CHIPLET_DATA g_ob0Data =
288
289 namespace OB1
290 {
291+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
292 struct RingVariants
293 {
294 uint16_t iv_base;
295@@ -584,6 +594,7 @@ static const CHIPLET_DATA g_ob1Data =
296
297 namespace OB2
298 {
299+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
300 struct RingVariants
301 {
302 uint16_t iv_base;
303@@ -616,6 +627,7 @@ static const CHIPLET_DATA g_ob2Data =
304
305 namespace OB3
306 {
307+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
308 struct RingVariants
309 {
310 uint16_t iv_base;
311@@ -647,6 +659,7 @@ static const CHIPLET_DATA g_ob3Data =
312 }; // end of namespace OB2
313 namespace PCI0
314 {
315+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
316 struct RingVariants
317 {
318 uint16_t iv_base;
319@@ -676,6 +689,7 @@ static const CHIPLET_DATA g_pci0Data =
320
321 namespace PCI1
322 {
323+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
324 struct RingVariants
325 {
326 uint16_t iv_base;
327@@ -705,6 +719,7 @@ static const CHIPLET_DATA g_pci1Data =
328
329 namespace PCI2
330 {
331+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
332 struct RingVariants
333 {
334 uint16_t iv_base;
335@@ -735,6 +750,7 @@ static const CHIPLET_DATA g_pci2Data =
336
337 namespace EQ
338 {
339+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
340 struct RingVariants
341 {
342 uint16_t iv_base;
343@@ -832,6 +848,7 @@ static const CHIPLET_DATA g_eqData =
344
345 namespace EC
346 {
347+// FIXME: this struct is nonsense - no one uses these fields (we only need the variant number)
348 struct RingVariants
349 {
350 uint16_t iv_base;
351@@ -868,7 +885,7 @@ static const uint8_t INVALID_RING = 0xFF;
352 #ifndef __PPE__
353 struct ringProperties_t
354 {
355- uint8_t iv_torOffSet;
356+ uint8_t iv_torOffSet; // FIXME: misnomer
357 char iv_name[50];
358 CHIPLET_TYPE iv_type;
359 };
360diff --git a/src/import/chips/p9/utils/imageProcs/p9_tor.C b/src/import/chips/p9/utils/imageProcs/p9_tor.C
361index b9b793a..d4879c8 100644
362--- a/src/import/chips/p9/utils/imageProcs/p9_tor.C
363+++ b/src/import/chips/p9/utils/imageProcs/p9_tor.C
364@@ -41,9 +41,7 @@
365 // While using tor_tor_get_block_of_rings and tor_get_single_ring API,
366 // it is used pass by value
367 //
368-#include "p9_ringId.H"
369 #include "p9_tor.H"
370-#include "p9_xip_image.h"
371 #include "p9_scan_compression.H"
372 #include "p9_infrastruct_help.H"
373
374@@ -72,7 +70,6 @@ const char* ringVariantName[] = { "BASE",
375 //////////////////////////////////////////////////////////////////////////////////
376 static
377 int get_ring_from_sbe_image( void* i_ringSection, // Ring section ptr
378- uint64_t i_magic, // Image Magic Number
379 RingID i_ringId, // Ring ID
380 uint16_t i_ddLevelOffset, // DD level offset (wrt i_ringSection)
381 RingType_t& io_RingType, // Common, Instance
382@@ -85,11 +82,13 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section
383 uint32_t i_dbgl ) // Debug option
384 {
385 int rc = TOR_SUCCESS;
386+ uint32_t torMagic;
387 uint32_t tor_slot_no = 0; // TOR slot number (within a TOR chiplet section)
388 uint16_t dd_level_offset; // Local DD level offset, if any (wrt i_ringSection)
389 uint32_t acc_offset = 0; // Accumulating offset to next TOR offset
390- uint32_t ppe_offset = 0; // Local offset to where SBE PPE section starts
391- uint32_t cplt_offset = 0; // Local offset to where SBE chiplet section starts
392+ uint32_t ppe_offset = 0; // Local offset to where SBE PPE ring section starts
393+ uint32_t ppe_cplt_offset = 0; // Local offset to where the pool of chiplets starts
394+ uint32_t cplt_offset = 0; // Local offset to where a specific chiplet section starts
395 uint16_t ring_offset = 0; // Local offset to where SBE ring container/block starts
396 uint32_t ring_size = 0; // Size of whole ring container/block.
397 RingVariantOrder* ring_variant_order;
398@@ -98,23 +97,35 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section
399 CHIPLET_DATA* l_cpltData;
400 uint8_t l_num_variant;
401
402- if (i_magic == P9_XIP_MAGIC_HW)
403+ torMagic = be32toh( ((TorHeader_t*)i_ringSection)->magic );
404+
405+ // Calculate the offset (wrt start of ringSection) to the SBE PPE
406+ // ring section. This offset, ppe_offset, will point to the
407+ // TORB header of the SBE PPE ring section.
408+ if (torMagic == TOR_MAGIC_HW)
409 {
410 dd_level_offset = i_ddLevelOffset;
411 ppe_offset = *(uint32_t*)((uint8_t*)i_ringSection + dd_level_offset);
412 ppe_offset = be32toh(ppe_offset);
413 }
414- else if (i_magic == P9_XIP_MAGIC_SEEPROM)
415+ else if (torMagic == TOR_MAGIC_SBE ||
416+ torMagic == TOR_MAGIC_OVRD ||
417+ torMagic == TOR_MAGIC_OVLY)
418 {
419 ppe_offset = 0;
420 dd_level_offset = 0;
421 }
422 else
423 {
424- MY_ERR("Magic number i_magic=0x%016lX is not valid for SBE\n", (uintptr_t)i_magic);
425+ MY_ERR("torMagic=0x%08x is not valid for SBE\n", torMagic);
426 return TOR_INVALID_MAGIC_NUMBER;
427 }
428
429+ // Calculate the offset (wrt start of ringSection) to where the
430+ // pool of chiplet offsets begins in the SBE PPE ring section,
431+ // which is right after the TORB header.
432+ ppe_cplt_offset = ppe_offset + sizeof(TorHeader_t);
433+
434 // Looper for each SBE chiplet
435 for (int iCplt = 0; iCplt < SBE_NOOF_CHIPLETS; iCplt++)
436 {
437@@ -129,7 +140,7 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section
438 return TOR_INVALID_CHIPLET;
439 }
440
441- l_num_variant = (i_RingVariant == OVERRIDE || i_RingVariant == OVERLAY) ? 1 : l_num_variant;
442+ l_num_variant = (torMagic == TOR_MAGIC_OVRD || torMagic == TOR_MAGIC_OVLY) ? 1 : l_num_variant;
443
444 if (i_dbgl > 1)
445 {
446@@ -154,19 +165,20 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section
447 (ring_id_list_common + i)->ringName, i, iVariant);
448 }
449
450- if ((strcmp( (ring_id_list_common + i)->ringName,
451- RING_PROPERTIES[i_ringId].iv_name) == 0)
452- && ( i_RingVariant == ring_variant_order->variant[iVariant]
453- || ( (i_RingVariant == OVERRIDE || i_RingVariant == OVERLAY) && i_magic == P9_XIP_MAGIC_SEEPROM)))
454+ if ( ( strcmp( (ring_id_list_common + i)->ringName,
455+ RING_PROPERTIES[i_ringId].iv_name) == 0 ) &&
456+ ( i_RingVariant == ring_variant_order->variant[iVariant] ||
457+ torMagic == TOR_MAGIC_OVRD ||
458+ torMagic == TOR_MAGIC_OVLY ) )
459 {
460 strcpy(o_ringName, RING_PROPERTIES[i_ringId].iv_name);
461-
462- acc_offset = dd_level_offset + ppe_offset + iCplt * sizeof(TorPpeBlock_t);
463+ acc_offset = dd_level_offset +
464+ ppe_cplt_offset +
465+ iCplt * sizeof(TorPpeBlock_t);
466 cplt_offset = *(uint32_t*)( (uint8_t*)i_ringSection +
467 acc_offset );
468 cplt_offset = be32toh(cplt_offset);
469-
470- acc_offset = dd_level_offset + ppe_offset + cplt_offset;
471+ acc_offset = dd_level_offset + ppe_cplt_offset + cplt_offset;
472 ring_offset = *(uint16_t*)( (uint8_t*)i_ringSection +
473 acc_offset +
474 tor_slot_no * sizeof(ring_offset) );
475@@ -175,7 +187,7 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section
476 if (i_RingBlockType == GET_SINGLE_RING)
477 {
478 acc_offset = dd_level_offset +
479- ppe_offset +
480+ ppe_cplt_offset +
481 cplt_offset +
482 ring_offset;
483 ring_size = be16toh( ((CompressedScanData*)
484@@ -233,7 +245,7 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section
485 " Chiplet section's offset to RS4 header = 0x%08x \n"
486 " Full offset to RS4 header = 0x%08x \n"
487 " Ring size = 0x%08x \n",
488- i, dd_level_offset, ppe_offset, cplt_offset, ring_offset, acc_offset, ring_size);
489+ i, dd_level_offset, ppe_cplt_offset, cplt_offset, ring_offset, acc_offset, ring_size);
490 }
491
492 return rc;
493@@ -296,14 +308,16 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section
494 strcpy(o_ringName, RING_PROPERTIES[i_ringId].iv_name);
495
496 acc_offset = dd_level_offset +
497- ppe_offset +
498+ ppe_cplt_offset +
499 iCplt * sizeof(TorPpeBlock_t) +
500 sizeof(cplt_offset); // Jump to instance offset
501 cplt_offset = *(uint32_t*)( (uint8_t*)i_ringSection +
502 acc_offset );
503 cplt_offset = be32toh(cplt_offset);
504
505- acc_offset = cplt_offset + dd_level_offset + ppe_offset;
506+ acc_offset = cplt_offset +
507+ dd_level_offset +
508+ ppe_cplt_offset;
509 ring_offset = *(uint16_t*)( (uint8_t*)i_ringSection +
510 acc_offset +
511 tor_slot_no * sizeof(ring_offset) );
512@@ -312,7 +326,7 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section
513 if (i_RingBlockType == GET_SINGLE_RING)
514 {
515 acc_offset = dd_level_offset +
516- ppe_offset +
517+ ppe_cplt_offset +
518 cplt_offset +
519 ring_offset;
520 ring_size = be16toh( ((CompressedScanData*)
521@@ -376,7 +390,7 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section
522 " Chiplet section's offset to RS4 header = 0x%08x \n"
523 " Full offset to RS4 header = 0x%08x \n"
524 " Ring size = 0x%08x \n",
525- i, dd_level_offset, ppe_offset, cplt_offset, ring_offset, acc_offset, ring_size);
526+ i, dd_level_offset, ppe_cplt_offset, cplt_offset, ring_offset, acc_offset, ring_size);
527 }
528
529 return rc;
530@@ -441,7 +455,6 @@ int get_ring_from_sbe_image( void* i_ringSection, // Ring section
531 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
532 static
533 int get_ring_from_sgpe_image ( void* i_ringSection, // Ring section ptr
534- uint64_t i_magic, // Image Magic Number
535 RingID i_ringId, // Ring ID
536 uint16_t i_ddLevelOffset, // DD level offset
537 RingType_t& io_RingType, // Common, Instance
538@@ -453,24 +466,42 @@ int get_ring_from_sgpe_image ( void* i_ringSection, // Ring sectio
539 char* o_ringName, // Name of ring
540 uint32_t i_dbgl ) // Debug option
541 {
542+ uint32_t torMagic;
543 uint32_t acc_offset = 0; // Accumulating offset to next TOR offset slot
544 uint32_t ring_offset = 0;
545 uint16_t chiplet_offset = 0;
546 uint32_t ringSize = 0;
547 int temp = (i_ddLevelOffset >> 2) + 4; // converting byte to word counter
548 uint32_t spge_offset = 0;
549+ uint32_t ppe_cplt_offset = 0; // Local offset to where the pool of chiplets starts
550+
551+ torMagic = be32toh( ((TorHeader_t*)i_ringSection)->magic );
552
553- if (i_magic == P9_XIP_MAGIC_HW)
554+ // Calculate the offset (wrt start of ringSection) to the SGPE PPE
555+ // ring section. This offset, inappropriately denoted "temp" here
556+ // but which needs to be renamed to "ppe_offset" asap, will point
557+ // to the TORG header of the SGPE PPE ring section.
558+ if (torMagic == TOR_MAGIC_HW)
559 {
560 spge_offset = *((uint32_t*)i_ringSection + temp); //DD level offset index
561 temp = be32toh(spge_offset);
562 }
563- else if (i_magic == P9_XIP_MAGIC_SGPE)
564+ else if (torMagic == TOR_MAGIC_SGPE)
565 {
566 spge_offset = 0;
567 i_ddLevelOffset = 0;
568 temp = be32toh(spge_offset);
569 }
570+ else
571+ {
572+ MY_ERR("torMagic=0x%08x is not valid for SGPE\n", torMagic);
573+ return TOR_INVALID_MAGIC_NUMBER;
574+ }
575+
576+ // Calculate the offset (wrt start of ringSection) to where the
577+ // pool of chiplet offsets begins in the SGPE PPE ring section,
578+ // which is right after the TORG header.
579+ ppe_cplt_offset = temp + sizeof(TorHeader_t);
580
581 GenRingIdList* ring_id_list_common = NULL;
582 GenRingIdList* ring_id_list_instance = NULL;
583@@ -494,18 +525,18 @@ int get_ring_from_sgpe_image ( void* i_ringSection, // Ring sectio
584 RING_PROPERTIES[i_ringId].iv_name) == 0) && ( i_RingVariant == j ))
585 {
586 strcpy(o_ringName, RING_PROPERTIES[i_ringId].iv_name);
587- uint32_t var = 0 + i_ddLevelOffset + temp;
588+ uint32_t var = 0 + i_ddLevelOffset + ppe_cplt_offset;
589 int temp1 = var / sizeof(uint32_t);
590 ring_offset = *((uint32_t*)i_ringSection + temp1);
591 ring_offset = be32toh(ring_offset);
592- var = ring_offset + i_ddLevelOffset + temp;
593+ var = ring_offset + i_ddLevelOffset + ppe_cplt_offset;
594 temp1 = var / sizeof(uint16_t) + local;
595 chiplet_offset = *((uint16_t*)i_ringSection + temp1);
596 chiplet_offset = be16toh(chiplet_offset);
597
598 if (i_RingBlockType == GET_SINGLE_RING)
599 {
600- var = ring_offset + chiplet_offset + i_ddLevelOffset + temp;
601+ var = ring_offset + chiplet_offset + i_ddLevelOffset + ppe_cplt_offset;
602 ringSize = be16toh( ((CompressedScanData*)
603 ((uint8_t*)i_ringSection +
604 var))->iv_size );
605@@ -545,7 +576,7 @@ int get_ring_from_sgpe_image ( void* i_ringSection, // Ring sectio
606 {
607 MY_INF(" Hex details (SGPE): Chiplet #%d offset 0x%08x local offset 0x%08x " \
608 "ring offset 0x%08x start adr 0x%08x ringSize=0x%08x \n",
609- i, var, temp, ring_offset, chiplet_offset, ringSize);
610+ i, var, ppe_cplt_offset, ring_offset, chiplet_offset, ringSize);
611 }
612
613 return TOR_RING_FOUND;
614@@ -611,18 +642,18 @@ int get_ring_from_sgpe_image ( void* i_ringSection, // Ring sectio
615 if ( i == io_instanceId && k == i_RingVariant )
616 {
617 strcpy(o_ringName, RING_PROPERTIES[i_ringId].iv_name);
618- uint32_t var = CPLT_OFFSET_SIZE + i_ddLevelOffset + temp;
619+ uint32_t var = CPLT_OFFSET_SIZE + i_ddLevelOffset + ppe_cplt_offset;
620 int temp1 = var / sizeof(uint32_t);
621 ring_offset = *((uint32_t*)i_ringSection + temp1);
622 ring_offset = be32toh(ring_offset);
623- var = ring_offset + i_ddLevelOffset + temp;
624+ var = ring_offset + i_ddLevelOffset + ppe_cplt_offset;
625 temp1 = var / sizeof(uint16_t) + local;
626 chiplet_offset = *((uint16_t*)i_ringSection + temp1);
627 chiplet_offset = be16toh(chiplet_offset);
628
629 if (i_RingBlockType == GET_SINGLE_RING)
630 {
631- var = ring_offset + chiplet_offset + i_ddLevelOffset + temp;
632+ var = ring_offset + chiplet_offset + i_ddLevelOffset + ppe_cplt_offset;
633 ringSize = be16toh( ((CompressedScanData*)
634 ((uint8_t*)i_ringSection +
635 var))->iv_size );
636@@ -667,7 +698,7 @@ int get_ring_from_sgpe_image ( void* i_ringSection, // Ring sectio
637 {
638 MY_INF(" Hex details (SGPE): Chiplet #%d offset 0x%08x local offset 0x%08x " \
639 "ring offset 0x%08x start adr 0x%08x ringSize=0x%08x \n",
640- i, var, temp, ring_offset, chiplet_offset, ringSize);
641+ i, var, ppe_cplt_offset, ring_offset, chiplet_offset, ringSize);
642 }
643
644 return TOR_RING_FOUND;
645@@ -735,7 +766,6 @@ int get_ring_from_sgpe_image ( void* i_ringSection, // Ring sectio
646 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////
647 static
648 int get_ring_from_cme_image ( void* i_ringSection, // Ring section ptr
649- uint64_t i_magic, // Image Magic Number
650 RingID i_ringId, // Ring ID
651 uint16_t i_ddLevelOffset, // DD level offset
652 RingType_t& io_RingType, // Common, Instance
653@@ -747,24 +777,38 @@ int get_ring_from_cme_image ( void* i_ringSection, // Ring section
654 char* o_ringName, // Name of ring
655 uint32_t i_dbgl ) // Debug option
656 {
657+ uint32_t torMagic;
658 uint32_t acc_offset = 0; // Accumulating offset to next TOR offset slot
659 uint32_t ring_offset = 0;
660 uint16_t chiplet_offset = 0;
661 uint32_t ringSize = 0;
662 int temp = (i_ddLevelOffset >> 2) + 2; // converting byte to word counter
663 uint32_t cme_offset = 0;
664+ uint32_t ppe_cplt_offset = 0; // Local offset to where the pool of chiplets starts
665
666- if (i_magic == P9_XIP_MAGIC_HW)
667+ torMagic = be32toh( ((TorHeader_t*)i_ringSection)->magic );
668+
669+ if (torMagic == TOR_MAGIC_HW)
670 {
671 cme_offset = *((uint32_t*)i_ringSection + temp); //DD level offset index
672 temp = be32toh(cme_offset);
673 }
674- else if (i_magic == P9_XIP_MAGIC_CME)
675+ else if (torMagic == TOR_MAGIC_CME)
676 {
677 cme_offset = 0;
678 i_ddLevelOffset = 0;
679 temp = be32toh(cme_offset);
680 }
681+ else
682+ {
683+ MY_ERR("torMagic=0x%08x is not valid for CME\n", torMagic);
684+ return TOR_INVALID_MAGIC_NUMBER;
685+ }
686+
687+ // Calculate the offset (wrt start of ringSection) to where the
688+ // pool of chiplet offsets begins in the CME PPE ring section,
689+ // which is right after the TORC header.
690+ ppe_cplt_offset = temp + sizeof(TorHeader_t);
691
692 GenRingIdList* ring_id_list_common = NULL;
693 GenRingIdList* ring_id_list_instance = NULL;
694@@ -788,18 +832,18 @@ int get_ring_from_cme_image ( void* i_ringSection, // Ring section
695 RING_PROPERTIES[i_ringId].iv_name) == 0) && ( i_RingVariant == j ))
696 {
697 strcpy(o_ringName, RING_PROPERTIES[i_ringId].iv_name);
698- uint32_t var = 0 + i_ddLevelOffset + temp;
699+ uint32_t var = 0 + i_ddLevelOffset + ppe_cplt_offset;
700 int temp1 = var / sizeof(uint32_t);
701 ring_offset = *((uint32_t*)i_ringSection + temp1);
702 ring_offset = be32toh(ring_offset);
703- var = ring_offset + i_ddLevelOffset + temp;
704+ var = ring_offset + i_ddLevelOffset + ppe_cplt_offset;
705 temp1 = var / sizeof(uint16_t) + local;
706 chiplet_offset = *((uint16_t*)i_ringSection + temp1);
707 chiplet_offset = be16toh(chiplet_offset);
708
709 if (i_RingBlockType == GET_SINGLE_RING)
710 {
711- var = ring_offset + chiplet_offset + i_ddLevelOffset + temp;
712+ var = ring_offset + chiplet_offset + i_ddLevelOffset + ppe_cplt_offset;
713 ringSize = be16toh( ((CompressedScanData*)
714 ((uint8_t*)i_ringSection +
715 var))->iv_size );
716@@ -839,7 +883,7 @@ int get_ring_from_cme_image ( void* i_ringSection, // Ring section
717 {
718 MY_INF(" Hex details (CME): Chiplet #%d offset 0x%08x local offset 0x%08x " \
719 "ring offset 0x%08x start adr 0x%08x ringSize=0x%08x \n",
720- i, var, temp, ring_offset, chiplet_offset, ringSize);
721+ i, var, ppe_cplt_offset, ring_offset, chiplet_offset, ringSize);
722 }
723
724 return TOR_RING_FOUND;
725@@ -905,18 +949,18 @@ int get_ring_from_cme_image ( void* i_ringSection, // Ring section
726 if ( i == io_instanceId && k == i_RingVariant )
727 {
728 strcpy(o_ringName, RING_PROPERTIES[i_ringId].iv_name);
729- uint32_t var = CPLT_OFFSET_SIZE + i_ddLevelOffset + temp;
730+ uint32_t var = i_ddLevelOffset + ppe_cplt_offset + CPLT_OFFSET_SIZE;
731 int temp1 = var / CPLT_OFFSET_SIZE;
732 ring_offset = *((uint32_t*)i_ringSection + temp1);
733 ring_offset = be32toh(ring_offset);
734- var = ring_offset + i_ddLevelOffset + temp;
735+ var = ring_offset + i_ddLevelOffset + ppe_cplt_offset;
736 temp1 = var / sizeof(uint16_t) + local;
737 chiplet_offset = *((uint16_t*)i_ringSection + temp1);
738 chiplet_offset = be16toh(chiplet_offset);
739
740 if (i_RingBlockType == GET_SINGLE_RING)
741 {
742- var = ring_offset + chiplet_offset + i_ddLevelOffset + temp;
743+ var = ring_offset + chiplet_offset + i_ddLevelOffset + ppe_cplt_offset;
744 ringSize = be16toh( ((CompressedScanData*)
745 ((uint8_t*)i_ringSection +
746 var))->iv_size );
747@@ -947,7 +991,7 @@ int get_ring_from_cme_image ( void* i_ringSection, // Ring section
748 {
749 MY_INF(" Hex details (CME): Chiplet #%d offset 0x%08x local offset 0x%08x " \
750 "ring offset 0x%08x start adr 0x%08x ringSize=0x%08x \n",
751- i, var, temp, ring_offset, chiplet_offset, ringSize);
752+ i, var, ppe_cplt_offset, ring_offset, chiplet_offset, ringSize);
753 }
754
755 memcpy( (uint8_t*)(*io_ringBlockPtr), (uint8_t*)i_ringSection + var,
756@@ -960,14 +1004,6 @@ int get_ring_from_cme_image ( void* i_ringSection, // Ring section
757 MY_INF(" After get_ring_from_cme_image Size %d \n", io_ringBlockSize);
758 }
759
760- if (i_dbgl > 1)
761- {
762- MY_INF(" 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x \n",
763- var, temp, ring_offset, chiplet_offset, ringSize);
764- MY_INF("Chiplet %d ChipletRing TOR offset %d %d Size %d %d \t\n",
765- i, ring_offset, chiplet_offset, ringSize, temp);
766- }
767-
768 return TOR_RING_FOUND;
769 }
770 else
771@@ -986,6 +1022,7 @@ int get_ring_from_cme_image ( void* i_ringSection, // Ring section
772 if (chiplet_offset)
773 {
774 MY_ERR("Ring container is already present in the CME section \n");
775+
776 return TOR_RING_AVAILABLE_IN_RINGSECTION;
777 }
778
779@@ -1032,7 +1069,6 @@ int get_ring_from_cme_image ( void* i_ringSection, // Ring section
780 ///
781 //////////////////////////////////////////////////////////////////////////////////////////
782 int tor_access_ring( void* i_ringSection, // Ring section ptr
783- uint64_t i_magic, // Image Magic Number
784 RingID i_ringId, // Ring ID
785 uint16_t i_ddLevel, // DD level
786 PpeType_t i_PpeType, // SBE, CME, SGPE
787@@ -1046,12 +1082,15 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
788 uint32_t i_dbgl ) // Debug option
789 {
790 int rc = 0;
791+ uint32_t torMagic;
792+ TorHeader_t* torHeader;
793+ TorDdBlock_t* torDdBlock;
794 uint8_t bDdCheck = 0;
795 uint32_t ddLevelOffset = 0;
796 uint32_t ddLevelCount = 0;
797 uint32_t ddLevel = 0;
798 uint32_t ddBlockSize = 0;
799- uint32_t temp = 0, local = 0;
800+ uint32_t temp = 0;
801
802
803 if (i_dbgl > 1)
804@@ -1059,10 +1098,12 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
805 MY_INF("Entering tor_access_ring()... \n");
806 }
807
808- if (i_magic == P9_XIP_MAGIC_HW)
809+ torHeader = (TorHeader_t*)i_ringSection;
810+ torMagic = be32toh(torHeader->magic);
811+
812+ if (torMagic == TOR_MAGIC_HW)
813 {
814- ddLevelCount = *((uint32_t*)i_ringSection + 0);
815- ddLevelCount = be32toh(ddLevelCount);
816+ ddLevelCount = torHeader->numDdLevels;
817
818 if (ddLevelCount > MAX_NOOF_DD_LEVELS_IN_IMAGE)
819 {
820@@ -1078,14 +1119,14 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
821 MY_INF("tor_access_ring(): No of DD levels: %d \n", ddLevelCount);
822 }
823
824- // start at one since we use that as an offset
825- for (uint8_t i = 1; i <= ddLevelCount; i++)
826+ for (uint8_t i = 0; i < ddLevelCount; i++)
827 {
828- local = 2 * i;
829- ddLevelOffset = *((uint32_t*)i_ringSection + local);
830-
831- ddLevel = be32toh(ddLevelOffset) >> 24 & 0x000000FF;
832- ddLevelOffset = be32toh(ddLevelOffset) & 0x00FFFFFF;
833+ torDdBlock = (TorDdBlock_t*)( (uint8_t*)torHeader +
834+ sizeof(TorHeader_t) +
835+ i * sizeof(TorDdBlock_t) );
836+ ddLevel = torDdBlock->ddLevel;
837+ // Local ddLevelOffset
838+ ddLevelOffset = be32toh(torDdBlock->offset);
839
840 if (i_dbgl > 1)
841 {
842@@ -1095,11 +1136,10 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
843
844 if ( ddLevel == i_ddLevel)
845 {
846- ddLevelOffset = ddLevelOffset + sizeof(TorNumDdLevels_t);
847- local = local + 1;
848- ddBlockSize = *((uint32_t*)i_ringSection + local);
849- ddBlockSize = be32toh(ddBlockSize);
850-
851+ // Convert to global ddLevelOffset
852+ ddLevelOffset = ddLevelOffset +
853+ sizeof(TorHeader_t);
854+ ddBlockSize = htobe32(torDdBlock->size);
855 bDdCheck = 1;
856 break;
857 }
858@@ -1115,7 +1155,9 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
859 return TOR_DD_LEVEL_NOT_FOUND;
860 }
861 }
862- else if ( i_magic == P9_XIP_MAGIC_SEEPROM)
863+ else if ( torMagic == TOR_MAGIC_SBE ||
864+ torMagic == TOR_MAGIC_OVRD ||
865+ torMagic == TOR_MAGIC_OVLY )
866 {
867 if ( i_PpeType == CME || i_PpeType == SGPE
868 || i_RingBlockType == GET_DD_LEVEL_RINGS
869@@ -1126,11 +1168,11 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
870 }
871 else
872 {
873- ddLevelOffset = 0;
874+ ddLevelOffset = sizeof(TorHeader_t);
875 ddBlockSize = 0;
876 }
877 }
878- else if ( i_magic == P9_XIP_MAGIC_CME)
879+ else if (torMagic == TOR_MAGIC_CME)
880 {
881 if ( i_PpeType == SBE || i_PpeType == SGPE
882 || i_RingBlockType == GET_DD_LEVEL_RINGS
883@@ -1141,11 +1183,11 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
884 }
885 else
886 {
887- ddLevelOffset = 0;
888+ ddLevelOffset = sizeof(TorHeader_t);
889 ddBlockSize = 0;
890 }
891 }
892- else if ( i_magic == P9_XIP_MAGIC_SGPE)
893+ else if (torMagic == TOR_MAGIC_SGPE)
894 {
895 if ( i_PpeType == SBE || i_PpeType == CME
896 || i_RingBlockType == GET_DD_LEVEL_RINGS
897@@ -1156,15 +1198,18 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
898 }
899 else
900 {
901- ddLevelOffset = 0;
902+ ddLevelOffset = sizeof(TorHeader_t);
903 ddBlockSize = 0;
904 }
905 }
906 else
907 {
908- MY_ERR("Magic number i_magic=0x%016lX\n is not valid.\n", (uintptr_t)i_magic);
909+ if (i_dbgl > 0)
910+ {
911+ MY_ERR("torMagic=0x%08x is not valid\n", torMagic);
912+ }
913
914- return TOR_AMBIGUOUS_API_PARMS;
915+ return TOR_INVALID_MAGIC_NUMBER;
916 }
917
918 if (i_RingBlockType == GET_DD_LEVEL_RINGS)
919@@ -1275,22 +1320,23 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
920 else if ( i_RingBlockType == GET_SINGLE_RING ||
921 i_RingBlockType == PUT_SINGLE_RING )
922 {
923- if (i_PpeType == SBE &&
924- ( i_magic == P9_XIP_MAGIC_HW ||
925- i_magic == P9_XIP_MAGIC_SEEPROM))
926+ if ( i_PpeType == SBE &&
927+ ( torMagic == TOR_MAGIC_HW ||
928+ torMagic == TOR_MAGIC_SBE ||
929+ torMagic == TOR_MAGIC_OVRD ||
930+ torMagic == TOR_MAGIC_OVLY ) )
931 {
932- rc = get_ring_from_sbe_image ( i_ringSection,
933- i_magic,
934- i_ringId,
935- ddLevelOffset,
936- io_RingType,
937- i_RingVariant,
938- io_instanceId,
939- i_RingBlockType,
940- io_ringBlockPtr,
941- io_ringBlockSize,
942- o_ringName,
943- i_dbgl);
944+ rc = get_ring_from_sbe_image( i_ringSection,
945+ i_ringId,
946+ ddLevelOffset,
947+ io_RingType,
948+ i_RingVariant,
949+ io_instanceId,
950+ i_RingBlockType,
951+ io_ringBlockPtr,
952+ io_ringBlockSize,
953+ o_ringName,
954+ i_dbgl );
955
956 if (rc)
957 {
958@@ -1312,22 +1358,21 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
959 return TOR_RING_BLOCKS_FOUND;
960 }
961 }
962- else if (i_PpeType == CME &&
963- ( i_magic == P9_XIP_MAGIC_HW ||
964- i_magic == P9_XIP_MAGIC_CME))
965+ else if ( i_PpeType == CME &&
966+ ( torMagic == TOR_MAGIC_HW ||
967+ torMagic == TOR_MAGIC_CME ) )
968 {
969- rc = get_ring_from_cme_image ( i_ringSection,
970- i_magic,
971- i_ringId,
972- ddLevelOffset,
973- io_RingType,
974- i_RingVariant,
975- io_instanceId,
976- i_RingBlockType,
977- io_ringBlockPtr,
978- io_ringBlockSize,
979- o_ringName,
980- i_dbgl);
981+ rc = get_ring_from_cme_image( i_ringSection,
982+ i_ringId,
983+ ddLevelOffset,
984+ io_RingType,
985+ i_RingVariant,
986+ io_instanceId,
987+ i_RingBlockType,
988+ io_ringBlockPtr,
989+ io_ringBlockSize,
990+ o_ringName,
991+ i_dbgl );
992
993 if (rc == TOR_RING_NOT_FOUND)
994 {
995@@ -1379,22 +1424,21 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
996 return TOR_RING_BLOCKS_FOUND;
997 }
998 }
999- else if (i_PpeType == SGPE &&
1000- ( i_magic == P9_XIP_MAGIC_HW ||
1001- i_magic == P9_XIP_MAGIC_SGPE))
1002+ else if ( i_PpeType == SGPE &&
1003+ ( torMagic == TOR_MAGIC_HW ||
1004+ torMagic == TOR_MAGIC_SGPE ) )
1005 {
1006- rc = get_ring_from_sgpe_image ( i_ringSection,
1007- i_magic,
1008- i_ringId,
1009- ddLevelOffset,
1010- io_RingType,
1011- i_RingVariant,
1012- io_instanceId,
1013- i_RingBlockType,
1014- io_ringBlockPtr,
1015- io_ringBlockSize,
1016- o_ringName,
1017- i_dbgl);
1018+ rc = get_ring_from_sgpe_image( i_ringSection,
1019+ i_ringId,
1020+ ddLevelOffset,
1021+ io_RingType,
1022+ i_RingVariant,
1023+ io_instanceId,
1024+ i_RingBlockType,
1025+ io_ringBlockPtr,
1026+ io_ringBlockSize,
1027+ o_ringName,
1028+ i_dbgl );
1029
1030 if (rc == TOR_RING_NOT_FOUND)
1031 {
1032@@ -1448,10 +1492,11 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
1033 }
1034 else
1035 {
1036- MY_ERR("\t Code bug: We are unpreparred for this input parm combination: \n"
1037- "\t i_PpeType=%d\n"
1038- "\t i_magic=0x%016lX\n",
1039- i_PpeType, (uintptr_t)i_magic);
1040+ if (i_dbgl > 0)
1041+ {
1042+ MY_ERR("\t Unsupported combination of i_PpeType=%d and torMagic=0x%08x\n",
1043+ i_PpeType, torMagic);
1044+ }
1045
1046 return TOR_AMBIGUOUS_API_PARMS;
1047 }
1048@@ -1466,7 +1511,8 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
1049 }
1050
1051 return TOR_AMBIGUOUS_API_PARMS;
1052-}
1053+
1054+} // End of tor_access_ring()
1055
1056
1057
1058@@ -1476,7 +1522,6 @@ int tor_access_ring( void* i_ringSection, // Ring section ptr
1059 //
1060 /////////////////////////////////////////////////////////////////////////////////////
1061 int tor_get_single_ring ( void* i_ringSection, // Ring section ptr
1062- uint64_t i_magic, // Image Magic Number
1063 uint16_t i_ddLevel, // DD level
1064 RingID i_ringId, // Ring ID
1065 PpeType_t i_PpeType, // SBE, CME, SGPE
1066@@ -1489,7 +1534,7 @@ int tor_get_single_ring ( void* i_ringSection, // Ring section ptr
1067
1068 uint32_t rc;
1069 char i_ringName[25];
1070- uint8_t l_instanceId = i_instanceId;
1071+ //@FIXME: This should really be ALLRING. But it's not used as input.
1072 RingType_t l_ringType;
1073 l_ringType = COMMON;
1074
1075@@ -1499,13 +1544,12 @@ int tor_get_single_ring ( void* i_ringSection, // Ring section ptr
1076 }
1077
1078 rc = tor_access_ring( i_ringSection,
1079- i_magic,
1080 i_ringId,
1081 i_ddLevel,
1082 i_PpeType,
1083 l_ringType,
1084 i_RingVariant,
1085- l_instanceId,
1086+ i_instanceId,
1087 GET_SINGLE_RING,
1088 io_ringBlockPtr,
1089 io_ringBlockSize,
1090@@ -1531,7 +1575,7 @@ int tor_get_single_ring ( void* i_ringSection, // Ring section ptr
1091 int tor_get_block_of_rings ( void* i_ringSection, // Ring section ptr
1092 uint16_t i_ddLevel, // DD level
1093 PpeType_t i_PpeType, // SBE,CME,SGPE
1094- RingType_t i_RingType, // Common, Instance
1095+ RingType_t i_ringType, // Common, Instance
1096 RingVariant_t i_RingVariant, // Base,CC, RL, Ovrd, Ovly
1097 uint8_t i_instanceId, // Instance ID
1098 void** io_ringBlockPtr, // Output ring buffer
1099@@ -1545,20 +1589,17 @@ int tor_get_block_of_rings ( void* i_ringSection, // Ring section
1100
1101 uint32_t rc = 0;
1102 char i_ringName[25];
1103- uint8_t l_instanceId = i_instanceId;
1104- RingType_t l_ringType = i_RingType;
1105
1106- if (l_ringType == ALLRING && i_PpeType != NUM_PPE_TYPES)
1107+ if (i_ringType == ALLRING && i_PpeType != NUM_PPE_TYPES)
1108 {
1109 // Get block of rings specific to a PPE type
1110 rc = tor_access_ring( i_ringSection,
1111- P9_XIP_MAGIC_HW,
1112 NUM_RING_IDS,
1113 i_ddLevel,
1114 i_PpeType,
1115- l_ringType,
1116+ i_ringType,
1117 i_RingVariant,
1118- l_instanceId,
1119+ i_instanceId,
1120 GET_PPE_LEVEL_RINGS,
1121 io_ringBlockPtr,
1122 io_ringBlockSize,
1123@@ -1566,17 +1607,16 @@ int tor_get_block_of_rings ( void* i_ringSection, // Ring section
1124 i_dbgl );
1125
1126 }
1127- else if (l_ringType == ALLRING && i_PpeType == NUM_PPE_TYPES)
1128+ else if (i_ringType == ALLRING && i_PpeType == NUM_PPE_TYPES)
1129 {
1130 // Get DD level block of rings
1131 rc = tor_access_ring( i_ringSection,
1132- P9_XIP_MAGIC_HW,
1133 NUM_RING_IDS,
1134 i_ddLevel,
1135 i_PpeType,
1136- l_ringType,
1137+ i_ringType,
1138 i_RingVariant,
1139- l_instanceId,
1140+ i_instanceId,
1141 GET_DD_LEVEL_RINGS,
1142 io_ringBlockPtr,
1143 io_ringBlockSize,
1144@@ -1622,39 +1662,17 @@ int tor_append_ring( void* i_ringSection, // Ring section ptr
1145 char i_ringName[25];
1146 uint32_t l_buf = 0;
1147 uint32_t* l_cpltSection = &l_buf;
1148- uint8_t l_instanceId = i_instanceId;
1149- RingType_t l_RingType = i_RingType;
1150 uint32_t l_ringBlockSize;
1151 uint16_t l_ringOffset16;
1152- uint64_t l_magic;
1153 uint32_t l_torOffsetSlot;
1154
1155- if (i_PpeType == SBE) // Assign i_magic variant as SBE image
1156- {
1157- l_magic = P9_XIP_MAGIC_SEEPROM;
1158- }
1159- else if (i_PpeType == CME) // Assign i_magic variant as CME image
1160- {
1161- l_magic = P9_XIP_MAGIC_CME;
1162- }
1163- else if (i_PpeType == SGPE) // Assign i_magic variant as SGPE image
1164- {
1165- l_magic = P9_XIP_MAGIC_SGPE;
1166- }
1167- else
1168- {
1169- MY_ERR("PPE type (i_PpeType=%d) is not supported \n", i_PpeType);
1170- return TOR_AMBIGUOUS_API_PARMS;
1171- }
1172-
1173 rc = tor_access_ring( i_ringSection,
1174- l_magic,
1175 i_ringId,
1176 0x00,
1177 i_PpeType,
1178- l_RingType,
1179+ i_RingType,
1180 i_RingVariant,
1181- l_instanceId,
1182+ i_instanceId,
1183 PUT_SINGLE_RING,
1184 (void**)&l_cpltSection, // On return, contains offset (wrt ringSection) of
1185 // chiplet section's common or instance section
1186@@ -1665,7 +1683,11 @@ int tor_append_ring( void* i_ringSection, // Ring section ptr
1187
1188 if (rc)
1189 {
1190- MY_ERR("tor_access_ring() failed w/rc=0x%x \n", rc);
1191+ if (i_dbgl > 0)
1192+ {
1193+ MY_ERR("tor_append_ring() failed in call to tor_access_ring w/rc=0x%x \n", rc);
1194+ }
1195+
1196 return rc;
1197 }
1198
1199@@ -1700,6 +1722,10 @@ int tor_append_ring( void* i_ringSection, // Ring section ptr
1200 // Update the ringSectionSize
1201 io_ringSectionSize += l_ringBlockSize;
1202
1203+ // Update also the size in the TOR header
1204+ TorHeader_t* torHeader = (TorHeader_t*)i_ringSection;
1205+ torHeader->size = htobe32(be32toh(torHeader->size) + l_ringBlockSize);
1206+
1207 return TOR_SUCCESS;
1208 }
1209
1210diff --git a/src/import/chips/p9/utils/imageProcs/p9_tor.H b/src/import/chips/p9/utils/imageProcs/p9_tor.H
1211index 94b5274..cc8f15a 100644
1212--- a/src/import/chips/p9/utils/imageProcs/p9_tor.H
1213+++ b/src/import/chips/p9/utils/imageProcs/p9_tor.H
1214@@ -25,7 +25,6 @@
1215 #ifndef _P9_TOR_H_
1216 #define _P9_TOR_H_
1217
1218-#include "p9_ring_id.h"
1219 #include "p9_ringId.H"
1220
1221 #define MAX_TOR_RING_OFFSET (256*256-1) // Max value of 2Byte uint
1222@@ -36,7 +35,7 @@ namespace P9_TOR
1223 extern const char* ppeTypeName[];
1224 extern const char* ringVariantName[];
1225
1226-#define TOR_VERSION 2
1227+#define TOR_VERSION 3
1228
1229 //
1230 // TOR Magic values for top-level TOR image and TOR sub-images
1231@@ -53,7 +52,34 @@ enum TorMagicNum
1232 TOR_MAGIC_CEN = (uint32_t)0x544F524E, // "TORN"
1233 };
1234
1235+//
1236+// Chip types to represent p9n, p9c, centaur
1237+//
1238+enum ChipType
1239+{
1240+ CT_P9N,
1241+ CT_P9C,
1242+ CT_CEN,
1243+ NUM_CHIP_TYPES
1244+};
1245+
1246 typedef uint8_t ChipType_t;
1247+const ChipType_t INVALID_CHIP_TYPE = 0xff;
1248+
1249+typedef struct ChipTypeList
1250+{
1251+ const char* name;
1252+ ChipType_t type;
1253+} ChipTypeList_t;
1254+
1255+const ChipTypeList_t CHIP_TYPE_LIST[] =
1256+{
1257+ {"p9n", CT_P9N},
1258+ {"p9c", CT_P9C},
1259+ {"cen", CT_CEN},
1260+};
1261+
1262+
1263
1264 //
1265 // TOR header field (appears in top of every HW, SBE, CEN, OVRD, etc ring section)
1266@@ -65,26 +91,26 @@ typedef struct
1267 ChipType_t chipType; // Value from ChipType enum
1268 uint8_t ddLevel; // =0xff if MAGIC_HW, >0 all other MAGICs
1269 uint8_t numDdLevels; // >0 if MAGIC_HW, =1 all other MAGICs
1270- uint32_t size; // Size of the TOR ringSection.
1271+ uint32_t size; // A place holder for now, but will be used in a later commit.
1272 } TorHeader_t;
1273
1274+#define UNDEFINED_DD_LEVEL (uint8_t)0xff
1275
1276+//
1277+// Subsequent TOR fields (listed in order they appear in TOR for easier understanding)
1278+//
1279 typedef struct
1280 {
1281- uint32_t TorNumDdLevels;
1282- uint32_t reserved;
1283-} TorNumDdLevels_t;
1284-
1285-typedef struct
1286-{
1287- uint32_t TorDdLevelAndOffset;
1288- uint32_t TorDdBlockSize;
1289-} TorDdLevelBlock_t;
1290+ uint32_t offset;
1291+ uint32_t size;
1292+ uint8_t ddLevel;
1293+ uint8_t reserved[3];
1294+} TorDdBlock_t;
1295
1296 typedef struct
1297 {
1298- uint32_t TorPpeTypeOffset;
1299- uint32_t TorPpeBlockSize;
1300+ uint32_t offset;
1301+ uint32_t size;
1302 } TorPpeBlock_t;
1303
1304 typedef struct
1305@@ -95,6 +121,13 @@ typedef struct
1306
1307 typedef uint16_t TorRingOffset_t; // Ring offset value in TOR offset slot
1308
1309+//@FIXME Discard asap
1310+typedef enum TorOffsetSize
1311+{
1312+ RING_OFFSET_SIZE = 2,
1313+ CPLT_OFFSET_SIZE = 4
1314+} TorOffsetSize_t;
1315+
1316 #define TOR_SUCCESS 0
1317 #define TOR_RING_FOUND 0
1318 #define TOR_RING_BLOCKS_FOUND 0
1319@@ -117,6 +150,7 @@ typedef uint16_t TorRingOffset_t; // Ring offset value in TOR offset slot
1320 #define TOR_BUFFER_TOO_SMALL 17
1321 #define TOR_TOO_MANY_DD_LEVELS 18
1322 #define TOR_OFFSET_TOO_BIG 19
1323+#define TOR_INVALID_VARIANT 20
1324
1325 // Different options to extract data using tor_access_ring API
1326 typedef enum RingBlockType
1327@@ -142,12 +176,6 @@ typedef enum PpeType
1328 NUM_PPE_TYPES = 0x03
1329 } PpeType_t;
1330
1331-typedef enum TorOffsetSize
1332-{
1333- RING_OFFSET_SIZE = 2,
1334- CPLT_OFFSET_SIZE = 4
1335-} TorOffsetSize_t;
1336-
1337 ///
1338 /// ****************************************************************************
1339 /// Function declares.
1340@@ -161,9 +189,6 @@ typedef enum TorOffsetSize
1341 /// TOR API supports two type of binary image. 1) HW image format and 2)
1342 /// SEEPROM image format binary
1343 ///
1344-/// \param[in] i_magic A uint64_t variable to indicate XIP image format
1345-/// ring section passed
1346-///
1347 /// \param[in] i_ringId A enum to indicate unique ID for the ring
1348 ///
1349 /// \param[in] i_ddLevel A variable to indicate chip DD level. TOR API
1350@@ -211,8 +236,7 @@ typedef enum TorOffsetSize
1351 /// and the following n number of operation based on the call.
1352 ///
1353 /// GET_SINGLE_RING (\a i_ringVariant) - traverse on \a i_ringSection buffer
1354-/// based on the following input param \a i_magic which gives details of image
1355-/// type, \a i_ringId which gives ring info, \a i_ddLevel which gives dd spec
1356+/// based on \a i_ringId which gives ring info, \a i_ddLevel which gives dd spec
1357 /// (Used only for HW image/optional for other image) i_ppeType which gives ppe
1358 /// type info, \a i_ringVarint gives ring variant info and \a io_instance which
1359 /// gives chiplet instance specific while accessing instance specific ring and
1360@@ -222,33 +246,29 @@ typedef enum TorOffsetSize
1361 /// data copied into io_ringBlockPtr. \a o_ringName returns ring string name.
1362 ///
1363 /// GET_DD_LEVEL_RINGS (\a i_ringVariant) - traverse on \a i_ringSection
1364-/// buffer based on the following input param \a i_magic which gives details
1365-/// of image type and \a i_ddLevel which gives dd spec(Used only for HW image
1366+/// buffer based on \a i_ddLevel which gives dd spec (used only for HW image
1367 /// /optional for other image) On return, \a io_ringBlockPtr contains DD level
1368 /// specific ring section and \a io_ringBlockSize contains size of the data
1369 /// copied into io_ringBlockPtr. \a Other params are optional.
1370 /// This ringVariant works on HW image.
1371 ///
1372 /// GET_PPE_LEVEL_RINGS (\a i_ringVariant) - traverse on \a i_ringSection
1373-/// buffer based on the following input param \a i_magic which gives the detail
1374-/// of image type, i_ppeType which gives ppe type info and \a i_ddLevel which
1375-/// gives dd spec(Used only for HW image/optional for other image) On return,
1376+/// buffer based on \a i_ppeType which gives ppe type info and \a i_ddLevel which
1377+/// gives dd spec used only for HW image/optional for other image) On return,
1378 /// \a io_ringBlockPtr contains PPE type specific ring section and
1379 /// \a io_ringBlockSize contains size of the data copied into io_ringBlockPtr.
1380 /// \a Other params are optional. This ringVariant works on HW image.
1381 ///
1382 /// GET_CPLT_LEVEL_RINGS (\a i_ringVariant) - traverse on \a i_ringSection
1383-/// buffer based on the following input param \a i_magic which gives the detail
1384-/// of image type, i_ppeType which gives ppe type info, \a i_ddLevel which gives
1385-/// dd spec(Used only for HW image/optional for other image) and \a io_RingType
1386+/// buffer based on \a i_ppeType which gives ppe type info, \a i_ddLevel which gives
1387+/// dd spec (used only for HW image/optional for other image) and \a io_RingType
1388 /// which gives ring type info. On return, \a io_ringBlockPtr contains chiplet
1389 /// specific ring type ring section and \a io_ringBlockSize contains size of
1390 /// the data copied into io_ringBlockPtr. \a Other params are optional.
1391 ///
1392 /// PUT_SINGLE_RING (\a i_ringVariant) - traverse on \a i_ringSection buffer
1393-/// based on the following input param \a i_magic which gives detail of image
1394-/// type, \a i_ringId which gives ring info, \a i_ddLevel which gives dd spec
1395-/// (Used only for HW image/optional for other image), i_ppeType which gives
1396+/// based on \a i_ringId which gives ring info, \a i_ddLevel which gives dd spec
1397+/// (used only for HW image/optional for other image), i_ppeType which gives
1398 /// ppe type info, \a i_ringVarint gives ring variant info and \a io_instance
1399 /// which gives chiplet instance specific while accessing instance specific
1400 /// ring and returns chiplet number while accessing common ring. On return,
1401@@ -261,7 +281,6 @@ typedef enum TorOffsetSize
1402 ///
1403 /// \retval non-0 See \ref TOR API RETURN errors
1404 int tor_access_ring( void* i_ringSection, // Ring address Ptr any of .rings, .overrides and .overlays.
1405- uint64_t i_magic, // Image Magic Number
1406 RingID i_ringId, // Unique ring ID
1407 uint16_t i_ddLevel, // DD level info
1408 PpeType_t i_PpeType, // PPE type : SBE, CME, etc
1409@@ -282,9 +301,6 @@ int tor_access_ring( void* i_ringSection, // Ring address Ptr any of .
1410 /// It contain details of p9 Ring which is used for scanning operation.
1411 /// TOR API supports HW image format only
1412 ///
1413-/// \param[in] i_magic A uint64_t variable to indicate XIP image format
1414-/// ring section passed
1415-///
1416 /// \param[in] i_ringId A enum to indicate unique ID for the ring
1417 ///
1418 /// \param[in] i_ddLevel A variable to indicate chip DD level. TOR API
1419@@ -316,7 +332,6 @@ int tor_access_ring( void* i_ringSection, // Ring address Ptr any of .
1420 ///
1421 /// \retval non-0 See \ref TOR API RETURN errors
1422 int tor_get_single_ring ( void* i_ringSection,
1423- uint64_t i_magic, // Image Magic Number
1424 uint16_t i_ddLevel,
1425 RingID i_ringId,
1426 PpeType_t i_PpeType,
1427--
14281.8.2.2
1429