Brian Silver | 137a00a | 2014-11-11 12:09:53 -0600 | [diff] [blame] | 1 | # The Serial Flash Controller is the AST2400 BMC. |
| 2 | set SFC_IS_AST2400 |
| 3 | set BMC_DOES_SFC_INIT |
| 4 | unset SFC_IS_IBM_DPSS |
| 5 | set ALLOW_MICRON_PNOR |
| 6 | set ALLOW_MACRONIX_PNOR |
| 7 | |
| 8 | # VPD options. |
| 9 | set MVPD_READ_FROM_HW |
Andrew Geissler | 19d408c | 2015-02-28 13:51:47 -0600 | [diff] [blame] | 10 | set MVPD_WRITE_TO_HW |
| 11 | set MVPD_READ_FROM_PNOR |
Dan Crowell | 199ddae | 2016-05-20 08:42:45 -0500 | [diff] [blame] | 12 | set MVPD_WRITE_TO_PNOR |
Brian Silver | 137a00a | 2014-11-11 12:09:53 -0600 | [diff] [blame] | 13 | set DJVPD_READ_FROM_HW |
Andrew Geissler | 19d408c | 2015-02-28 13:51:47 -0600 | [diff] [blame] | 14 | set DJVPD_WRITE_TO_HW |
| 15 | set DJVPD_READ_FROM_PNOR |
| 16 | set DJVPD_WRITE_TO_PNOR |
Brian Silver | 137a00a | 2014-11-11 12:09:53 -0600 | [diff] [blame] | 17 | set CVPD_READ_FROM_HW |
Andrew Geissler | 19d408c | 2015-02-28 13:51:47 -0600 | [diff] [blame] | 18 | set CVPD_WRITE_TO_HW |
| 19 | set CVPD_READ_FROM_PNOR |
| 20 | set CVPD_WRITE_TO_PNOR |
Bill Schwartz | 2075be0 | 2015-04-30 14:17:52 -0500 | [diff] [blame] | 21 | set PVPD_READ_FROM_HW |
| 22 | set PVPD_WRITE_TO_HW |
| 23 | set PVPD_READ_FROM_PNOR |
| 24 | set PVPD_WRITE_TO_PNOR |
Brian Silver | 137a00a | 2014-11-11 12:09:53 -0600 | [diff] [blame] | 25 | set SKIP_RESTRICT_EX_UNITS |
Andrew Geissler | 19d408c | 2015-02-28 13:51:47 -0600 | [diff] [blame] | 26 | unset CDIMM_FORMAT_FOR_CVPD |
Brian Silver | 137a00a | 2014-11-11 12:09:53 -0600 | [diff] [blame] | 27 | |
| 28 | # gpio config |
| 29 | set GPIODD |
| 30 | set PALMETTO_VDDR |
| 31 | |
Andrew Geissler | 62864f6 | 2015-02-27 14:49:28 -0600 | [diff] [blame] | 32 | # Enable SBE updates |
Andrew Geissler | ff7983f | 2015-03-01 09:39:29 -0600 | [diff] [blame] | 33 | set SBE_UPDATE_INDEPENDENT |
Andrew Geissler | 62864f6 | 2015-02-27 14:49:28 -0600 | [diff] [blame] | 34 | |
Brian Silver | 137a00a | 2014-11-11 12:09:53 -0600 | [diff] [blame] | 35 | unset PCIE_HOTPLUG_CONTROLLER |
| 36 | |
| 37 | # turn on console output |
| 38 | set CONSOLE |
Richard J. Knight | 4fe380d | 2015-04-30 13:55:27 -0500 | [diff] [blame] | 39 | set BMC_AST2400 |
Brian Silver | 137a00a | 2014-11-11 12:09:53 -0600 | [diff] [blame] | 40 | |
| 41 | # Enable Kingston dimm voltage workaround |
| 42 | set KINGSTON_1_35_VOLT |
| 43 | |
Andrew Geissler | 19d408c | 2015-02-28 13:51:47 -0600 | [diff] [blame] | 44 | unset DISABLE_HOSTBOOT_RUNTIME |
Andrew Geissler | 5a28eaa | 2014-12-18 11:50:42 -0600 | [diff] [blame] | 45 | |
Andrew Geissler | b131459 | 2015-03-01 22:11:03 -0600 | [diff] [blame] | 46 | # Compile in hostboot runtime PRD |
| 47 | set HBRT_PRD |
| 48 | |
Andrew Geissler | 5a28eaa | 2014-12-18 11:50:42 -0600 | [diff] [blame] | 49 | # OCC Enablment flags |
Andrew Geissler | 590f263 | 2014-12-18 14:15:01 -0600 | [diff] [blame] | 50 | unset SET_NOMINAL_PSTATE |
| 51 | set HTMGT |
| 52 | set START_OCC_DURING_BOOT |
Matt Ploetz | 19aba25 | 2015-02-24 20:30:13 -0600 | [diff] [blame] | 53 | |
| 54 | #PNOR flags |
| 55 | set PNOR_TWO_SIDE_SUPPORT |
Andrew Geissler | 558fdb6 | 2015-02-26 17:56:14 -0600 | [diff] [blame] | 56 | |
| 57 | set BMC_BT_LPC_IPMI |
| 58 | |
Mike Baiocchi | 6adfe3c | 2015-04-23 17:25:14 -0500 | [diff] [blame] | 59 | # Enable Checktop Analysis |
| 60 | set ENABLE_CHECKSTOP_ANALYSIS |
aalugore | d6d2ddb | 2015-10-30 10:08:33 -0500 | [diff] [blame] | 61 | set IPLTIME_CHECKSTOP_ANALYSIS |
Mike Baiocchi | 6adfe3c | 2015-04-23 17:25:14 -0500 | [diff] [blame] | 62 | |
Bill Hoffa | dab65d9 | 2015-06-02 13:39:03 -0500 | [diff] [blame] | 63 | # Hostboot will detect hardware changes |
| 64 | set HOST_HCDB_SUPPORT |
| 65 | |
Andrew Geissler | 558fdb6 | 2015-02-26 17:56:14 -0600 | [diff] [blame] | 66 | # set for trace debug to console |
| 67 | unset CONSOLE_OUTPUT_TRACE |