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gerrit.openbmc.org / premsjha / op-build / d8d6f340602f5855c7ffe97834f38eaac8d73412 / . / openpower / package / hostboot / 0001-Revert-Fixes-LRDIMM-eff_config-bugs.patch
blob: 93b9ffc37ca43a08037490ec3cbe8692642577e8 [file] [log] [blame]
Stewart Smitha55c02c2018-11-27 11:36:05 +1100[diff] [blame]1From bfd3a8c6279881b761ed057f469b0814283fdb67 Mon Sep 17 00:00:00 2001
2From: Stewart Smith <stewart@linux.ibm.com>
3Date: Thu, 22 Nov 2018 10:51:50 +1100
4Subject: [PATCH] Revert "Fixes LRDIMM eff_config bugs"
5
6This reverts commit 40a34c94a981ebfe9e1ff95263663cda0cbaaa42.
7
8This broke p9dsu platforms with 16GB DIMMs.
9
10We'd die in ISTEP 15.1 and come back with callouts like this:
11
1210.12460|ERRL|Dumping errors reported prior to registration
1310.12793|================================================
1410.12794|Error reported by prdf (0xE500) PLID 0x90000005
1510.12794| PRD Signature : 0x240004 0x18A0000E
1610.15353| Signature Description : pu.mca:k0:n0:s0:p00:c4 (MCAECCFIR[14]) \
17 Mainline read UE
1810.17354| UserData1 : 0x0024000400000103
1910.17354| UserData2 : 0x18a0000e88047008
2010.17354|------------------------------------------------
2110.18357| Callout type : Hardware Callout
2210.20356| CPU id : 2
2310.22360| Target : Physical:/Sys0/Node0/DIMM5
2410.22361| Deconfig State : NO_DECONFIG
2510.22361| GARD Error Type : GARD_Fatal
2610.22362| Priority : SRCI_PRIORITY_MED
2710.22362|------------------------------------------------
2810.22362|
2910.22363|------------------------------------------------
3010.22363| System checkstop occurred during IPL on previous boot
3110.22364|------------------------------------------------
3210.22364|
3310.22364|------------------------------------------------
3410.22365| Hostboot Build ID: hostboot-40a34c9-p36fbe89/hbicore.bin
3510.22365|================================================
36
37*IF* you were lucky enough to IPL, you'd have a bunch of GARD records
38for DIMMs that previously worked perfectly, as well as some runtime
39memory errors:
40
41root@bstn004p1:~# opal-gard list
42 ID | Error | Type | Path
43---------------------------------------------------------
44 00000001 | 90000014 | Fatal | /Sys0/Node0/DIMM1
45 00000002 | 90000019 | Fatal | /Sys0/Node0/DIMM7
46 00000003 | 9000001e | Predictive | /Sys0/Node0/DIMM5
47 00000004 | 90000025 | Predictive | /Sys0/Node0/DIMM3
48=========================================================
49
50[ 16.165513] Memory failure: 0x0: reserved kernel page still referenced by 1 users
51[ 16.166347] Memory failure: 0x0: recovery action for reserved kernel page: Failed
52[ 17.268941] Memory failure: 0x0: already hardware poisoned
53[ 17.269908] Memory failure: 0x1: reserved kernel page still referenced by 1 users
54[ 17.270776] Memory failure: 0x1: recovery action for reserved kernel page: Failed
55
56and from opal-prd:
57
58Nov 20 00:44:13 bstn004p1 opal-prd[2894]:
59MEM: Memory error: range 0000000000000800-0000000fffffeb40, type: uncorrectable
60MEM: Failed to offline memory! page addr: 0000000000000800 type: 1: \
61 Device or resource busy
62MEM: Memory error: range 0000000000000800-0000000fffffeb40, type: uncorrectable
63MEM: Failed to offline memory! page addr: 0000000000010800 type: 1: \
64 Device or resource busy
65
66Out of the three p9dsu systems I tried, the ones with 16GB DIMMs failed,
67and the ones with 32GB DIMMs did not. FRU snippets:
68
69FRU Device Description : P1-DIMMA1 (ID 12)
70 Product Manufacturer : Samsung Electronics
71 Product Name : DDR4-2666 32GiB 64-bit ECC RDIMM
72 Product Part Number : M393A4K40BB2-CTD
73 Product Version : 00
74 Product Serial : 34ee7214
75
76FRU Device Description : P1-DIMMA1 (ID 12)
77 Product Manufacturer : Samsung Electronics
78 Product Name : DDR4-2666 16GiB 64-bit ECC RDIMM
79 Product Part Number : M393A2K40BB2-CTD
80 Product Version : 00
81 Product Serial : 3446d454
82
83FRU Device Description : P1-DIMMA1 (ID 12)
84Product Manufacturer : Samsung Electronics
85Product Name : DDR4-2666 16GiB 64-bit ECC RDIMM
86Product Part Number : M393A2K40BB2-CTD
87Product Version : 00
88Product Serial : 3569b648
89
90So, for the moment, to not break existing hardware, revert the commit.
91
92Change-Id: Ib35da530c301e2c57e8bd495a4281fc750150f5d
93Fixes: https://github.com/open-power/hostboot/issues/150
94Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
95---
96 .../procedures/hwp/initfiles/p9n_mca_scom.C | 136 +--
97 .../hwp/memory/lib/dimm/bcw_load_ddr4.C | 16 +-
98 .../memory/lib/dimm/ddr4/data_buffer_ddr4.H | 9 +-
99 .../hwp/memory/lib/dimm/ddr4/mrs01.C | 4 +-
100 .../procedures/hwp/memory/lib/dimm/eff_dimm.C | 617 ++-----------
101 .../procedures/hwp/memory/lib/dimm/eff_dimm.H | 212 +----
102 .../hwp/memory/lib/mss_attribute_accessors.H | 834 ++----------------
103 .../procedures/hwp/memory/lib/phy/ddr_phy.C | 6 +-
104 .../hwp/memory/lib/shared/mss_const.H | 1 -
105 .../procedures/hwp/memory/p9_mss_eff_config.C | 20 -
106 .../attribute_info/memory_mcs_attributes.xml | 60 --
107 .../error_info/p9_memory_mss_eff_config.xml | 18 -
108 12 files changed, 236 insertions(+), 1697 deletions(-)
109 mode change 100755 => 100644 src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
110 mode change 100755 => 100644 src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
111
112diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C
113index edce5e27f158..7b010b1da6df 100644
114--- a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C
115+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C
116@@ -183,10 +183,10 @@ fapi2::ReturnCode p9n_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0
117 literal_0x0) | l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_1]);
118 uint64_t l_def_SLOT1_DRAM_STACK_HEIGHT = (l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_1] /
119 l_def_SLOT1_DENOMINATOR);
120- fapi2::ATTR_MSS_EFF_ODT_RD_Type l_TGT2_ATTR_MSS_EFF_ODT_RD;
121- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_ODT_RD, TGT2, l_TGT2_ATTR_MSS_EFF_ODT_RD));
122- fapi2::ATTR_MSS_EFF_ODT_WR_Type l_TGT2_ATTR_MSS_EFF_ODT_WR;
123- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_ODT_WR, TGT2, l_TGT2_ATTR_MSS_EFF_ODT_WR));
124+ fapi2::ATTR_MSS_VPD_MT_ODT_RD_Type l_TGT2_ATTR_MSS_VPD_MT_ODT_RD;
125+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_RD, TGT2, l_TGT2_ATTR_MSS_VPD_MT_ODT_RD));
126+ fapi2::ATTR_MSS_VPD_MT_ODT_WR_Type l_TGT2_ATTR_MSS_VPD_MT_ODT_WR;
127+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_WR, TGT2, l_TGT2_ATTR_MSS_VPD_MT_ODT_WR));
128 fapi2::ATTR_EFF_DRAM_TREFI_Type l_TGT2_ATTR_EFF_DRAM_TREFI;
129 FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_TREFI, TGT2, l_TGT2_ATTR_EFF_DRAM_TREFI));
130 uint64_t l_def_REFRESH_INTERVAL = (l_TGT2_ATTR_EFF_DRAM_TREFI[l_def_PORT_INDEX] / (literal_8 * l_def_NUM_RANKS));
131@@ -712,133 +712,133 @@ fapi2::ReturnCode p9n_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0
132 {
133 FAPI_TRY(fapi2::getScom( TGT0, 0x7010915ull, l_scom_buffer ));
134
135- l_scom_buffer.insert<0, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_0] >>
136+ l_scom_buffer.insert<0, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_0] >>
137 literal_7) );
138- l_scom_buffer.insert<1, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_0] >>
139+ l_scom_buffer.insert<1, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_0] >>
140 literal_6) );
141- l_scom_buffer.insert<2, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_0] >>
142+ l_scom_buffer.insert<2, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_0] >>
143 literal_3) );
144- l_scom_buffer.insert<3, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_0] >>
145+ l_scom_buffer.insert<3, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_0] >>
146 literal_2) );
147- l_scom_buffer.insert<4, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_1] >>
148+ l_scom_buffer.insert<4, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_1] >>
149 literal_7) );
150- l_scom_buffer.insert<5, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_1] >>
151+ l_scom_buffer.insert<5, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_1] >>
152 literal_6) );
153- l_scom_buffer.insert<6, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_1] >>
154+ l_scom_buffer.insert<6, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_1] >>
155 literal_3) );
156- l_scom_buffer.insert<7, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_1] >>
157+ l_scom_buffer.insert<7, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_1] >>
158 literal_2) );
159- l_scom_buffer.insert<8, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_2] >>
160+ l_scom_buffer.insert<8, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_2] >>
161 literal_7) );
162- l_scom_buffer.insert<9, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_2] >>
163+ l_scom_buffer.insert<9, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_2] >>
164 literal_6) );
165- l_scom_buffer.insert<10, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_2] >>
166+ l_scom_buffer.insert<10, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_2] >>
167 literal_3) );
168- l_scom_buffer.insert<11, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_2] >>
169+ l_scom_buffer.insert<11, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_2] >>
170 literal_2) );
171- l_scom_buffer.insert<12, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_3] >>
172+ l_scom_buffer.insert<12, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_3] >>
173 literal_7) );
174- l_scom_buffer.insert<13, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_3] >>
175+ l_scom_buffer.insert<13, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_3] >>
176 literal_6) );
177- l_scom_buffer.insert<14, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_3] >>
178+ l_scom_buffer.insert<14, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_3] >>
179 literal_3) );
180- l_scom_buffer.insert<15, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_0][literal_3] >>
181+ l_scom_buffer.insert<15, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_0][literal_3] >>
182 literal_2) );
183- l_scom_buffer.insert<16, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_0] >>
184+ l_scom_buffer.insert<16, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_0] >>
185 literal_7) );
186- l_scom_buffer.insert<17, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_0] >>
187+ l_scom_buffer.insert<17, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_0] >>
188 literal_6) );
189- l_scom_buffer.insert<18, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_0] >>
190+ l_scom_buffer.insert<18, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_0] >>
191 literal_3) );
192- l_scom_buffer.insert<19, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_0] >>
193+ l_scom_buffer.insert<19, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_0] >>
194 literal_2) );
195- l_scom_buffer.insert<20, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_1] >>
196+ l_scom_buffer.insert<20, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_1] >>
197 literal_7) );
198- l_scom_buffer.insert<21, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_1] >>
199+ l_scom_buffer.insert<21, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_1] >>
200 literal_6) );
201- l_scom_buffer.insert<22, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_1] >>
202+ l_scom_buffer.insert<22, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_1] >>
203 literal_3) );
204- l_scom_buffer.insert<23, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_1] >>
205+ l_scom_buffer.insert<23, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_1] >>
206 literal_2) );
207- l_scom_buffer.insert<24, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_2] >>
208+ l_scom_buffer.insert<24, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_2] >>
209 literal_7) );
210- l_scom_buffer.insert<25, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_2] >>
211+ l_scom_buffer.insert<25, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_2] >>
212 literal_6) );
213- l_scom_buffer.insert<26, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_2] >>
214+ l_scom_buffer.insert<26, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_2] >>
215 literal_3) );
216- l_scom_buffer.insert<27, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_2] >>
217+ l_scom_buffer.insert<27, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_2] >>
218 literal_2) );
219- l_scom_buffer.insert<28, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_3] >>
220+ l_scom_buffer.insert<28, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_3] >>
221 literal_7) );
222- l_scom_buffer.insert<29, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_3] >>
223+ l_scom_buffer.insert<29, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_3] >>
224 literal_6) );
225- l_scom_buffer.insert<30, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_3] >>
226+ l_scom_buffer.insert<30, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_3] >>
227 literal_3) );
228- l_scom_buffer.insert<31, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_RD[l_def_PORT_INDEX][literal_1][literal_3] >>
229+ l_scom_buffer.insert<31, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_RD[l_def_PORT_INDEX][literal_1][literal_3] >>
230 literal_2) );
231- l_scom_buffer.insert<32, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_0] >>
232+ l_scom_buffer.insert<32, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_0] >>
233 literal_7) );
234- l_scom_buffer.insert<33, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_0] >>
235+ l_scom_buffer.insert<33, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_0] >>
236 literal_6) );
237- l_scom_buffer.insert<34, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_0] >>
238+ l_scom_buffer.insert<34, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_0] >>
239 literal_3) );
240- l_scom_buffer.insert<35, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_0] >>
241+ l_scom_buffer.insert<35, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_0] >>
242 literal_2) );
243- l_scom_buffer.insert<36, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_1] >>
244+ l_scom_buffer.insert<36, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_1] >>
245 literal_7) );
246- l_scom_buffer.insert<37, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_1] >>
247+ l_scom_buffer.insert<37, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_1] >>
248 literal_6) );
249- l_scom_buffer.insert<38, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_1] >>
250+ l_scom_buffer.insert<38, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_1] >>
251 literal_3) );
252- l_scom_buffer.insert<39, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_1] >>
253+ l_scom_buffer.insert<39, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_1] >>
254 literal_2) );
255- l_scom_buffer.insert<40, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_2] >>
256+ l_scom_buffer.insert<40, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_2] >>
257 literal_7) );
258- l_scom_buffer.insert<41, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_2] >>
259+ l_scom_buffer.insert<41, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_2] >>
260 literal_6) );
261- l_scom_buffer.insert<42, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_2] >>
262+ l_scom_buffer.insert<42, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_2] >>
263 literal_3) );
264- l_scom_buffer.insert<43, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_2] >>
265+ l_scom_buffer.insert<43, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_2] >>
266 literal_2) );
267- l_scom_buffer.insert<44, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_3] >>
268+ l_scom_buffer.insert<44, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_3] >>
269 literal_7) );
270- l_scom_buffer.insert<45, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_3] >>
271+ l_scom_buffer.insert<45, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_3] >>
272 literal_6) );
273- l_scom_buffer.insert<46, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_3] >>
274+ l_scom_buffer.insert<46, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_3] >>
275 literal_3) );
276- l_scom_buffer.insert<47, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_0][literal_3] >>
277+ l_scom_buffer.insert<47, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_0][literal_3] >>
278 literal_2) );
279- l_scom_buffer.insert<48, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_0] >>
280+ l_scom_buffer.insert<48, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_0] >>
281 literal_7) );
282- l_scom_buffer.insert<49, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_0] >>
283+ l_scom_buffer.insert<49, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_0] >>
284 literal_6) );
285- l_scom_buffer.insert<50, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_0] >>
286+ l_scom_buffer.insert<50, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_0] >>
287 literal_3) );
288- l_scom_buffer.insert<51, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_0] >>
289+ l_scom_buffer.insert<51, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_0] >>
290 literal_2) );
291- l_scom_buffer.insert<52, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_1] >>
292+ l_scom_buffer.insert<52, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_1] >>
293 literal_7) );
294- l_scom_buffer.insert<53, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_1] >>
295+ l_scom_buffer.insert<53, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_1] >>
296 literal_6) );
297- l_scom_buffer.insert<54, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_1] >>
298+ l_scom_buffer.insert<54, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_1] >>
299 literal_3) );
300- l_scom_buffer.insert<55, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_1] >>
301+ l_scom_buffer.insert<55, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_1] >>
302 literal_2) );
303- l_scom_buffer.insert<56, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_2] >>
304+ l_scom_buffer.insert<56, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_2] >>
305 literal_7) );
306- l_scom_buffer.insert<57, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_2] >>
307+ l_scom_buffer.insert<57, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_2] >>
308 literal_6) );
309- l_scom_buffer.insert<58, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_2] >>
310+ l_scom_buffer.insert<58, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_2] >>
311 literal_3) );
312- l_scom_buffer.insert<59, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_2] >>
313+ l_scom_buffer.insert<59, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_2] >>
314 literal_2) );
315- l_scom_buffer.insert<60, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_3] >>
316+ l_scom_buffer.insert<60, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_3] >>
317 literal_7) );
318- l_scom_buffer.insert<61, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_3] >>
319+ l_scom_buffer.insert<61, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_3] >>
320 literal_6) );
321- l_scom_buffer.insert<62, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_3] >>
322+ l_scom_buffer.insert<62, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_3] >>
323 literal_3) );
324- l_scom_buffer.insert<63, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_EFF_ODT_WR[l_def_PORT_INDEX][literal_1][literal_3] >>
325+ l_scom_buffer.insert<63, 1, 63, uint64_t>((l_TGT2_ATTR_MSS_VPD_MT_ODT_WR[l_def_PORT_INDEX][literal_1][literal_3] >>
326 literal_2) );
327 FAPI_TRY(fapi2::putScom(TGT0, 0x7010915ull, l_scom_buffer));
328 }
329diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C
330index 353973562b99..92e65bc5d0fd 100644
331--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C
332+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C
333@@ -100,7 +100,6 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target
334 { FUNC_SPACE_0, DQ_DRIVER_CW, eff_dimm_ddr4_bc03, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW},
335 { FUNC_SPACE_0, MDQ_RTT_CW, eff_dimm_ddr4_bc04, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW},
336 { FUNC_SPACE_0, MDQ_DRIVER_CW, eff_dimm_ddr4_bc05, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW},
337- { FUNC_SPACE_0, CMD_SPACE_CW, eff_dimm_ddr4_bc06, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW},
338 { FUNC_SPACE_0, RANK_PRESENCE_CW, eff_dimm_ddr4_bc07, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW},
339 { FUNC_SPACE_0, RANK_SELECTION_CW, eff_dimm_ddr4_bc08, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW},
340 { FUNC_SPACE_0, POWER_SAVING_CW, eff_dimm_ddr4_bc09, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW},
341@@ -112,23 +111,14 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target
342 { FUNC_SPACE_0, ERROR_STATUS_CW, eff_dimm_ddr4_bc0f, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW},
343
344 // 8-bit BCW's now
345- // Function space 0 - we're already there, so that's nice
346- { FUNC_SPACE_0, BUFF_CONFIG_CW, eff_dimm_ddr4_f0bc1x, mss::tmrc(), CW8_DATA_LEN, cw_info::BCW},
347- { FUNC_SPACE_0, LRDIMM_OPERATING_SPEED, eff_dimm_ddr4_f0bc6x, mss::tmrc(), CW8_DATA_LEN, cw_info::BCW},
348-
349- // Function space 2
350- { FUNC_SPACE_2, FUNC_SPACE_SELECT_CW, FUNC_SPACE_2, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW},
351- { FUNC_SPACE_2, HOST_DFE, eff_dimm_ddr4_f2bcex, mss::tmrc(), CW8_DATA_LEN, cw_info::BCW},
352+ // Function space 6
353+ { FUNC_SPACE_6, FUNC_SPACE_SELECT_CW, FUNC_SPACE_6, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW},
354+ { FUNC_SPACE_6, BUFF_TRAIN_CONFIG_CW, eff_dimm_ddr4_f6bc4x, mss::tmrc(), CW8_DATA_LEN, cw_info::BCW},
355
356 // Function space 5
357 { FUNC_SPACE_5, FUNC_SPACE_SELECT_CW, FUNC_SPACE_5, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW},
358- { FUNC_SPACE_5, HOST_VREF_CW, eff_dimm_ddr4_f5bc5x, mss::tmrc(), CW8_DATA_LEN, cw_info::BCW},
359 { FUNC_SPACE_5, DRAM_VREF_CW, eff_dimm_ddr4_f5bc6x, mss::tmrc(), CW8_DATA_LEN, cw_info::BCW},
360
361- // Function space 6
362- { FUNC_SPACE_6, FUNC_SPACE_SELECT_CW, FUNC_SPACE_6, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW},
363- { FUNC_SPACE_6, BUFF_TRAIN_CONFIG_CW, eff_dimm_ddr4_f6bc4x, mss::tmrc(), CW8_DATA_LEN, cw_info::BCW},
364-
365
366 // So, we always want to know what function space we're in
367 // The way to do that is to always return to one function space
368diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H
369index ab980a962bcc..9f7d38a41eb6 100644
370--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H
371+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H
372@@ -90,12 +90,9 @@ enum db02_def : size_t
373 FUNC_SPACE_SELECT_CW = 0x7,
374
375 // 8 bit BCWs
376- BUFF_CONFIG_CW = 0x1, // Func space 0
377- LRDIMM_OPERATING_SPEED = 0x6, // Func space 0
378- HOST_DFE = 0xE, // Func space 2
379- HOST_VREF_CW = 0x5, // Func space 5
380- DRAM_VREF_CW = 0x6, // Func space 5
381- BUFF_TRAIN_CONFIG_CW = 0x4, // Func space 6
382+ BUFF_CONFIG_CW = 0x1,
383+ DRAM_VREF_CW = 0x6,
384+ BUFF_TRAIN_CONFIG_CW = 0x4,
385 };
386
387 namespace ddr4
388diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C
389index 834ee1ead1fc..3fd08b8a060e 100644
390--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C
391+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C
392@@ -5,7 +5,7 @@
393 /* */
394 /* OpenPOWER HostBoot Project */
395 /* */
396-/* Contributors Listed Below - COPYRIGHT 2016,2018 */
397+/* Contributors Listed Below - COPYRIGHT 2016,2017 */
398 /* [+] International Business Machines Corp. */
399 /* */
400 /* */
401@@ -62,7 +62,7 @@ mrs01_data::mrs01_data( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
402 iv_qoff(0)
403 {
404 FAPI_TRY( mss::eff_dram_dll_enable(i_target, iv_dll_enable), "Error in mrs01_data()" );
405- FAPI_TRY( mss::eff_dram_odic(i_target, &(iv_odic[0])), "Error in mrs01_data()" );
406+ FAPI_TRY( mss::vpd_mt_dram_drv_imp_dq_dqs(i_target, &(iv_odic[0])), "Error in mrs01_data()" );
407 FAPI_TRY( mss::eff_dram_al(i_target, iv_additive_latency), "Error in mrs01_data()" );
408 FAPI_TRY( mss::eff_dram_wr_lvl_enable(i_target, iv_wl_enable), "Error in mrs01_data()" );
409 FAPI_TRY( mss::eff_dram_rtt_nom(i_target, &(iv_rtt_nom[0])), "Error in mrs01_data()" );
410diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
411old mode 100755
412new mode 100644
413index b5e562a398e4..ae55f78e05bf
414--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
415+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
416@@ -312,20 +312,9 @@ enum rc3x_encode : uint8_t
417 enum bc03_encode : uint8_t
418 {
419 // Bit position of the BC03 bit to enable/ disable DQ/ DQS drivers
420- BC03_HOST_DQ_DISABLE_POS = 4,
421- BC03_HOST_DQ_DISABLE = 1,
422- BC03_HOST_DQ_ENABLE = 0,
423-};
424-
425-///
426-/// @brief bc05_encode enums for DRAM Interface MDQ Driver Control Word
427-///
428-enum bc05_encode : uint8_t
429-{
430- // Bit position of the BC05 bit to enable/ disable DQ/ DQS drivers
431- BC05_DRAM_DQ_DRIVER_DISABLE_POS = 4,
432- BC05_DRAM_DQ_DRIVER_DISABLE = 1,
433- BC05_DRAM_DQ_DRIVER_ENABLE = 0,
434+ BC03_DQ_DISABLE_POS = 4,
435+ BC03_DQ_DISABLE = 1,
436+ BC03_DQ_ENABLE = 0,
437 };
438
439
440@@ -340,7 +329,6 @@ enum bc09_encode : uint8_t
441 BC09_CKE_POWER_DOWN_ENABLE_POS = 4,
442 BC09_CKE_POWER_ODT_OFF = 1,
443 BC09_CKE_POWER_ODT_ON = 0,
444- BC09_CKE_POWER_ODT_POS = 5,
445 };
446
447 ///
448@@ -360,7 +348,6 @@ enum invalid_freq_function_encoding : uint8_t
449 RC0A = 0x0a,
450 RC3X = 0x30,
451 BC0A = 0x0a,
452- F0BC6X = 0x60,
453 };
454
455 ///
456@@ -1417,28 +1404,6 @@ fapi_try_exit:
457 return fapi2::current_err;
458 }
459
460-///
461-/// @brief Determines & sets effective config for DRAM output driver impedance control
462-/// @return fapi2::FAPI2_RC_SUCCESS if okay
463-///
464-fapi2::ReturnCode eff_rdimm::dram_odic()
465-{
466- uint8_t l_dram_odic[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
467- uint8_t l_vpd_odic[MAX_RANK_PER_DIMM];
468- FAPI_TRY( eff_dram_odic(iv_mcs, &l_dram_odic[0][0][0]));
469-
470- // Gets the VPD value
471- FAPI_TRY( mss::vpd_mt_dram_drv_imp_dq_dqs(iv_dimm, &(l_vpd_odic[0])));
472-
473- // Updates DRAM ODIC with the VPD value
474- memcpy(&(l_dram_odic[iv_port_index][iv_dimm_index][0]), l_vpd_odic, MAX_RANK_PER_DIMM);
475-
476- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_ODIC, iv_mcs, l_dram_odic) );
477-
478-fapi_try_exit:
479- return fapi2::current_err;
480-}
481-
482 ///
483 /// @brief Determines & sets effective config for tCCD_L
484 /// @return fapi2::FAPI2_RC_SUCCESS if okay
485@@ -1926,8 +1891,8 @@ fapi2::ReturnCode eff_dimm::dimm_rc09()
486 // 2) Gets the ODT values for the other DIMM
487 uint8_t l_wr_odt[MAX_RANK_PER_DIMM] = {};
488 uint8_t l_rd_odt[MAX_RANK_PER_DIMM] = {};
489- FAPI_TRY(eff_odt_rd(l_other_dimm, l_rd_odt));
490- FAPI_TRY(eff_odt_wr(l_other_dimm, l_wr_odt));
491+ FAPI_TRY(vpd_mt_odt_rd(l_other_dimm, l_rd_odt));
492+ FAPI_TRY(vpd_mt_odt_wr(l_other_dimm, l_wr_odt));
493
494 // 3) Checks whether this DIMM's ODTs are used for writes or reads that target the other DIMMs
495 for(uint8_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank)
496@@ -2896,42 +2861,6 @@ fapi_try_exit:
497 return fapi2::current_err;
498 }
499
500-///
501-/// @brief Determines & sets effective config for Vref DQ Train Value and Range
502-/// @return fapi2::FAPI2_RC_SUCCESS if okay
503-///
504-// TODO:RTC200577 Update LRDIMM termination settings for dual drop and 4 rank DIMM's
505-fapi2::ReturnCode eff_lrdimm::vref_dq_train_value_and_range()
506-{
507- uint8_t l_vref_dq_train_value[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
508- uint8_t l_vref_dq_train_range[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
509- fapi2::buffer<uint8_t> l_vref_range;
510-
511- // Gets the attributes
512- FAPI_TRY( eff_vref_dq_train_value(iv_mcs, &l_vref_dq_train_value[0][0][0]) );
513- FAPI_TRY( eff_vref_dq_train_range(iv_mcs, &l_vref_dq_train_range[0][0][0]) );
514-
515- // Using hardcoded values for 2R settings from the IBM SI team
516- // It should be good enough to get us going
517- for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank)
518- {
519- constexpr uint8_t VREF_79PERCENT = 0x1d;
520- // Yes, range1 has a value of 0 this is taken from the JEDEC spec
521- constexpr uint8_t RANGE1 = 0x00;
522- l_vref_dq_train_value[iv_port_index][iv_dimm_index][l_rank] = VREF_79PERCENT;
523- l_vref_dq_train_range[iv_port_index][iv_dimm_index][l_rank] = RANGE1;
524- }
525-
526- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_VREF_DQ_TRAIN_VALUE, iv_mcs, l_vref_dq_train_value),
527- "Failed setting attribute for ATTR_EFF_VREF_DQ_TRAIN_VALUE");
528-
529- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_VREF_DQ_TRAIN_RANGE, iv_mcs, l_vref_dq_train_range),
530- "Failed setting attribute for ATTR_EFF_VREF_DQ_TRAIN_RANGE");
531-
532-fapi_try_exit:
533- return fapi2::current_err;
534-}
535-
536 ///
537 /// @brief Determines & sets effective config for Vref DQ Train Enable
538 /// @return fapi2::FAPI2_RC_SUCCESS if okay
539@@ -4350,7 +4279,7 @@ fapi2::ReturnCode eff_rdimm::dram_rtt_nom()
540 // Indexed by denominator. So, if RQZ is 240, and you have OHM240, then you're looking
541 // for mss::index 1. So this doesn't correspond directly with the table in the JEDEC spec,
542 // as that's not in "denominator order."
543- // 0 RQZ/1 RQZ/2 RQZ/3 RQZ/4 RQZ/5 RQZ/6 RQZ/7
544+ // 0 RQZ/1 RQZ/2 RQZ/3 RQZ/4 RQZ/5 RQZ/6 RQZ/7
545 constexpr uint8_t rtt_nom_map[RTT_NOM_MAP_SIZE] = { 0, 0b100, 0b010, 0b110, 0b001, 0b101, 0b011, 0b111 };
546
547 size_t l_rtt_nom_index = 0;
548@@ -4400,21 +4329,24 @@ fapi_try_exit:
549 /// @return fapi2::FAPI2_RC_SUCCESS if okay
550 /// @note used for MRS01
551 ///
552-// TODO:RTC200577 Update LRDIMM termination settings for dual drop and 4 rank DIMM's
553 fapi2::ReturnCode eff_lrdimm::dram_rtt_nom()
554 {
555+ std::vector< uint64_t > l_ranks;
556+
557+ uint8_t l_decoder_val = 0;
558 uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
559 FAPI_TRY( eff_dram_rtt_nom(iv_mcs, &l_mcs_attrs[0][0][0]) );
560
561- // The host is in charge of ensuring good termination from the buffer to the DRAM
562- // That means that we need to know and set the settings
563- // Currently, our SI team thinks that the 2R single drop open power settings will work for BUP
564- // We're going to hard code in those settings the above story can be used as a catchall to improve settings if need be
565- // Loops through all ranks
566- for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank)
567+ // Get the value from the LRDIMM SPD
568+ FAPI_TRY( iv_spd_decoder.dram_rtt_nom(iv_freq, l_decoder_val));
569+
570+ // Plug into every rank position for the attribute so it'll fit the same style as the RDIMM value
571+ // Same value for every rank for LRDIMMs
572+ FAPI_TRY(mss::rank::ranks(iv_dimm, l_ranks));
573+
574+ for (const auto& l_rank : l_ranks)
575 {
576- // Taking the 34ohm value from up above
577- l_mcs_attrs[iv_port_index][iv_dimm_index][l_rank] = 0b111;
578+ l_mcs_attrs[iv_port_index][iv_dimm_index][mss::index(l_rank)] = l_decoder_val;
579 }
580
581 FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_NOM, iv_mcs, l_mcs_attrs) );
582@@ -4481,21 +4413,23 @@ fapi_try_exit:
583 /// @return fapi2::FAPI2_RC_SUCCESS if okay
584 /// @note used for MRS02
585 ///
586-// TODO:RTC200577 Update LRDIMM termination settings for dual drop and 4 rank DIMM's
587 fapi2::ReturnCode eff_lrdimm::dram_rtt_wr()
588 {
589+ std::vector< uint64_t > l_ranks;
590+
591+ uint8_t l_decoder_val = 0;
592 uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
593- FAPI_TRY( eff_dram_rtt_wr(iv_mcs, &l_mcs_attrs[0][0][0]) );
594
595- // The host is in charge of ensuring good termination from the buffer to the DRAM
596- // That means that we need to know and set the settings
597- // Currently, our SI team thinks that the 2R single drop open power settings will work for BUP
598- // We're going to hard code in those settings the above story can be used as a catchall to improve settings if need be
599- // Loops through all ranks
600- for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank)
601+ // Get the value from the LRDIMM SPD
602+ FAPI_TRY( iv_spd_decoder.dram_rtt_wr(iv_freq, l_decoder_val));
603+
604+ // Plug into every rank position for the attribute so it'll fit the same style as the RDIMM value
605+ // Same value for every rank for LRDIMMs
606+ FAPI_TRY(mss::rank::ranks(iv_dimm, l_ranks));
607+
608+ for (const auto& l_rank : l_ranks)
609 {
610- // Taking the disable value from up above
611- l_mcs_attrs[iv_port_index][iv_dimm_index][l_rank] = 0b000;
612+ l_mcs_attrs[iv_port_index][iv_dimm_index][mss::index(l_rank)] = l_decoder_val;
613 }
614
615 // Set the attribute
616@@ -4554,23 +4488,27 @@ fapi_try_exit:
617 /// @return fapi2::FAPI2_RC_SUCCESS if okay
618 /// @note used for MRS05
619 ///
620-// TODO:RTC200577 Update LRDIMM termination settings for dual drop and 4 rank DIMM's
621 fapi2::ReturnCode eff_lrdimm::dram_rtt_park()
622 {
623 uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
624+ uint8_t l_decoder_val_01 = 0;
625+ uint8_t l_decoder_val_23 = 0;
626
627 FAPI_TRY( eff_dram_rtt_park(iv_mcs, &l_mcs_attrs[0][0][0]) );
628
629- // The host is in charge of ensuring good termination from the buffer to the DRAM
630- // That means that we need to know and set the settings
631- // Currently, our SI team thinks that the 2R single drop open power settings will work for BUP
632- // We're going to hard code in those settings the above story can be used as a catchall to improve settings if need be
633- // Loops through all ranks
634- for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank)
635- {
636- // Taking the disable value from up above
637- l_mcs_attrs[iv_port_index][iv_dimm_index][l_rank] = 0b000;
638- }
639+ // Get the value from the LRDIMM SPD
640+ FAPI_TRY( iv_spd_decoder.dram_rtt_park_ranks0_1(iv_freq, l_decoder_val_01),
641+ "%s failed to decode RTT_PARK for ranks 0/1", mss::c_str(iv_mcs) );
642+ FAPI_TRY( iv_spd_decoder.dram_rtt_park_ranks2_3(iv_freq, l_decoder_val_23),
643+ "%s failed to decode RTT_PARK for ranks 2/3", mss::c_str(iv_mcs) );
644+
645+ // Setting the four rank values for this dimm
646+ // Rank 0 and 1 have the same value, l_decoder_val_01
647+ // Rank 2 and 3 have the same value, l_decoder_val_23
648+ l_mcs_attrs[iv_port_index][iv_dimm_index][0] = l_decoder_val_01;
649+ l_mcs_attrs[iv_port_index][iv_dimm_index][1] = l_decoder_val_01;
650+ l_mcs_attrs[iv_port_index][iv_dimm_index][2] = l_decoder_val_23;
651+ l_mcs_attrs[iv_port_index][iv_dimm_index][3] = l_decoder_val_23;
652
653 FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_PARK, iv_mcs, l_mcs_attrs) );
654
655@@ -4661,16 +4599,13 @@ fapi2::ReturnCode eff_lrdimm::dimm_bc01()
656 uint8_t l_dram_rtt_wr[MAX_RANK_PER_DIMM];
657 FAPI_TRY( mss::vpd_mt_dram_rtt_wr(iv_dimm, &(l_dram_rtt_wr[0])) );
658
659- // Rzq is 240, so calculate from there
660 static const std::vector< std::pair<uint8_t, uint8_t> > l_rtt_wr_map =
661 {
662 {fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_DISABLE, 0b000},
663- {fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_HIGHZ, 0b111},
664- // Note: we don't have this value for DDR4 RTT_WR, so we don't have a constant for it
665- {60, 0b001}, // RZQ/4
666- {fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM80, 0b110}, // RZQ/3
667- {fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM120, 0b010}, // RZQ/2
668- {fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM240, 0b100} // RZQ/1
669+ {fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_HIGHZ, 0b011},
670+ {fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM80, 0b100}, // RZQ/3
671+ {fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM120, 0b001}, // RZQ/2
672+ {fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM240, 0b010}
673 };
674
675 FAPI_ASSERT( mss::find_value_from_key(l_rtt_wr_map, l_dram_rtt_wr[l_rank], l_encoding),
676@@ -4708,38 +4643,29 @@ fapi2::ReturnCode eff_lrdimm::dimm_bc02()
677 // Retrieve MCS attribute data
678 uint8_t l_attrs_dimm_bc02[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
679
680- uint8_t l_rank = 0;
681- // Indexed by denominator. So, if RQZ is 240, and you have OHM240, then you're looking
682- // for mss::index 1. So this doesn't correspond directly with the table in the JEDEC spec,
683- // as that's not in "denominator order."
684- constexpr uint64_t RTT_PARK_COUNT = 8;
685- // 0 RQZ/1 RQZ/2 RQZ/3 RQZ/4 RQZ/5 RQZ/6 RQZ/7
686- constexpr uint8_t rtt_park_map[RTT_PARK_COUNT] = { 0, 0b100, 0b010, 0b110, 0b001, 0b101, 0b011, 0b111 };
687+ {
688+ uint8_t l_rank = 0;
689+ // Indexed by denominator. So, if RQZ is 240, and you have OHM240, then you're looking
690+ // for mss::index 1. So this doesn't correspond directly with the table in the JEDEC spec,
691+ // as that's not in "denominator order."
692+ constexpr uint64_t RTT_PARK_COUNT = 8;
693+ // 0 RQZ/1 RQZ/2 RQZ/3 RQZ/4 RQZ/5 RQZ/6 RQZ/7
694+ constexpr uint8_t rtt_park_map[RTT_PARK_COUNT] = { 0, 0b100, 0b010, 0b110, 0b001, 0b101, 0b011, 0b111 };
695
696- uint8_t l_rtt_park[MAX_RANK_PER_DIMM];
697- uint8_t l_rtt_park_index = 0;
698+ uint8_t l_rtt_park[MAX_RANK_PER_DIMM];
699
700- FAPI_TRY( mss::vpd_mt_dram_rtt_park(iv_dimm, &(l_rtt_park[0])) );
701+ FAPI_TRY( mss::vpd_mt_dram_rtt_park(iv_dimm, &(l_rtt_park[0])) );
702
703- // We have to be careful about 0
704- l_rtt_park_index = (l_rtt_park[l_rank] == 0) ?
705- 0 : fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_PARK_240OHM / l_rtt_park[l_rank];
706+ // Calculate the value for each rank and store in attribute
707+ uint8_t l_rtt_park_index = 0;
708
709- // Make sure it's a valid index
710- FAPI_ASSERT( l_rtt_park_index < RTT_PARK_COUNT,
711- fapi2::MSS_INVALID_RTT_PARK_CALCULATIONS()
712- .set_RANK(l_rank)
713- .set_RTT_PARK_INDEX(l_rtt_park_index)
714- .set_RTT_PARK_FROM_VPD(l_rtt_park[mss::index(l_rank)])
715- .set_DIMM_TARGET(iv_dimm),
716- "Error calculating RTT_PARK for target %s rank %d, rtt_park from vpd is %d, index is %d",
717- mss::c_str(iv_dimm),
718- l_rank,
719- l_rtt_park[mss::index(l_rank)],
720- l_rtt_park_index);
721+ // We have to be careful about 0
722+ l_rtt_park_index = (l_rtt_park[l_rank] == 0) ?
723+ 0 : fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_PARK_240OHM / l_rtt_park[l_rank];
724
725- // Map from RTT_PARK array to the value in the map
726- l_decoder_val = rtt_park_map[l_rtt_park_index];
727+ // Map from RTT_PARK array to the value in the map
728+ l_decoder_val = rtt_park_map[l_rtt_park_index];
729+ }
730
731 FAPI_TRY( eff_dimm_ddr4_bc02(iv_mcs, &l_attrs_dimm_bc02[0][0]) );
732 l_attrs_dimm_bc02[iv_port_index][iv_dimm_index] = l_decoder_val;
733@@ -4798,7 +4724,7 @@ fapi2::ReturnCode eff_lrdimm_db01::dimm_bc03()
734
735 // Using a writeBit for clarity sake
736 // Enabling Host interface DQ/DQS driver
737- l_result.writeBit<BC03_HOST_DQ_DISABLE_POS>(BC03_HOST_DQ_ENABLE);
738+ l_result.writeBit<BC03_DQ_DISABLE_POS>(BC03_DQ_ENABLE);
739
740 FAPI_TRY( eff_dimm_ddr4_bc03(iv_mcs, &l_attrs_dimm_bc03[0][0]) );
741 l_attrs_dimm_bc03[iv_port_index][iv_dimm_index] = l_result;
742@@ -4834,7 +4760,7 @@ fapi2::ReturnCode eff_lrdimm_db02::dimm_bc03()
743
744 // Treat buffer as 0th rank. LRDIMM in our eyes only have 1 rank
745 constexpr size_t l_rank = 0;
746- fapi2::buffer<uint8_t> l_result;
747+ fapi2::buffer<uint8_t> l_result = 0;
748 uint64_t l_ohm_value = 0;
749 uint8_t l_encoding = 0;
750 // attributes
751@@ -4858,7 +4784,7 @@ fapi2::ReturnCode eff_lrdimm_db02::dimm_bc03()
752
753 // Using a writeBit for clarity sake
754 // Enabling DQ/DQS drivers
755- l_result.writeBit<BC03_HOST_DQ_DISABLE_POS>(BC03_HOST_DQ_ENABLE);
756+ l_result.writeBit<BC03_DQ_DISABLE_POS>(BC03_DQ_ENABLE);
757
758 // Retrieve MCS attribute data
759 FAPI_TRY( eff_dimm_ddr4_bc03(iv_mcs, &l_attrs_dimm_bc03[0][0]) );
760@@ -4886,15 +4812,21 @@ fapi_try_exit:
761 /// DRAM Interface MDQ/MDQS ODT Strength for Data Buffer
762 /// Comes from SPD
763 ///
764-// TODO:RTC200577 Update LRDIMM termination settings for dual drop and 4 rank DIMM's
765 fapi2::ReturnCode eff_lrdimm::dimm_bc04()
766 {
767+ uint8_t l_decoder_val = 0;
768+
769 // Retrieve MCS attribute data
770 uint8_t l_attrs_dimm_bc04[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
771 FAPI_TRY( eff_dimm_ddr4_bc04(iv_mcs, &l_attrs_dimm_bc04[0][0]) );
772+ // Update MCS attribute
773
774- // Taken from SI spreadsheet and JEDEC - we want 60 Ohms, so 0x01 for a value
775- l_attrs_dimm_bc04[iv_port_index][iv_dimm_index] = 0x01;
776+ // So the encoding from the SPD is the same as the encoding for the buffer control encoding
777+ // Simple grab and insert
778+ // Value is checked in decoder function for validity
779+ FAPI_TRY( iv_spd_decoder.data_buffer_mdq_rtt(iv_freq, l_decoder_val) );
780+
781+ // Update MCS attribute
782
783 FAPI_INF("%s: BC04 settting (MDQ_RTT): %d", mss::c_str(iv_dimm), l_attrs_dimm_bc04[iv_port_index][iv_dimm_index] );
784 FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_BC04, iv_mcs, l_attrs_dimm_bc04) );
785@@ -4911,22 +4843,19 @@ fapi_try_exit:
786 /// Page 57 Table 28
787 /// @note DRAM Interface MDQ/MDQS Output Driver Impedance control
788 ///
789-// TODO:RTC200577 Update LRDIMM termination settings for dual drop and 4 rank DIMM's
790 fapi2::ReturnCode eff_lrdimm::dimm_bc05()
791 {
792- // Taken from the SI spreadsheet - we want 34 Ohms so 0x01
793- fapi2::buffer<uint8_t> l_result(0x01);
794+ uint8_t l_decoder_val;
795
796 // Retrieve MCS attribute data
797 uint8_t l_attrs_dimm_bc05[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
798 FAPI_TRY( eff_dimm_ddr4_bc05(iv_mcs, &l_attrs_dimm_bc05[0][0]) );
799
800- // Using a writeBit for clarity sake
801- // Enabling DQ/DQS drivers
802- l_result.writeBit<BC05_DRAM_DQ_DRIVER_DISABLE_POS>(BC05_DRAM_DQ_DRIVER_ENABLE);
803- l_attrs_dimm_bc05[iv_port_index][iv_dimm_index] = l_result;
804+ // Same as BC04, grab from SPD and put into BC
805+ FAPI_TRY( iv_spd_decoder.data_buffer_mdq_drive_strength(iv_freq, l_decoder_val) );
806+ l_attrs_dimm_bc05[iv_port_index][iv_dimm_index] = l_decoder_val;
807
808- FAPI_INF("%s: BC05 settting (MDQ Drive Strength): 0x%02x", mss::c_str(iv_dimm),
809+ FAPI_INF("%s: BC05 settting (MDQ Drive Strenght): %d", mss::c_str(iv_dimm),
810 l_attrs_dimm_bc05[iv_port_index][iv_dimm_index] );
811 FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_BC05, iv_mcs, l_attrs_dimm_bc05) );
812
813@@ -4934,32 +4863,6 @@ fapi_try_exit:
814 return fapi2::current_err;
815 }
816
817-///
818-/// @brief Determines & sets effective config for DIMM BC06
819-/// @return fapi2::FAPI2_RC_SUCCESS if okay
820-/// @noteCommand Space Control Word
821-/// From DDR4DB02 Spec Rev 0.95
822-/// Page 57 Table 28
823-/// @note DRAM Interface MDQ/MDQS Output Driver Impedance control
824-///
825-fapi2::ReturnCode eff_lrdimm::dimm_bc06()
826-{
827- constexpr uint8_t RESET_DLL = 0x00;
828-
829- // Retrieve MCS attribute data
830- uint8_t l_attrs_dimm_bc06[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
831- FAPI_TRY( eff_dimm_ddr4_bc06(iv_mcs, &l_attrs_dimm_bc06[0][0]) );
832-
833- l_attrs_dimm_bc06[iv_port_index][iv_dimm_index] = RESET_DLL;
834-
835- FAPI_INF("%s: BC06 settting (Command Space Control Word): 0x%02x", mss::c_str(iv_dimm),
836- l_attrs_dimm_bc06[iv_port_index][iv_dimm_index] );
837- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_BC06, iv_mcs, l_attrs_dimm_bc06) );
838-
839-fapi_try_exit:
840- return fapi2::current_err;
841-}
842-
843 ///
844 /// @brief Determines & sets effective config for DIMM BC07
845 /// @return fapi2::FAPI2_RC_SUCCESS if okay
846@@ -4972,7 +4875,7 @@ fapi2::ReturnCode eff_lrdimm::dimm_bc07()
847 {
848 // Map for the bc07 attribute, Each bit and its position represents one rank
849 // 0b0 == enabled, 0b1 == disabled
850- // 1 rank 2 rank 3 rank 4 rank
851+ // 1 rank 2 rank 3 rank 4 rank
852 constexpr uint8_t const dram_map [MAX_RANK_PER_DIMM] = {0b1110, 0b1100, 0b1000, 0b0000};
853 uint8_t l_ranks_per_dimm = 0;
854
855@@ -4986,15 +4889,7 @@ fapi2::ReturnCode eff_lrdimm::dimm_bc07()
856 // Subtract so 1 rank == 0, 2 rank == 1, etc. For array mss::indexing
857 --l_ranks_per_dimm;
858 // Make sure we didn't overflow or screw up somehow
859- // TK Thoughts on if we need an official error code below??
860- FAPI_ASSERT(l_ranks_per_dimm < MAX_RANK_PER_DIMM,
861- fapi2::MSS_OUT_OF_BOUNDS_INDEXING()
862- .set_TARGET(iv_dimm)
863- .set_INDEX(l_ranks_per_dimm)
864- .set_LIST_SIZE(MAX_RANK_PER_DIMM)
865- .set_FUNCTION(EFF_BC07),
866- "%s has ranks per dimm (%u) out of bounds: %u",
867- mss::c_str(iv_dimm), l_ranks_per_dimm, MAX_RANK_PER_DIMM);
868+ fapi2::Assert (l_ranks_per_dimm < MAX_RANK_PER_DIMM);
869
870 l_attrs_dimm_bc07[iv_port_index][iv_dimm_index] = dram_map[l_ranks_per_dimm];
871
872@@ -5024,7 +4919,8 @@ fapi2::ReturnCode eff_lrdimm::dimm_bc08()
873 // Update MCS attribute
874 FAPI_TRY( eff_dimm_ddr4_bc08(iv_mcs, &l_attrs_dimm_bc08[0][0]) );
875 // BC08 is used to set the rank for Write Leveling training modes
876- // This value is used in training so a value of 0 is fine for now
877+ // Defaulting to 0 because every dimm should have a rank 0, right?
878+ // This attribute should be set in training...
879 l_attrs_dimm_bc08[iv_port_index][iv_dimm_index] = 0;
880
881 FAPI_INF("%s: BC08 settting: %d", mss::c_str(iv_dimm), l_attrs_dimm_bc08[iv_port_index][iv_dimm_index] );
882@@ -5051,9 +4947,9 @@ fapi2::ReturnCode eff_lrdimm::dimm_bc09()
883
884 fapi2::buffer<uint8_t> l_setting = 0;
885
886- // Enabling power down mode (when CKE's are low!) to bring us inline with RC09/RCD powerdown mode
887- l_setting.writeBit<BC09_CKE_POWER_DOWN_ENABLE_POS>(BC09_CKE_POWER_DOWN_ENABLE)
888- .writeBit<BC09_CKE_POWER_ODT_POS>(BC09_CKE_POWER_ODT_OFF);
889+ // Disabling for now until characterization can be done
890+ // Power/ performance setting
891+ l_setting.writeBit<BC09_CKE_POWER_DOWN_ENABLE_POS> (BC09_CKE_POWER_DOWN_DISABLE);
892
893 // Update MCS attribute
894 FAPI_TRY( eff_dimm_ddr4_bc09(iv_mcs, &l_attrs_dimm_bc09[0][0]) );
895@@ -5126,7 +5022,6 @@ fapi2::ReturnCode eff_lrdimm_db01::dimm_bc0b()
896
897 // Update MCS attribute
898 // Only option is to set it to 0 to signify 1.2 operating Voltage, everything else is reserved
899- // Per the IBM signal integrity team, the default value should be sufficient
900 l_attrs_dimm_bc0b[iv_port_index][iv_dimm_index] = 0;
901
902 FAPI_INF("%s: BC0b settting: %d", mss::c_str(iv_dimm), l_attrs_dimm_bc0b[iv_port_index][iv_dimm_index] );
903@@ -5153,7 +5048,6 @@ fapi2::ReturnCode eff_lrdimm_db02::dimm_bc0b()
904 // Bits 0~1 (IBM numbering) are for slew rate
905 // Bit 3 is reserved, Bit 4 has to be 0 to signal 1.2 V Buffer Vdd Voltage
906 // Hard coding values to 0, sets slew rate to Moderate (according to Dan Phipps, this is fine)
907- // Per the IBM signal integrity team, the default value should be sufficient
908 l_attrs_dimm_bc0b[iv_port_index][iv_dimm_index] = 0;
909
910 FAPI_INF("%s: BC0b settting: %d", mss::c_str(iv_dimm), l_attrs_dimm_bc0b[iv_port_index][iv_dimm_index] );
911@@ -5216,7 +5110,7 @@ fapi_try_exit:
912 ///
913 /// @brief Determines & sets effective config for DIMM BC0d
914 /// @return fapi2::FAPI2_RC_SUCCESS if okay
915-/// @note Reserved for future use - set it to 0 for now
916+/// @note LDQ Operation Control Word
917 /// From DDR4DB01 Spec Rev 1.0
918 /// Page 61 Table 25
919 /// All values are reserved for DB01, setting to 0
920@@ -5240,7 +5134,7 @@ fapi_try_exit:
921 ///
922 /// @brief Determines & sets effective config for DIMM BC0d
923 /// @return fapi2::FAPI2_RC_SUCCESS if okay
924-/// @note Reserved for future use - set it to 0 for now
925+/// @note LDQ Operation Control Word
926 /// From DDR4DB02 Spec Rev 0.95
927 /// Page 60 Table 24
928 /// @note This register is used by the Non Volatile controller (NVC) to change the mode of operation of the DDR4DB02
929@@ -5309,219 +5203,6 @@ fapi_try_exit:
930 return fapi2::current_err;
931 }
932
933-///
934-/// @brief Determines and sets DIMM BC1x
935-/// @return fapi2::FAPI2_RC_SUCCESS if okay
936-///
937-fapi2::ReturnCode eff_lrdimm::dimm_f0bc1x()
938-{
939- uint8_t l_attrs_dimm_bc_1x[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
940-
941- // Retrieve MCS attribute data
942- FAPI_TRY( eff_dimm_ddr4_f0bc1x(iv_mcs, &l_attrs_dimm_bc_1x[0][0]) );
943-
944- // Setup to default as we want to be in runtime mode
945- l_attrs_dimm_bc_1x[iv_port_index][iv_dimm_index] = 0;
946-
947- FAPI_INF( "%s: F0BC1X setting: 0x%02x", mss::c_str(iv_dimm), l_attrs_dimm_bc_1x[iv_port_index][iv_dimm_index] );
948- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_F0BC1x, iv_mcs, l_attrs_dimm_bc_1x) );
949-
950-
951-fapi_try_exit:
952- return fapi2::current_err;
953-}
954-
955-///
956-/// @brief Determines and sets DIMM BC6x
957-/// @return fapi2::FAPI2_RC_SUCCESS if okay
958-///
959-fapi2::ReturnCode eff_lrdimm::dimm_f0bc6x()
960-{
961- uint8_t l_attrs_dimm_bc_6x[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
962-
963- // Retrieve MCS attribute data
964- FAPI_TRY( eff_dimm_ddr4_f0bc6x(iv_mcs, &l_attrs_dimm_bc_6x[0][0]) );
965-
966- // Frequency encoding is the same as rc3x, so reusing here
967- switch(iv_freq)
968- {
969- case fapi2::ENUM_ATTR_MSS_FREQ_MT1866:
970- l_attrs_dimm_bc_6x[iv_port_index][iv_dimm_index] = rc3x_encode::MT1860_TO_MT1880;
971- break;
972-
973- case fapi2::ENUM_ATTR_MSS_FREQ_MT2133:
974- l_attrs_dimm_bc_6x[iv_port_index][iv_dimm_index] = rc3x_encode::MT2120_TO_MT2140;
975- break;
976-
977- case fapi2::ENUM_ATTR_MSS_FREQ_MT2400:
978- l_attrs_dimm_bc_6x[iv_port_index][iv_dimm_index] = rc3x_encode::MT2380_TO_MT2400;
979- break;
980-
981- case fapi2::ENUM_ATTR_MSS_FREQ_MT2666:
982- l_attrs_dimm_bc_6x[iv_port_index][iv_dimm_index] = rc3x_encode::MT2660_TO_MT2680;
983- break;
984-
985- default:
986- FAPI_ASSERT( false,
987- fapi2::MSS_INVALID_FREQ_RC()
988- .set_FREQ(iv_freq)
989- .set_RC_NUM(F0BC6X)
990- .set_DIMM_TARGET(iv_dimm),
991- "%s: Invalid frequency for BC_6X encoding received: %d",
992- mss::c_str(iv_dimm),
993- iv_freq);
994- break;
995- }
996-
997- FAPI_INF( "%s: F0BC6X setting: 0x%02x", mss::c_str(iv_dimm), l_attrs_dimm_bc_6x[iv_port_index][iv_dimm_index] );
998- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_F0BC6x, iv_mcs, l_attrs_dimm_bc_6x) );
999-
1000-
1001-fapi_try_exit:
1002- return fapi2::current_err;
1003-}
1004-
1005-///
1006-/// @brief Determines and sets DIMM F2BCEx
1007-/// @return fapi2::FAPI2_RC_SUCCESS if okay
1008-///
1009-fapi2::ReturnCode eff_lrdimm::dimm_f2bcex()
1010-{
1011- uint8_t l_attrs_dimm_f2bcex[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
1012-
1013- // Retrieve MCS attribute data
1014- FAPI_TRY( eff_dimm_ddr4_f2bcex(iv_mcs, &l_attrs_dimm_f2bcex[0][0]) );
1015-
1016- // Setup to default as we want to be in runtime mode (not DFE mode)
1017- l_attrs_dimm_f2bcex[iv_port_index][iv_dimm_index] = 0;
1018-
1019- FAPI_INF( "%s: F2BCEX setting: 0x%02x", mss::c_str(iv_dimm), l_attrs_dimm_f2bcex[iv_port_index][iv_dimm_index] );
1020- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_F2BCEx, iv_mcs, l_attrs_dimm_f2bcex) );
1021-
1022-
1023-fapi_try_exit:
1024- return fapi2::current_err;
1025-}
1026-
1027-///
1028-/// @brief Determines and sets DIMM F5BC5x
1029-/// @return fapi2::FAPI2_RC_SUCCESS if okay
1030-///
1031-fapi2::ReturnCode eff_lrdimm::dimm_f5bc5x()
1032-{
1033- // Taken from DDR4 (this attribute is DDR4 only) spec MRS6 section VrefDQ training: values table
1034- constexpr uint8_t JEDEC_MAX_TRAIN_VALUE = 0b00110010;
1035-
1036- // Gets the JEDEC VREFDQ range and value
1037- fapi2::buffer<uint8_t> l_train_value;
1038- fapi2::buffer<uint8_t> l_train_range;
1039- uint8_t l_attrs_dimm_f5bc5x[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
1040-
1041- // Retrieve MCS attribute data
1042- FAPI_TRY( eff_dimm_ddr4_f5bc5x(iv_mcs, &l_attrs_dimm_f5bc5x[0][0]) );
1043- FAPI_TRY(mss::get_vpd_wr_vref_range_and_value(iv_dimm, l_train_range, l_train_value));
1044-
1045- FAPI_ASSERT(l_train_value <= JEDEC_MAX_TRAIN_VALUE,
1046- fapi2::MSS_INVALID_VPD_VREF_DRAM_WR_RANGE()
1047- .set_MAX(JEDEC_MAX_TRAIN_VALUE)
1048- .set_VALUE(l_train_value)
1049- .set_MCS_TARGET(iv_mcs),
1050- "%s VPD DRAM VREF value out of range max 0x%02x value 0x%02x", mss::c_str(iv_dimm),
1051- JEDEC_MAX_TRAIN_VALUE, l_train_value );
1052-
1053- // F5BC5x is just the VREF training range
1054- l_attrs_dimm_f5bc5x[iv_port_index][iv_dimm_index] = l_train_value;
1055-
1056- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_F5BC5x, iv_mcs, l_attrs_dimm_f5bc5x),
1057- "Failed setting attribute for ATTR_EFF_DIMM_DDR4_F5BC5x");
1058-
1059-fapi_try_exit:
1060- return fapi2::current_err;
1061-}
1062-
1063-///
1064-/// @brief Determines and sets DIMM F5BC6x
1065-/// @return fapi2::FAPI2_RC_SUCCESS if okay
1066-///
1067-// TODO:RTC200577 Update LRDIMM termination settings for dual drop and 4 rank DIMM's
1068-fapi2::ReturnCode eff_lrdimm::dimm_f5bc6x()
1069-{
1070- constexpr uint8_t VREF_73PERCENT = 0x14;
1071- uint8_t l_attrs_dimm_f5bc6x[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
1072-
1073- // Retrieve MCS attribute data
1074- FAPI_TRY( eff_dimm_ddr4_f5bc6x(iv_mcs, &l_attrs_dimm_f5bc6x[0][0]) );
1075-
1076- // F5BC6x is just the VREF training range
1077- l_attrs_dimm_f5bc6x[iv_port_index][iv_dimm_index] = VREF_73PERCENT;
1078-
1079- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_F5BC6x, iv_mcs, l_attrs_dimm_f5bc6x),
1080- "Failed setting attribute for ATTR_EFF_DIMM_DDR4_F5BC6x");
1081-
1082-fapi_try_exit:
1083- return fapi2::current_err;
1084-}
1085-
1086-///
1087-/// @brief Determines and sets DIMM F6BC4x
1088-/// @return fapi2::FAPI2_RC_SUCCESS if okay
1089-///
1090-fapi2::ReturnCode eff_lrdimm::dimm_f6bc4x()
1091-{
1092- constexpr uint64_t WR_VREFDQ_BIT = 6;
1093- constexpr uint64_t RD_VREFDQ_BIT = 5;
1094-
1095- uint8_t l_attrs_dimm_f6bc4x[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {};
1096- uint8_t l_buffer_rd_vref_range = 0;
1097- uint8_t l_buffer_wr_vref_range = 0;
1098- uint8_t l_wr_vref_value = 0; // Used in F5BC5x, but we need it for a helper function
1099- fapi2::buffer<uint8_t> l_temp;
1100-
1101- // Retrieve MCS attribute data
1102- FAPI_TRY( eff_dimm_ddr4_f6bc4x(iv_mcs, &l_attrs_dimm_f6bc4x[0][0]) );
1103-
1104- // Gets the WR VREF range
1105- FAPI_TRY( get_vpd_wr_vref_range_and_value(iv_dimm, l_buffer_wr_vref_range, l_wr_vref_value) );
1106-
1107- // Gets the RD VREF range
1108- FAPI_TRY( iv_spd_decoder.data_buffer_vref_dq_range(l_buffer_rd_vref_range) );
1109-
1110- // Setup to default as we want to be in runtime mode
1111- l_temp.writeBit<WR_VREFDQ_BIT>(l_buffer_wr_vref_range)
1112- .writeBit<RD_VREFDQ_BIT>(l_buffer_rd_vref_range);
1113- l_attrs_dimm_f6bc4x[iv_port_index][iv_dimm_index] = l_temp;
1114-
1115- FAPI_INF( "%s: F6BC4X setting: 0x%02x", mss::c_str(iv_dimm), l_attrs_dimm_f6bc4x[iv_port_index][iv_dimm_index] );
1116- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_F6BC4x, iv_mcs, l_attrs_dimm_f6bc4x) );
1117-
1118-
1119-fapi_try_exit:
1120- return fapi2::current_err;
1121-}
1122-
1123-///
1124-/// @brief Determines & sets effective config for DRAM output driver impedance control
1125-/// @return fapi2::FAPI2_RC_SUCCESS if okay
1126-///
1127-// TODO:RTC200577 Update LRDIMM termination settings for dual drop and 4 rank DIMM's
1128-fapi2::ReturnCode eff_lrdimm::dram_odic()
1129-{
1130- uint8_t l_dram_odic[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
1131- FAPI_TRY( eff_dram_odic(iv_mcs, &l_dram_odic[0][0][0]));
1132-
1133- // Updates DRAM ODIC with the VPD value
1134- for(uint8_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank)
1135- {
1136- // JEDEC setting - taken from SI spreadsheet
1137- l_dram_odic[iv_port_index][iv_dimm_index][l_rank] = fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM34;
1138- }
1139-
1140- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_ODIC, iv_mcs, l_dram_odic) );
1141-
1142-fapi_try_exit:
1143- return fapi2::current_err;
1144-}
1145-
1146 ///
1147 /// @brief Grab the VPD blobs and decode into attributes
1148 /// @param[in] i_target FAPI2 target (MCS)
1149@@ -5881,116 +5562,4 @@ fapi2::ReturnCode eff_dimm::phy_seq_refresh()
1150 iv_mcs,
1151 UINT8_VECTOR_TO_1D_ARRAY(l_phy_seq_ref_enable, PORTS_PER_MCS));
1152 }
1153-
1154-///
1155-/// @brief Determines & sets effective ODT write values
1156-/// @return fapi2::FAPI2_RC_SUCCESS if okay
1157-///
1158-fapi2::ReturnCode eff_rdimm::odt_wr()
1159-{
1160- uint8_t l_mcs_attr[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
1161- uint8_t l_vpd_odt[MAX_RANK_PER_DIMM];
1162-
1163- // Gets the VPD value
1164- FAPI_TRY( mss::vpd_mt_odt_wr(iv_dimm, &(l_vpd_odt[0])));
1165- FAPI_TRY( eff_odt_wr( iv_mcs, &(l_mcs_attr[0][0][0])) );
1166-
1167-
1168- memcpy(&(l_mcs_attr[iv_port_index][iv_dimm_index][0]), l_vpd_odt, MAX_RANK_PER_DIMM);
1169-
1170- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_EFF_ODT_WR, iv_mcs, l_mcs_attr) );
1171-
1172-fapi_try_exit:
1173- return fapi2::current_err;
1174-}
1175-
1176-///
1177-/// @brief Determines & sets effective ODT write values
1178-/// @return fapi2::FAPI2_RC_SUCCESS if okay
1179-///
1180-fapi2::ReturnCode eff_lrdimm::odt_wr()
1181-{
1182- constexpr uint8_t ODT_2R_1DROP_VALUES[MAX_RANK_PER_DIMM] =
1183- {
1184- 0x40,
1185- 0x80,
1186- 0x00,
1187- 0x00,
1188- };
1189- uint8_t l_mcs_attr[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
1190- uint8_t l_vpd_odt[MAX_RANK_PER_DIMM];
1191-
1192- // Gets the VPD value
1193- FAPI_TRY( mss::vpd_mt_odt_wr(iv_dimm, &(l_vpd_odt[0])));
1194- FAPI_TRY( eff_odt_wr( iv_mcs, &(l_mcs_attr[0][0][0])) );
1195-
1196- // Loops through and sets/updates all ranks
1197- for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank)
1198- {
1199- // TODO:RTC200577 Update LRDIMM termination settings for dual drop and 4 rank DIMM's
1200- // So, here we do a bitwise or of our LR settings and our VPD settings
1201- // The VPD contains the host <-> buffer settings
1202- // The constant contains the buffer <-> DRAM
1203- // Due to how the ODT functions, we need to or them
1204- l_mcs_attr[iv_port_index][iv_dimm_index][l_rank] = l_vpd_odt[l_rank] | ODT_2R_1DROP_VALUES[l_rank];
1205- }
1206-
1207- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_EFF_ODT_WR, iv_mcs, l_mcs_attr) );
1208-
1209-fapi_try_exit:
1210- return fapi2::current_err;
1211-}
1212-
1213-///
1214-/// @brief Determines & sets effective ODT read values
1215-/// @return fapi2::FAPI2_RC_SUCCESS if okay
1216-///
1217-fapi2::ReturnCode eff_rdimm::odt_rd()
1218-{
1219- uint8_t l_mcs_attr[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
1220- uint8_t l_vpd_odt[MAX_RANK_PER_DIMM];
1221-
1222- // Gets the VPD value
1223- FAPI_TRY( mss::vpd_mt_odt_rd(iv_dimm, &(l_vpd_odt[0])));
1224- FAPI_TRY( eff_odt_rd( iv_mcs, &(l_mcs_attr[0][0][0])) );
1225-
1226-
1227- memcpy(&(l_mcs_attr[iv_port_index][iv_dimm_index][0]), l_vpd_odt, MAX_RANK_PER_DIMM);
1228-
1229- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_EFF_ODT_RD, iv_mcs, l_mcs_attr) );
1230-
1231-fapi_try_exit:
1232- return fapi2::current_err;
1233-}
1234-
1235-///
1236-/// @brief Determines & sets effective ODT read values
1237-/// @return fapi2::FAPI2_RC_SUCCESS if okay
1238-///
1239-fapi2::ReturnCode eff_lrdimm::odt_rd()
1240-{
1241- uint8_t l_mcs_attr[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {};
1242- uint8_t l_vpd_odt[MAX_RANK_PER_DIMM];
1243-
1244- // Gets the VPD value
1245- FAPI_TRY( mss::vpd_mt_odt_rd(iv_dimm, &(l_vpd_odt[0])));
1246- FAPI_TRY( eff_odt_rd( iv_mcs, &(l_mcs_attr[0][0][0])) );
1247-
1248- // Loops through and sets/updates all ranks
1249- for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank)
1250- {
1251- // TODO:RTC200577 Update LRDIMM termination settings for dual drop and 4 rank DIMM's
1252- // So, here we do a bitwise or of our LR settings and our VPD settings
1253- // The VPD contains the host <-> buffer settings
1254- // The constant contains the buffer <-> DRAM
1255- // Due to how the ODT functions, we need to or them
1256- l_mcs_attr[iv_port_index][iv_dimm_index][l_rank] = l_vpd_odt[l_rank] | 0x00;
1257- }
1258-
1259- FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_EFF_ODT_RD, iv_mcs, l_mcs_attr) );
1260-
1261-fapi_try_exit:
1262- return fapi2::current_err;
1263-}
1264-
1265 }//mss
1266diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H
1267index 693e14a8b0ca..7e33c0bdb1cb 100644
1268--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H
1269+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H
1270@@ -290,12 +290,6 @@ class eff_dimm
1271 ///
1272 fapi2::ReturnCode dram_dqs_time();
1273
1274- ///
1275- /// @brief Determines & sets effective config for DRAM output driver impedance control
1276- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1277- ///
1278- virtual fapi2::ReturnCode dram_odic() = 0;
1279-
1280 ///
1281 /// @brief Determines & sets effective config for tCCD_L
1282 /// @return fapi2::FAPI2_RC_SUCCESS if okay
1283@@ -534,7 +528,7 @@ class eff_dimm
1284 /// @brief Determines & sets effective config for Vref DQ Train Value and Range
1285 /// @return fapi2::FAPI2_RC_SUCCESS if okay
1286 ///
1287- virtual fapi2::ReturnCode vref_dq_train_value_and_range();
1288+ fapi2::ReturnCode vref_dq_train_value_and_range();
1289
1290 ///
1291 /// @brief Determines & sets effective config for Vref DQ Train Enable
1292@@ -571,18 +565,6 @@ class eff_dimm
1293 /// @return fapi2::FAPI2_RC_SUCCESS if okay
1294 ///
1295 fapi2::ReturnCode odt_input_buffer();
1296-
1297- ///
1298- /// @brief Determines & sets effective ODT write values
1299- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1300- ///
1301- virtual fapi2::ReturnCode odt_wr() = 0;
1302-
1303- ///
1304- /// @brief Determines & sets effective ODT read values
1305- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1306- ///
1307- virtual fapi2::ReturnCode odt_rd() = 0;
1308 ///
1309 /// @brief Determines & sets effective config for data_mask
1310 /// @return fapi2::FAPI2_RC_SUCCESS if okay
1311@@ -908,12 +890,6 @@ class eff_dimm
1312 ///
1313 virtual fapi2::ReturnCode dimm_bc05() = 0;
1314
1315- ///
1316- /// @brief Determines and sets DIMM BC06
1317- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1318- ///
1319- virtual fapi2::ReturnCode dimm_bc06() = 0;
1320-
1321 ///
1322 /// @brief Determines and sets DIMM BC07
1323 /// @return fapi2::FAPI2_RC_SUCCESS if okay
1324@@ -969,43 +945,6 @@ class eff_dimm
1325 ///
1326 virtual fapi2::ReturnCode dimm_bc0f() = 0;
1327
1328- ///
1329- /// @brief Determines and sets DIMM F0BC1x
1330- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1331- ///
1332- virtual fapi2::ReturnCode dimm_f0bc1x() = 0;
1333-
1334- ///
1335- /// @brief Determines and sets DIMM F0BC6x
1336- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1337- ///
1338- virtual fapi2::ReturnCode dimm_f0bc6x() = 0;
1339-
1340- ///
1341- /// @brief Determines and sets DIMM F2BCEx
1342- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1343- ///
1344- virtual fapi2::ReturnCode dimm_f2bcex() = 0;
1345-
1346- ///
1347- /// @brief Determines and sets DIMM F5BC5x
1348- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1349- ///
1350- virtual fapi2::ReturnCode dimm_f5bc5x() = 0;
1351-
1352- ///
1353- /// @brief Determines and sets DIMM F5BC6x
1354- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1355- ///
1356- virtual fapi2::ReturnCode dimm_f5bc6x() = 0;
1357-
1358-
1359- ///
1360- /// @brief Determines and sets DIMM F6BC4x
1361- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1362- ///
1363- virtual fapi2::ReturnCode dimm_f6bc4x() = 0;
1364-
1365 private:
1366
1367 ///
1368@@ -1076,25 +1015,6 @@ class eff_lrdimm : public eff_dimm
1369 ///
1370 virtual ~eff_lrdimm() = default;
1371
1372-
1373- ///
1374- /// @brief Determines & sets effective config for Vref DQ Train Value and Range
1375- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1376- ///
1377- virtual fapi2::ReturnCode vref_dq_train_value_and_range() final;
1378-
1379- ///
1380- /// @brief Determines & sets effective ODT write values
1381- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1382- ///
1383- virtual fapi2::ReturnCode odt_wr() final;
1384-
1385- ///
1386- /// @brief Determines & sets effective ODT read values
1387- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1388- ///
1389- virtual fapi2::ReturnCode odt_rd() final;
1390-
1391 ///
1392 /// @brief Sets the RTT_NOM value from SPD
1393 /// @return fapi2::FAPI2_RC_SUCCESS if okay
1394@@ -1116,12 +1036,6 @@ class eff_lrdimm : public eff_dimm
1395 ///
1396 virtual fapi2::ReturnCode dram_rtt_park() final;
1397
1398- ///
1399- /// @brief Determines & sets effective config for DRAM output driver impedance control
1400- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1401- ///
1402- virtual fapi2::ReturnCode dram_odic() final;
1403-
1404 ///
1405 /// @brief Determines and sets DIMM BC00
1406 /// @return fapi2::FAPI2_RC_SUCCESS if okay
1407@@ -1158,12 +1072,6 @@ class eff_lrdimm : public eff_dimm
1408 ///
1409 virtual fapi2::ReturnCode dimm_bc05() final;
1410
1411- ///
1412- /// @brief Determines and sets DIMM BC09
1413- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1414- ///
1415- virtual fapi2::ReturnCode dimm_bc06() final;
1416-
1417 ///
1418 /// @brief Determines and sets DIMM BC07
1419 /// @return fapi2::FAPI2_RC_SUCCESS if okay
1420@@ -1217,42 +1125,6 @@ class eff_lrdimm : public eff_dimm
1421 /// @return fapi2::FAPI2_RC_SUCCESS if okay
1422 ///
1423 virtual fapi2::ReturnCode dimm_bc0f() final;
1424-
1425- ///
1426- /// @brief Determines and sets DIMM F0BC1x
1427- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1428- ///
1429- virtual fapi2::ReturnCode dimm_f0bc1x() final;
1430-
1431- ///
1432- /// @brief Determines and sets DIMM F0BC6x
1433- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1434- ///
1435- virtual fapi2::ReturnCode dimm_f0bc6x() final;
1436-
1437- ///
1438- /// @brief Determines and sets DIMM F2BCex
1439- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1440- ///
1441- virtual fapi2::ReturnCode dimm_f2bcex() final;
1442-
1443- ///
1444- /// @brief Determines and sets DIMM F5BC5x
1445- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1446- ///
1447- virtual fapi2::ReturnCode dimm_f5bc5x() final;
1448-
1449- ///
1450- /// @brief Determines and sets DIMM F5BC6x
1451- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1452- ///
1453- virtual fapi2::ReturnCode dimm_f5bc6x() final;
1454-
1455- ///
1456- /// @brief Determines and sets DIMM F6BC4x
1457- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1458- ///
1459- virtual fapi2::ReturnCode dimm_f6bc4x() final;
1460 };
1461
1462 ///
1463@@ -1397,18 +1269,6 @@ class eff_rdimm : public eff_dimm
1464 ///
1465 ~eff_rdimm() = default;
1466
1467- ///
1468- /// @brief Determines & sets effective ODT write values
1469- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1470- ///
1471- virtual fapi2::ReturnCode odt_wr() final;
1472-
1473- ///
1474- /// @brief Determines & sets effective ODT read values
1475- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1476- ///
1477- virtual fapi2::ReturnCode odt_rd() final;
1478-
1479 ///
1480 /// @brief Sets the RTT_NOM value from SPD
1481 /// @return fapi2::FAPI2_RC_SUCCESS if okay
1482@@ -1430,12 +1290,6 @@ class eff_rdimm : public eff_dimm
1483 ///
1484 fapi2::ReturnCode dram_rtt_park() final;
1485
1486- ///
1487- /// @brief Determines & sets effective config for DRAM output driver impedance control
1488- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1489- ///
1490- virtual fapi2::ReturnCode dram_odic() final;
1491-
1492 ///
1493 /// @brief Determines and sets DIMM BC00
1494 /// @return fapi2::FAPI2_RC_SUCCESS if okay
1495@@ -1490,15 +1344,6 @@ class eff_rdimm : public eff_dimm
1496 return fapi2::FAPI2_RC_SUCCESS;
1497 }
1498
1499- ///
1500- /// @brief Determines and sets DIMM BC06
1501- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1502- ///
1503- fapi2::ReturnCode dimm_bc06() final
1504- {
1505- return fapi2::FAPI2_RC_SUCCESS;
1506- }
1507-
1508 ///
1509 /// @brief Determines and sets DIMM BC07
1510 /// @return fapi2::FAPI2_RC_SUCCESS if okay
1511@@ -1579,61 +1424,6 @@ class eff_rdimm : public eff_dimm
1512 {
1513 return fapi2::FAPI2_RC_SUCCESS;
1514 }
1515-
1516- ///
1517- /// @brief Determines and sets DIMM F0BC1x
1518- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1519- ///
1520- virtual fapi2::ReturnCode dimm_f0bc1x() final
1521- {
1522- return fapi2::FAPI2_RC_SUCCESS;
1523- }
1524-
1525- ///
1526- /// @brief Determines and sets DIMM F0BC6x
1527- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1528- ///
1529- virtual fapi2::ReturnCode dimm_f0bc6x() final
1530- {
1531- return fapi2::FAPI2_RC_SUCCESS;
1532- }
1533-
1534- ///
1535- /// @brief Determines and sets DIMM F2BCEx
1536- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1537- ///
1538- virtual fapi2::ReturnCode dimm_f2bcex() final
1539- {
1540- return fapi2::FAPI2_RC_SUCCESS;
1541- }
1542-
1543- ///
1544- /// @brief Determines and sets DIMM F5BC5x
1545- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1546- ///
1547- virtual fapi2::ReturnCode dimm_f5bc5x() final
1548- {
1549- return fapi2::FAPI2_RC_SUCCESS;
1550- }
1551-
1552- ///
1553- /// @brief Determines and sets DIMM F5BC6x
1554- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1555- ///
1556- virtual fapi2::ReturnCode dimm_f5bc6x() final
1557- {
1558- return fapi2::FAPI2_RC_SUCCESS;
1559- }
1560-
1561-
1562- ///
1563- /// @brief Determines and sets DIMM F6BC4x
1564- /// @return fapi2::FAPI2_RC_SUCCESS if okay
1565- ///
1566- virtual fapi2::ReturnCode dimm_f6bc4x() final
1567- {
1568- return fapi2::FAPI2_RC_SUCCESS;
1569- }
1570 };
1571 }//mss
1572
1573diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
1574index 31dfa4592ed3..3660561c03ad 100644
1575--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
1576+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
1577@@ -8569,90 +8569,6 @@ fapi_try_exit:
1578 return fapi2::current_err;
1579 }
1580
1581-///
1582-/// @brief ATTR_EFF_DIMM_DDR4_BC06 getter
1583-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
1584-/// @param[out] ref to the value uint8_t
1585-/// @note Generated by gen_accessors.pl generateParameters (F)
1586-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1587-/// @note F0BCW06 Command Space Control
1588-/// Word
1589-///
1590-inline fapi2::ReturnCode eff_dimm_ddr4_bc06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
1591-{
1592- uint8_t l_value[2][2];
1593- auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
1594- auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>();
1595-
1596- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_BC06, l_mcs, l_value) );
1597- o_value = l_value[mss::index(l_mca)][mss::index(i_target)];
1598- return fapi2::current_err;
1599-
1600-fapi_try_exit:
1601- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_BC06: 0x%lx (target: %s)",
1602- uint64_t(fapi2::current_err), mss::c_str(i_target));
1603- return fapi2::current_err;
1604-}
1605-
1606-///
1607-/// @brief ATTR_EFF_DIMM_DDR4_BC06 getter
1608-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
1609-/// @param[out] uint8_t* memory to store the value
1610-/// @note Generated by gen_accessors.pl generateParameters (G)
1611-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1612-/// @note F0BCW06 Command Space Control
1613-/// Word
1614-///
1615-inline fapi2::ReturnCode eff_dimm_ddr4_bc06(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
1616-{
1617- if (o_array == nullptr)
1618- {
1619- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
1620- return fapi2::FAPI2_RC_INVALID_PARAMETER;
1621- }
1622-
1623- uint8_t l_value[2][2];
1624- auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>();
1625-
1626- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_BC06, l_mcs, l_value) );
1627- memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2);
1628- return fapi2::current_err;
1629-
1630-fapi_try_exit:
1631- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_BC06: 0x%lx (target: %s)",
1632- uint64_t(fapi2::current_err), mss::c_str(i_target));
1633- return fapi2::current_err;
1634-}
1635-
1636-///
1637-/// @brief ATTR_EFF_DIMM_DDR4_BC06 getter
1638-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
1639-/// @param[out] uint8_t* memory to store the value
1640-/// @note Generated by gen_accessors.pl generateParameters (H)
1641-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1642-/// @note F0BCW06 Command Space Control
1643-/// Word
1644-///
1645-inline fapi2::ReturnCode eff_dimm_ddr4_bc06(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
1646-{
1647- if (o_array == nullptr)
1648- {
1649- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
1650- return fapi2::FAPI2_RC_INVALID_PARAMETER;
1651- }
1652-
1653- uint8_t l_value[2][2];
1654-
1655- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_BC06, i_target, l_value) );
1656- memcpy(o_array, &l_value, 4);
1657- return fapi2::current_err;
1658-
1659-fapi_try_exit:
1660- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_BC06: 0x%lx (target: %s)",
1661- uint64_t(fapi2::current_err), mss::c_str(i_target));
1662- return fapi2::current_err;
1663-}
1664-
1665 ///
1666 /// @brief ATTR_EFF_DIMM_DDR4_BC07 getter
1667 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
1668@@ -9410,40 +9326,40 @@ fapi_try_exit:
1669 }
1670
1671 ///
1672-/// @brief ATTR_EFF_DIMM_DDR4_F0BC1x getter
1673+/// @brief ATTR_EFF_DIMM_DDR4_F5BC6x getter
1674 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
1675 /// @param[out] ref to the value uint8_t
1676 /// @note Generated by gen_accessors.pl generateParameters (F)
1677 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1678-/// @note F0BCW1x Buffer Configuration Control
1679+/// @note F5BCW6x DRAM Interface Vref Control
1680 /// Word
1681 ///
1682-inline fapi2::ReturnCode eff_dimm_ddr4_f0bc1x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
1683+inline fapi2::ReturnCode eff_dimm_ddr4_f5bc6x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
1684 {
1685 uint8_t l_value[2][2];
1686 auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
1687 auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>();
1688
1689- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F0BC1x, l_mcs, l_value) );
1690+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F5BC6x, l_mcs, l_value) );
1691 o_value = l_value[mss::index(l_mca)][mss::index(i_target)];
1692 return fapi2::current_err;
1693
1694 fapi_try_exit:
1695- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F0BC1x: 0x%lx (target: %s)",
1696+ FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F5BC6x: 0x%lx (target: %s)",
1697 uint64_t(fapi2::current_err), mss::c_str(i_target));
1698 return fapi2::current_err;
1699 }
1700
1701 ///
1702-/// @brief ATTR_EFF_DIMM_DDR4_F0BC1x getter
1703+/// @brief ATTR_EFF_DIMM_DDR4_F5BC6x getter
1704 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
1705 /// @param[out] uint8_t* memory to store the value
1706 /// @note Generated by gen_accessors.pl generateParameters (G)
1707 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1708-/// @note F0BCW1x Buffer Configuration Control
1709+/// @note F5BCW6x DRAM Interface Vref Control
1710 /// Word
1711 ///
1712-inline fapi2::ReturnCode eff_dimm_ddr4_f0bc1x(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
1713+inline fapi2::ReturnCode eff_dimm_ddr4_f5bc6x(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
1714 {
1715 if (o_array == nullptr)
1716 {
1717@@ -9454,26 +9370,26 @@ inline fapi2::ReturnCode eff_dimm_ddr4_f0bc1x(const fapi2::Target<fapi2::TARGET_
1718 uint8_t l_value[2][2];
1719 auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>();
1720
1721- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F0BC1x, l_mcs, l_value) );
1722+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F5BC6x, l_mcs, l_value) );
1723 memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2);
1724 return fapi2::current_err;
1725
1726 fapi_try_exit:
1727- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F0BC1x: 0x%lx (target: %s)",
1728+ FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F5BC6x: 0x%lx (target: %s)",
1729 uint64_t(fapi2::current_err), mss::c_str(i_target));
1730 return fapi2::current_err;
1731 }
1732
1733 ///
1734-/// @brief ATTR_EFF_DIMM_DDR4_F0BC1x getter
1735+/// @brief ATTR_EFF_DIMM_DDR4_F5BC6x getter
1736 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
1737 /// @param[out] uint8_t* memory to store the value
1738 /// @note Generated by gen_accessors.pl generateParameters (H)
1739 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1740-/// @note F0BCW1x Buffer Configuration Control
1741+/// @note F5BCW6x DRAM Interface Vref Control
1742 /// Word
1743 ///
1744-inline fapi2::ReturnCode eff_dimm_ddr4_f0bc1x(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
1745+inline fapi2::ReturnCode eff_dimm_ddr4_f5bc6x(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
1746 {
1747 if (o_array == nullptr)
1748 {
1749@@ -9483,51 +9399,51 @@ inline fapi2::ReturnCode eff_dimm_ddr4_f0bc1x(const fapi2::Target<fapi2::TARGET_
1750
1751 uint8_t l_value[2][2];
1752
1753- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F0BC1x, i_target, l_value) );
1754+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F5BC6x, i_target, l_value) );
1755 memcpy(o_array, &l_value, 4);
1756 return fapi2::current_err;
1757
1758 fapi_try_exit:
1759- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F0BC1x: 0x%lx (target: %s)",
1760+ FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F5BC6x: 0x%lx (target: %s)",
1761 uint64_t(fapi2::current_err), mss::c_str(i_target));
1762 return fapi2::current_err;
1763 }
1764
1765 ///
1766-/// @brief ATTR_EFF_DIMM_DDR4_F0BC6x getter
1767+/// @brief ATTR_EFF_DIMM_DDR4_F6BC4x getter
1768 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
1769 /// @param[out] ref to the value uint8_t
1770 /// @note Generated by gen_accessors.pl generateParameters (F)
1771 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1772-/// @note F0BCW6x Fine Granularity Frequency Operating Speed Control
1773+/// @note F6BCW4x Buffer Training Configuration Control
1774 /// Word
1775 ///
1776-inline fapi2::ReturnCode eff_dimm_ddr4_f0bc6x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
1777+inline fapi2::ReturnCode eff_dimm_ddr4_f6bc4x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
1778 {
1779 uint8_t l_value[2][2];
1780 auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
1781 auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>();
1782
1783- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F0BC6x, l_mcs, l_value) );
1784+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F6BC4x, l_mcs, l_value) );
1785 o_value = l_value[mss::index(l_mca)][mss::index(i_target)];
1786 return fapi2::current_err;
1787
1788 fapi_try_exit:
1789- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F0BC6x: 0x%lx (target: %s)",
1790+ FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F6BC4x: 0x%lx (target: %s)",
1791 uint64_t(fapi2::current_err), mss::c_str(i_target));
1792 return fapi2::current_err;
1793 }
1794
1795 ///
1796-/// @brief ATTR_EFF_DIMM_DDR4_F0BC6x getter
1797+/// @brief ATTR_EFF_DIMM_DDR4_F6BC4x getter
1798 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
1799 /// @param[out] uint8_t* memory to store the value
1800 /// @note Generated by gen_accessors.pl generateParameters (G)
1801 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1802-/// @note F0BCW6x Fine Granularity Frequency Operating Speed Control
1803+/// @note F6BCW4x Buffer Training Configuration Control
1804 /// Word
1805 ///
1806-inline fapi2::ReturnCode eff_dimm_ddr4_f0bc6x(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
1807+inline fapi2::ReturnCode eff_dimm_ddr4_f6bc4x(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
1808 {
1809 if (o_array == nullptr)
1810 {
1811@@ -9538,26 +9454,26 @@ inline fapi2::ReturnCode eff_dimm_ddr4_f0bc6x(const fapi2::Target<fapi2::TARGET_
1812 uint8_t l_value[2][2];
1813 auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>();
1814
1815- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F0BC6x, l_mcs, l_value) );
1816+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F6BC4x, l_mcs, l_value) );
1817 memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2);
1818 return fapi2::current_err;
1819
1820 fapi_try_exit:
1821- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F0BC6x: 0x%lx (target: %s)",
1822+ FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F6BC4x: 0x%lx (target: %s)",
1823 uint64_t(fapi2::current_err), mss::c_str(i_target));
1824 return fapi2::current_err;
1825 }
1826
1827 ///
1828-/// @brief ATTR_EFF_DIMM_DDR4_F0BC6x getter
1829+/// @brief ATTR_EFF_DIMM_DDR4_F6BC4x getter
1830 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
1831 /// @param[out] uint8_t* memory to store the value
1832 /// @note Generated by gen_accessors.pl generateParameters (H)
1833 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1834-/// @note F0BCW6x Fine Granularity Frequency Operating Speed Control
1835+/// @note F6BCW4x Buffer Training Configuration Control
1836 /// Word
1837 ///
1838-inline fapi2::ReturnCode eff_dimm_ddr4_f0bc6x(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
1839+inline fapi2::ReturnCode eff_dimm_ddr4_f6bc4x(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
1840 {
1841 if (o_array == nullptr)
1842 {
1843@@ -9567,165 +9483,79 @@ inline fapi2::ReturnCode eff_dimm_ddr4_f0bc6x(const fapi2::Target<fapi2::TARGET_
1844
1845 uint8_t l_value[2][2];
1846
1847- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F0BC6x, i_target, l_value) );
1848+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F6BC4x, i_target, l_value) );
1849 memcpy(o_array, &l_value, 4);
1850 return fapi2::current_err;
1851
1852 fapi_try_exit:
1853- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F0BC6x: 0x%lx (target: %s)",
1854- uint64_t(fapi2::current_err), mss::c_str(i_target));
1855- return fapi2::current_err;
1856-}
1857-
1858-///
1859-/// @brief ATTR_EFF_DIMM_DDR4_F2BCEx getter
1860-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
1861-/// @param[out] ref to the value uint8_t
1862-/// @note Generated by gen_accessors.pl generateParameters (F)
1863-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1864-/// @note F2BCWEx Host Interface DFE Programming Control
1865-/// Word
1866-///
1867-inline fapi2::ReturnCode eff_dimm_ddr4_f2bcex(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
1868-{
1869- uint8_t l_value[2][2];
1870- auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
1871- auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>();
1872-
1873- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F2BCEx, l_mcs, l_value) );
1874- o_value = l_value[mss::index(l_mca)][mss::index(i_target)];
1875- return fapi2::current_err;
1876-
1877-fapi_try_exit:
1878- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F2BCEx: 0x%lx (target: %s)",
1879+ FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F6BC4x: 0x%lx (target: %s)",
1880 uint64_t(fapi2::current_err), mss::c_str(i_target));
1881 return fapi2::current_err;
1882 }
1883
1884 ///
1885-/// @brief ATTR_EFF_DIMM_DDR4_F2BCEx getter
1886+/// @brief ATTR_EFF_DRAM_TDQS getter
1887 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
1888-/// @param[out] uint8_t* memory to store the value
1889-/// @note Generated by gen_accessors.pl generateParameters (G)
1890-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1891-/// @note F2BCWEx Host Interface DFE Programming Control
1892-/// Word
1893-///
1894-inline fapi2::ReturnCode eff_dimm_ddr4_f2bcex(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
1895-{
1896- if (o_array == nullptr)
1897- {
1898- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
1899- return fapi2::FAPI2_RC_INVALID_PARAMETER;
1900- }
1901-
1902- uint8_t l_value[2][2];
1903- auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>();
1904-
1905- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F2BCEx, l_mcs, l_value) );
1906- memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2);
1907- return fapi2::current_err;
1908-
1909-fapi_try_exit:
1910- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F2BCEx: 0x%lx (target: %s)",
1911- uint64_t(fapi2::current_err), mss::c_str(i_target));
1912- return fapi2::current_err;
1913-}
1914-
1915-///
1916-/// @brief ATTR_EFF_DIMM_DDR4_F2BCEx getter
1917-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
1918-/// @param[out] uint8_t* memory to store the value
1919-/// @note Generated by gen_accessors.pl generateParameters (H)
1920+/// @param[out] ref to the value uint8_t
1921+/// @note Generated by gen_accessors.pl generateParameters (D)
1922 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1923-/// @note F2BCWEx Host Interface DFE Programming Control
1924-/// Word
1925+/// @note TDQS. Used in various locations and is computed in mss_eff_cnfg. Each memory
1926+/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware
1927+/// notes:
1928+/// none
1929 ///
1930-inline fapi2::ReturnCode eff_dimm_ddr4_f2bcex(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
1931+inline fapi2::ReturnCode eff_dram_tdqs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
1932 {
1933- if (o_array == nullptr)
1934- {
1935- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
1936- return fapi2::FAPI2_RC_INVALID_PARAMETER;
1937- }
1938-
1939- uint8_t l_value[2][2];
1940+ uint8_t l_value[2];
1941
1942- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F2BCEx, i_target, l_value) );
1943- memcpy(o_array, &l_value, 4);
1944+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_TDQS, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
1945+ o_value = l_value[mss::index(i_target)];
1946 return fapi2::current_err;
1947
1948 fapi_try_exit:
1949- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F2BCEx: 0x%lx (target: %s)",
1950+ FAPI_ERR("failed accessing ATTR_EFF_DRAM_TDQS: 0x%lx (target: %s)",
1951 uint64_t(fapi2::current_err), mss::c_str(i_target));
1952 return fapi2::current_err;
1953 }
1954
1955 ///
1956-/// @brief ATTR_EFF_DIMM_DDR4_F5BC5x getter
1957+/// @brief ATTR_EFF_DRAM_TDQS getter
1958 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
1959 /// @param[out] ref to the value uint8_t
1960-/// @note Generated by gen_accessors.pl generateParameters (F)
1961+/// @note Generated by gen_accessors.pl generateParameters (D.1)
1962 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1963-/// @note F5BCW5x Host Interface Vref Control
1964-/// Word
1965+/// @note TDQS. Used in various locations and is computed in mss_eff_cnfg. Each memory
1966+/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware
1967+/// notes:
1968+/// none
1969 ///
1970-inline fapi2::ReturnCode eff_dimm_ddr4_f5bc5x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
1971+inline fapi2::ReturnCode eff_dram_tdqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
1972 {
1973- uint8_t l_value[2][2];
1974+ uint8_t l_value[2];
1975 auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
1976- auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>();
1977-
1978- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F5BC5x, l_mcs, l_value) );
1979- o_value = l_value[mss::index(l_mca)][mss::index(i_target)];
1980- return fapi2::current_err;
1981-
1982-fapi_try_exit:
1983- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F5BC5x: 0x%lx (target: %s)",
1984- uint64_t(fapi2::current_err), mss::c_str(i_target));
1985- return fapi2::current_err;
1986-}
1987-
1988-///
1989-/// @brief ATTR_EFF_DIMM_DDR4_F5BC5x getter
1990-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
1991-/// @param[out] uint8_t* memory to store the value
1992-/// @note Generated by gen_accessors.pl generateParameters (G)
1993-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
1994-/// @note F5BCW5x Host Interface Vref Control
1995-/// Word
1996-///
1997-inline fapi2::ReturnCode eff_dimm_ddr4_f5bc5x(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
1998-{
1999- if (o_array == nullptr)
2000- {
2001- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2002- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2003- }
2004-
2005- uint8_t l_value[2][2];
2006- auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>();
2007
2008- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F5BC5x, l_mcs, l_value) );
2009- memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2);
2010+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_TDQS, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
2011+ o_value = l_value[mss::index(l_mca)];
2012 return fapi2::current_err;
2013
2014 fapi_try_exit:
2015- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F5BC5x: 0x%lx (target: %s)",
2016+ FAPI_ERR("failed accessing ATTR_EFF_DRAM_TDQS: 0x%lx (target: %s)",
2017 uint64_t(fapi2::current_err), mss::c_str(i_target));
2018 return fapi2::current_err;
2019 }
2020
2021 ///
2022-/// @brief ATTR_EFF_DIMM_DDR4_F5BC5x getter
2023+/// @brief ATTR_EFF_DRAM_TDQS getter
2024 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
2025 /// @param[out] uint8_t* memory to store the value
2026-/// @note Generated by gen_accessors.pl generateParameters (H)
2027+/// @note Generated by gen_accessors.pl generateParameters (E)
2028 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2029-/// @note F5BCW5x Host Interface Vref Control
2030-/// Word
2031+/// @note TDQS. Used in various locations and is computed in mss_eff_cnfg. Each memory
2032+/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware
2033+/// notes:
2034+/// none
2035 ///
2036-inline fapi2::ReturnCode eff_dimm_ddr4_f5bc5x(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
2037+inline fapi2::ReturnCode eff_dram_tdqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
2038 {
2039 if (o_array == nullptr)
2040 {
2041@@ -9733,203 +9563,10 @@ inline fapi2::ReturnCode eff_dimm_ddr4_f5bc5x(const fapi2::Target<fapi2::TARGET_
2042 return fapi2::FAPI2_RC_INVALID_PARAMETER;
2043 }
2044
2045- uint8_t l_value[2][2];
2046-
2047- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F5BC5x, i_target, l_value) );
2048- memcpy(o_array, &l_value, 4);
2049- return fapi2::current_err;
2050-
2051-fapi_try_exit:
2052- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F5BC5x: 0x%lx (target: %s)",
2053- uint64_t(fapi2::current_err), mss::c_str(i_target));
2054- return fapi2::current_err;
2055-}
2056-
2057-///
2058-/// @brief ATTR_EFF_DIMM_DDR4_F5BC6x getter
2059-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
2060-/// @param[out] ref to the value uint8_t
2061-/// @note Generated by gen_accessors.pl generateParameters (F)
2062-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2063-/// @note F5BCW6x DRAM Interface Vref Control
2064-/// Word
2065-///
2066-inline fapi2::ReturnCode eff_dimm_ddr4_f5bc6x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
2067-{
2068- uint8_t l_value[2][2];
2069- auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
2070- auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>();
2071+ uint8_t l_value[2];
2072
2073- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F5BC6x, l_mcs, l_value) );
2074- o_value = l_value[mss::index(l_mca)][mss::index(i_target)];
2075- return fapi2::current_err;
2076-
2077-fapi_try_exit:
2078- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F5BC6x: 0x%lx (target: %s)",
2079- uint64_t(fapi2::current_err), mss::c_str(i_target));
2080- return fapi2::current_err;
2081-}
2082-
2083-///
2084-/// @brief ATTR_EFF_DIMM_DDR4_F5BC6x getter
2085-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
2086-/// @param[out] uint8_t* memory to store the value
2087-/// @note Generated by gen_accessors.pl generateParameters (G)
2088-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2089-/// @note F5BCW6x DRAM Interface Vref Control
2090-/// Word
2091-///
2092-inline fapi2::ReturnCode eff_dimm_ddr4_f5bc6x(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
2093-{
2094- if (o_array == nullptr)
2095- {
2096- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2097- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2098- }
2099-
2100- uint8_t l_value[2][2];
2101- auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>();
2102-
2103- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F5BC6x, l_mcs, l_value) );
2104- memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2);
2105- return fapi2::current_err;
2106-
2107-fapi_try_exit:
2108- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F5BC6x: 0x%lx (target: %s)",
2109- uint64_t(fapi2::current_err), mss::c_str(i_target));
2110- return fapi2::current_err;
2111-}
2112-
2113-///
2114-/// @brief ATTR_EFF_DIMM_DDR4_F5BC6x getter
2115-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
2116-/// @param[out] uint8_t* memory to store the value
2117-/// @note Generated by gen_accessors.pl generateParameters (H)
2118-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2119-/// @note F5BCW6x DRAM Interface Vref Control
2120-/// Word
2121-///
2122-inline fapi2::ReturnCode eff_dimm_ddr4_f5bc6x(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
2123-{
2124- if (o_array == nullptr)
2125- {
2126- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2127- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2128- }
2129-
2130- uint8_t l_value[2][2];
2131-
2132- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F5BC6x, i_target, l_value) );
2133- memcpy(o_array, &l_value, 4);
2134- return fapi2::current_err;
2135-
2136-fapi_try_exit:
2137- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F5BC6x: 0x%lx (target: %s)",
2138- uint64_t(fapi2::current_err), mss::c_str(i_target));
2139- return fapi2::current_err;
2140-}
2141-
2142-///
2143-/// @brief ATTR_EFF_DIMM_DDR4_F6BC4x getter
2144-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
2145-/// @param[out] ref to the value uint8_t
2146-/// @note Generated by gen_accessors.pl generateParameters (F)
2147-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2148-/// @note F6BCW4x Buffer Training Configuration Control
2149-/// Word
2150-///
2151-inline fapi2::ReturnCode eff_dimm_ddr4_f6bc4x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
2152-{
2153- uint8_t l_value[2][2];
2154- auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
2155- auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>();
2156-
2157- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F6BC4x, l_mcs, l_value) );
2158- o_value = l_value[mss::index(l_mca)][mss::index(i_target)];
2159- return fapi2::current_err;
2160-
2161-fapi_try_exit:
2162- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F6BC4x: 0x%lx (target: %s)",
2163- uint64_t(fapi2::current_err), mss::c_str(i_target));
2164- return fapi2::current_err;
2165-}
2166-
2167-///
2168-/// @brief ATTR_EFF_DIMM_DDR4_F6BC4x getter
2169-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
2170-/// @param[out] uint8_t* memory to store the value
2171-/// @note Generated by gen_accessors.pl generateParameters (G)
2172-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2173-/// @note F6BCW4x Buffer Training Configuration Control
2174-/// Word
2175-///
2176-inline fapi2::ReturnCode eff_dimm_ddr4_f6bc4x(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
2177-{
2178- if (o_array == nullptr)
2179- {
2180- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2181- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2182- }
2183-
2184- uint8_t l_value[2][2];
2185- auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>();
2186-
2187- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F6BC4x, l_mcs, l_value) );
2188- memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2);
2189- return fapi2::current_err;
2190-
2191-fapi_try_exit:
2192- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F6BC4x: 0x%lx (target: %s)",
2193- uint64_t(fapi2::current_err), mss::c_str(i_target));
2194- return fapi2::current_err;
2195-}
2196-
2197-///
2198-/// @brief ATTR_EFF_DIMM_DDR4_F6BC4x getter
2199-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
2200-/// @param[out] uint8_t* memory to store the value
2201-/// @note Generated by gen_accessors.pl generateParameters (H)
2202-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2203-/// @note F6BCW4x Buffer Training Configuration Control
2204-/// Word
2205-///
2206-inline fapi2::ReturnCode eff_dimm_ddr4_f6bc4x(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
2207-{
2208- if (o_array == nullptr)
2209- {
2210- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2211- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2212- }
2213-
2214- uint8_t l_value[2][2];
2215-
2216- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_DDR4_F6BC4x, i_target, l_value) );
2217- memcpy(o_array, &l_value, 4);
2218- return fapi2::current_err;
2219-
2220-fapi_try_exit:
2221- FAPI_ERR("failed accessing ATTR_EFF_DIMM_DDR4_F6BC4x: 0x%lx (target: %s)",
2222- uint64_t(fapi2::current_err), mss::c_str(i_target));
2223- return fapi2::current_err;
2224-}
2225-
2226-///
2227-/// @brief ATTR_EFF_DRAM_TDQS getter
2228-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
2229-/// @param[out] ref to the value uint8_t
2230-/// @note Generated by gen_accessors.pl generateParameters (D)
2231-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2232-/// @note TDQS. Used in various locations and is computed in mss_eff_cnfg. Each memory
2233-/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware
2234-/// notes:
2235-/// none
2236-///
2237-inline fapi2::ReturnCode eff_dram_tdqs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
2238-{
2239- uint8_t l_value[2];
2240-
2241- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_TDQS, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
2242- o_value = l_value[mss::index(i_target)];
2243+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_TDQS, i_target, l_value) );
2244+ memcpy(o_array, &l_value, 2);
2245 return fapi2::current_err;
2246
2247 fapi_try_exit:
2248@@ -9938,351 +9575,6 @@ fapi_try_exit:
2249 return fapi2::current_err;
2250 }
2251
2252-///
2253-/// @brief ATTR_EFF_DRAM_TDQS getter
2254-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
2255-/// @param[out] ref to the value uint8_t
2256-/// @note Generated by gen_accessors.pl generateParameters (D.1)
2257-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2258-/// @note TDQS. Used in various locations and is computed in mss_eff_cnfg. Each memory
2259-/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware
2260-/// notes:
2261-/// none
2262-///
2263-inline fapi2::ReturnCode eff_dram_tdqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
2264-{
2265- uint8_t l_value[2];
2266- auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
2267-
2268- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_TDQS, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
2269- o_value = l_value[mss::index(l_mca)];
2270- return fapi2::current_err;
2271-
2272-fapi_try_exit:
2273- FAPI_ERR("failed accessing ATTR_EFF_DRAM_TDQS: 0x%lx (target: %s)",
2274- uint64_t(fapi2::current_err), mss::c_str(i_target));
2275- return fapi2::current_err;
2276-}
2277-
2278-///
2279-/// @brief ATTR_EFF_DRAM_TDQS getter
2280-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
2281-/// @param[out] uint8_t* memory to store the value
2282-/// @note Generated by gen_accessors.pl generateParameters (E)
2283-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2284-/// @note TDQS. Used in various locations and is computed in mss_eff_cnfg. Each memory
2285-/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware
2286-/// notes:
2287-/// none
2288-///
2289-inline fapi2::ReturnCode eff_dram_tdqs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
2290-{
2291- if (o_array == nullptr)
2292- {
2293- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2294- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2295- }
2296-
2297- uint8_t l_value[2];
2298-
2299- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_TDQS, i_target, l_value) );
2300- memcpy(o_array, &l_value, 2);
2301- return fapi2::current_err;
2302-
2303-fapi_try_exit:
2304- FAPI_ERR("failed accessing ATTR_EFF_DRAM_TDQS: 0x%lx (target: %s)",
2305- uint64_t(fapi2::current_err), mss::c_str(i_target));
2306- return fapi2::current_err;
2307-}
2308-
2309-///
2310-/// @brief ATTR_EFF_DRAM_ODIC getter
2311-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
2312-/// @param[out] uint8_t* memory to store the value
2313-/// @note Generated by gen_accessors.pl generateParameters (A)
2314-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2315-/// @note DRAM output driver impedance control
2316-/// (ODIC)
2317-///
2318-inline fapi2::ReturnCode eff_dram_odic(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
2319-{
2320- if (o_array == nullptr)
2321- {
2322- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2323- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2324- }
2325-
2326- uint8_t l_value[2][2][4];
2327- auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
2328- auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>();
2329-
2330- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_ODIC, l_mcs, l_value) );
2331- memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4);
2332- return fapi2::current_err;
2333-
2334-fapi_try_exit:
2335- FAPI_ERR("failed accessing ATTR_EFF_DRAM_ODIC: 0x%lx (target: %s)",
2336- uint64_t(fapi2::current_err), mss::c_str(i_target));
2337- return fapi2::current_err;
2338-}
2339-
2340-///
2341-/// @brief ATTR_EFF_DRAM_ODIC getter
2342-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
2343-/// @param[out] uint8_t* memory to store the value
2344-/// @note Generated by gen_accessors.pl generateParameters (B)
2345-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2346-/// @note DRAM output driver impedance control
2347-/// (ODIC)
2348-///
2349-inline fapi2::ReturnCode eff_dram_odic(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
2350-{
2351- if (o_array == nullptr)
2352- {
2353- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2354- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2355- }
2356-
2357- uint8_t l_value[2][2][4];
2358- auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>();
2359-
2360- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_ODIC, l_mcs, l_value) );
2361- memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8);
2362- return fapi2::current_err;
2363-
2364-fapi_try_exit:
2365- FAPI_ERR("failed accessing ATTR_EFF_DRAM_ODIC: 0x%lx (target: %s)",
2366- uint64_t(fapi2::current_err), mss::c_str(i_target));
2367- return fapi2::current_err;
2368-}
2369-
2370-///
2371-/// @brief ATTR_EFF_DRAM_ODIC getter
2372-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
2373-/// @param[out] uint8_t* memory to store the value
2374-/// @note Generated by gen_accessors.pl generateParameters (C)
2375-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2376-/// @note DRAM output driver impedance control
2377-/// (ODIC)
2378-///
2379-inline fapi2::ReturnCode eff_dram_odic(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
2380-{
2381- if (o_array == nullptr)
2382- {
2383- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2384- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2385- }
2386-
2387- uint8_t l_value[2][2][4];
2388-
2389- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_ODIC, i_target, l_value) );
2390- memcpy(o_array, &l_value, 16);
2391- return fapi2::current_err;
2392-
2393-fapi_try_exit:
2394- FAPI_ERR("failed accessing ATTR_EFF_DRAM_ODIC: 0x%lx (target: %s)",
2395- uint64_t(fapi2::current_err), mss::c_str(i_target));
2396- return fapi2::current_err;
2397-}
2398-
2399-///
2400-/// @brief ATTR_MSS_EFF_ODT_RD getter
2401-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
2402-/// @param[out] uint8_t* memory to store the value
2403-/// @note Generated by gen_accessors.pl generateParameters (A)
2404-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2405-/// @note READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to
2406-/// fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0
2407-/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] Attribute is derived from VPD
2408-/// for RDIMM or from termination settings for
2409-/// LRDIMM
2410-///
2411-inline fapi2::ReturnCode eff_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
2412-{
2413- if (o_array == nullptr)
2414- {
2415- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2416- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2417- }
2418-
2419- uint8_t l_value[2][2][4];
2420- auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
2421- auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>();
2422-
2423- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_ODT_RD, l_mcs, l_value) );
2424- memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4);
2425- return fapi2::current_err;
2426-
2427-fapi_try_exit:
2428- FAPI_ERR("failed accessing ATTR_MSS_EFF_ODT_RD: 0x%lx (target: %s)",
2429- uint64_t(fapi2::current_err), mss::c_str(i_target));
2430- return fapi2::current_err;
2431-}
2432-
2433-///
2434-/// @brief ATTR_MSS_EFF_ODT_RD getter
2435-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
2436-/// @param[out] uint8_t* memory to store the value
2437-/// @note Generated by gen_accessors.pl generateParameters (B)
2438-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2439-/// @note READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to
2440-/// fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0
2441-/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] Attribute is derived from VPD
2442-/// for RDIMM or from termination settings for
2443-/// LRDIMM
2444-///
2445-inline fapi2::ReturnCode eff_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
2446-{
2447- if (o_array == nullptr)
2448- {
2449- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2450- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2451- }
2452-
2453- uint8_t l_value[2][2][4];
2454- auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>();
2455-
2456- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_ODT_RD, l_mcs, l_value) );
2457- memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8);
2458- return fapi2::current_err;
2459-
2460-fapi_try_exit:
2461- FAPI_ERR("failed accessing ATTR_MSS_EFF_ODT_RD: 0x%lx (target: %s)",
2462- uint64_t(fapi2::current_err), mss::c_str(i_target));
2463- return fapi2::current_err;
2464-}
2465-
2466-///
2467-/// @brief ATTR_MSS_EFF_ODT_RD getter
2468-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
2469-/// @param[out] uint8_t* memory to store the value
2470-/// @note Generated by gen_accessors.pl generateParameters (C)
2471-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2472-/// @note READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to
2473-/// fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0
2474-/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] Attribute is derived from VPD
2475-/// for RDIMM or from termination settings for
2476-/// LRDIMM
2477-///
2478-inline fapi2::ReturnCode eff_odt_rd(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
2479-{
2480- if (o_array == nullptr)
2481- {
2482- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2483- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2484- }
2485-
2486- uint8_t l_value[2][2][4];
2487-
2488- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_ODT_RD, i_target, l_value) );
2489- memcpy(o_array, &l_value, 16);
2490- return fapi2::current_err;
2491-
2492-fapi_try_exit:
2493- FAPI_ERR("failed accessing ATTR_MSS_EFF_ODT_RD: 0x%lx (target: %s)",
2494- uint64_t(fapi2::current_err), mss::c_str(i_target));
2495- return fapi2::current_err;
2496-}
2497-
2498-///
2499-/// @brief ATTR_MSS_EFF_ODT_WR getter
2500-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
2501-/// @param[out] uint8_t* memory to store the value
2502-/// @note Generated by gen_accessors.pl generateParameters (A)
2503-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2504-/// @note WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT
2505-/// to fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0
2506-/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] Attribute is derived from VPD
2507-/// for RDIMM or from termination settings for
2508-/// LRDIMM
2509-///
2510-inline fapi2::ReturnCode eff_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
2511-{
2512- if (o_array == nullptr)
2513- {
2514- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2515- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2516- }
2517-
2518- uint8_t l_value[2][2][4];
2519- auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
2520- auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>();
2521-
2522- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_ODT_WR, l_mcs, l_value) );
2523- memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4);
2524- return fapi2::current_err;
2525-
2526-fapi_try_exit:
2527- FAPI_ERR("failed accessing ATTR_MSS_EFF_ODT_WR: 0x%lx (target: %s)",
2528- uint64_t(fapi2::current_err), mss::c_str(i_target));
2529- return fapi2::current_err;
2530-}
2531-
2532-///
2533-/// @brief ATTR_MSS_EFF_ODT_WR getter
2534-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
2535-/// @param[out] uint8_t* memory to store the value
2536-/// @note Generated by gen_accessors.pl generateParameters (B)
2537-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2538-/// @note WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT
2539-/// to fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0
2540-/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] Attribute is derived from VPD
2541-/// for RDIMM or from termination settings for
2542-/// LRDIMM
2543-///
2544-inline fapi2::ReturnCode eff_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t* o_array)
2545-{
2546- if (o_array == nullptr)
2547- {
2548- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2549- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2550- }
2551-
2552- uint8_t l_value[2][2][4];
2553- auto l_mcs = i_target.getParent<fapi2::TARGET_TYPE_MCS>();
2554-
2555- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_ODT_WR, l_mcs, l_value) );
2556- memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8);
2557- return fapi2::current_err;
2558-
2559-fapi_try_exit:
2560- FAPI_ERR("failed accessing ATTR_MSS_EFF_ODT_WR: 0x%lx (target: %s)",
2561- uint64_t(fapi2::current_err), mss::c_str(i_target));
2562- return fapi2::current_err;
2563-}
2564-
2565-///
2566-/// @brief ATTR_MSS_EFF_ODT_WR getter
2567-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
2568-/// @param[out] uint8_t* memory to store the value
2569-/// @note Generated by gen_accessors.pl generateParameters (C)
2570-/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
2571-/// @note WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT
2572-/// to fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0
2573-/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] Attribute is derived from VPD
2574-/// for RDIMM or from termination settings for
2575-/// LRDIMM
2576-///
2577-inline fapi2::ReturnCode eff_odt_wr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
2578-{
2579- if (o_array == nullptr)
2580- {
2581- FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
2582- return fapi2::FAPI2_RC_INVALID_PARAMETER;
2583- }
2584-
2585- uint8_t l_value[2][2][4];
2586-
2587- FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_ODT_WR, i_target, l_value) );
2588- memcpy(o_array, &l_value, 16);
2589- return fapi2::current_err;
2590-
2591-fapi_try_exit:
2592- FAPI_ERR("failed accessing ATTR_MSS_EFF_ODT_WR: 0x%lx (target: %s)",
2593- uint64_t(fapi2::current_err), mss::c_str(i_target));
2594- return fapi2::current_err;
2595-}
2596-
2597 ///
2598 /// @brief ATTR_EFF_DRAM_TREFI getter
2599 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
2600diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
2601index c8f59400e8ff..187b60c085fe 100644
2602--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
2603+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
2604@@ -1255,7 +1255,7 @@ fapi2::ReturnCode reset_odt_rd_config( const fapi2::Target<fapi2::TARGET_TYPE_MC
2605
2606 const uint64_t l_dimm_count = count_dimm(i_target);
2607
2608- FAPI_TRY( mss::eff_odt_rd(i_target, &(l_odt_rd[0][0])) );
2609+ FAPI_TRY( mss::vpd_mt_odt_rd(i_target, &(l_odt_rd[0][0])) );
2610
2611 return reset_odt_rd_config_helper<fapi2::TARGET_TYPE_MCA, MAX_DIMM_PER_PORT, MAX_RANK_PER_DIMM>(
2612 i_target, l_dimm_count, l_odt_rd);
2613@@ -1276,7 +1276,7 @@ fapi2::ReturnCode reset_odt_wr_config( const fapi2::Target<fapi2::TARGET_TYPE_MC
2614
2615 const uint64_t l_dimm_count = count_dimm(i_target);
2616
2617- FAPI_TRY( mss::eff_odt_wr(i_target, &(l_odt_wr[0][0])) );
2618+ FAPI_TRY( mss::vpd_mt_odt_wr(i_target, &(l_odt_wr[0][0])) );
2619
2620 return reset_odt_wr_config_helper<fapi2::TARGET_TYPE_MCA, MAX_DIMM_PER_PORT, MAX_RANK_PER_DIMM>(
2621 i_target, l_dimm_count, l_odt_wr);
2622@@ -1310,7 +1310,7 @@ fapi2::ReturnCode override_odt_wr_config( const fapi2::Target<fapi2::TARGET_TYPE
2623 i_rank );
2624
2625 // read the attributes
2626- FAPI_TRY( mss::eff_odt_wr(i_target, &(l_odt_wr[0][0])) );
2627+ FAPI_TRY( mss::vpd_mt_odt_wr(i_target, &(l_odt_wr[0][0])) );
2628
2629 // set the ODTs for the rank selected
2630 // The ODT encoding is (for mranks only)
2631diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
2632index 3adb52f9e516..56dd353399eb 100644
2633--- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
2634+++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H
2635@@ -156,7 +156,6 @@ enum ffdc_function_codes
2636 DRAM_BANK_BITS = 25,
2637 DRAM_ROW_BITS = 26,
2638 SOFT_POST_PACKAGE_REPAIR = 27,
2639- EFF_BC07 = 28,
2640
2641 // Used in fw_mark_store.H for MSS_INVALID_RANK_PASSED
2642 FWMS_READ = 30,
2643diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
2644old mode 100755
2645new mode 100644
2646index 6b078f902dc9..c05c51992aa7
2647--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
2648+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
2649@@ -98,12 +98,6 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>
2650
2651 FAPI_INF("Running eff_config on %s", mss::c_str(l_dimm) );
2652
2653- FAPI_TRY( l_eff_dimm->dram_odic(),
2654- "Failed dram_odic for %s", mss::c_str(l_dimm) );
2655- FAPI_TRY( l_eff_dimm->odt_wr(),
2656- "Failed odt_wr for %s", mss::c_str(l_dimm) );
2657- FAPI_TRY( l_eff_dimm->odt_rd(),
2658- "Failed odt_rd for %s", mss::c_str(l_dimm) );
2659 FAPI_TRY( l_eff_dimm->rcd_mfg_id(),
2660 "Failed rcd_mfg_id for %s", mss::c_str(l_dimm) );
2661 FAPI_TRY( l_eff_dimm->register_type(),
2662@@ -306,8 +300,6 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>
2663 "Failed dimm_bc04 for %s", mss::c_str(l_dimm) );
2664 FAPI_TRY( l_eff_dimm->dimm_bc05(),
2665 "Failed dimm_bc05 for %s", mss::c_str(l_dimm) );
2666- FAPI_TRY( l_eff_dimm->dimm_bc06(),
2667- "Failed dimm_bc06 for %s", mss::c_str(l_dimm) );
2668 FAPI_TRY( l_eff_dimm->dimm_bc07(),
2669 "Failed dimm_bc07 for %s", mss::c_str(l_dimm) );
2670 FAPI_TRY( l_eff_dimm->dimm_bc08(),
2671@@ -340,18 +332,6 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>
2672 "Failed nibble_map for %s", mss::c_str(l_dimm) );
2673 FAPI_TRY( l_eff_dimm->wr_crc(),
2674 "Failed wr_crc for %s", mss::c_str(l_dimm) );
2675- FAPI_TRY( l_eff_dimm->dimm_f0bc1x(),
2676- "Failed dimm_f0bc1x for %s", mss::c_str(l_dimm) );
2677- FAPI_TRY( l_eff_dimm->dimm_f0bc6x(),
2678- "Failed dimm_f0bc6x for %s", mss::c_str(l_dimm) );
2679- FAPI_TRY( l_eff_dimm->dimm_f2bcex(),
2680- "Failed dimm_f2bcex for %s", mss::c_str(l_dimm) );
2681- FAPI_TRY( l_eff_dimm->dimm_f5bc5x(),
2682- "Failed dimm_f5bc5x for %s", mss::c_str(l_dimm) );
2683- FAPI_TRY( l_eff_dimm->dimm_f5bc6x(),
2684- "Failed dimm_f5bc6x for %s", mss::c_str(l_dimm) );
2685- FAPI_TRY( l_eff_dimm->dimm_f6bc4x(),
2686- "Failed dimm_f6bc4x for %s", mss::c_str(l_dimm) );
2687
2688 // Sets up the calibration steps
2689 FAPI_TRY( l_eff_dimm->cal_step_enable(),
2690diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
2691index 2ff3e37937b9..bb96987aa783 100644
2692--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
2693+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
2694@@ -2409,7 +2409,6 @@
2695 <valueType>uint8</valueType>
2696 <writeable />
2697 <array> 2 2 </array>
2698- <mssAccessorName>eff_dimm_ddr4_bc06</mssAccessorName>
2699 </attribute>
2700
2701 <attribute>
2702@@ -2519,7 +2518,6 @@
2703 <valueType>uint8</valueType>
2704 <writeable />
2705 <array> 2 2 </array>
2706- <mssAccessorName>eff_dimm_ddr4_f0bc1x</mssAccessorName>
2707 </attribute>
2708
2709 <attribute>
2710@@ -2570,7 +2568,6 @@
2711 <valueType>uint8</valueType>
2712 <writeable />
2713 <array> 2 2 </array>
2714- <mssAccessorName>eff_dimm_ddr4_f0bc6x</mssAccessorName>
2715 </attribute>
2716
2717 <attribute>
2718@@ -2700,17 +2697,6 @@
2719 <array> 2 2 </array>
2720 </attribute>
2721
2722- <attribute>
2723- <id>ATTR_EFF_DIMM_DDR4_F2BCEx</id>
2724- <targetType>TARGET_TYPE_MCS</targetType>
2725- <description>F2BCWEx Host Interface DFE Programming Control Word</description>
2726- <initToZero></initToZero>
2727- <valueType>uint8</valueType>
2728- <writeable />
2729- <array> 2 2 </array>
2730- <mssAccessorName>eff_dimm_ddr4_f2bcex</mssAccessorName>
2731- </attribute>
2732-
2733 <attribute>
2734 <id>ATTR_EFF_DIMM_DDR4_F4BC0x</id>
2735 <targetType>TARGET_TYPE_MCS</targetType>
2736@@ -2829,7 +2815,6 @@
2737 <valueType>uint8</valueType>
2738 <writeable />
2739 <array> 2 2 </array>
2740- <mssAccessorName>eff_dimm_ddr4_f5bc5x</mssAccessorName>
2741 </attribute>
2742
2743 <attribute>
2744@@ -3018,51 +3003,6 @@
2745 <mssAccessorName>eff_dram_tdqs</mssAccessorName>
2746 </attribute>
2747
2748- <attribute>
2749- <id>ATTR_EFF_DRAM_ODIC</id>
2750- <targetType>TARGET_TYPE_MCS</targetType>
2751- <description>
2752- DRAM output driver impedance control (ODIC)
2753- </description>
2754- <initToZero></initToZero>
2755- <valueType>uint8</valueType>
2756- <enum>OHM34 = 34, OHM48 = 48</enum>
2757- <writeable/>
2758- <array> 2 2 4 </array>
2759- <mssAccessorName>eff_dram_odic</mssAccessorName>
2760- </attribute>
2761-
2762- <attribute>
2763- <id>ATTR_MSS_EFF_ODT_RD</id>
2764- <targetType>TARGET_TYPE_MCS</targetType>
2765- <description>
2766- READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank.
2767- The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A]
2768- Attribute is derived from VPD for RDIMM or from termination settings for LRDIMM
2769- </description>
2770- <initToZero></initToZero>
2771- <writeable/>
2772- <valueType>uint8</valueType>
2773- <mssAccessorName>eff_odt_rd</mssAccessorName>
2774- <array>2 2 4</array>
2775- </attribute>
2776-
2777- <attribute>
2778- <id>ATTR_MSS_EFF_ODT_WR</id>
2779- <targetType>TARGET_TYPE_MCS</targetType>
2780- <description>
2781- WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank.
2782- The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A]
2783- Attribute is derived from VPD for RDIMM or from termination settings for LRDIMM
2784- </description>
2785- <initToZero></initToZero>
2786- <writeable/>
2787- <valueType>uint8</valueType>
2788- <writeable/>
2789- <mssAccessorName>eff_odt_wr</mssAccessorName>
2790- <array>2 2 4</array>
2791- </attribute>
2792-
2793 <attribute>
2794 <id>ATTR_EFF_DRAM_TREFI</id>
2795 <targetType>TARGET_TYPE_MCS</targetType>
2796diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml
2797index 9d9aea1744fb..965e0de84ccc 100644
2798--- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml
2799+++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml
2800@@ -485,24 +485,6 @@
2801 </callout>
2802 </hwpError>
2803
2804- <hwpError>
2805- <rc>RC_MSS_INVALID_RTT_PARK_CALCULATIONS</rc>
2806- <description>
2807- Calculated the rtt_park_index into the VPD attribute incorrectly
2808- </description>
2809- <ffdc>RANK</ffdc>
2810- <ffdc>RTT_PARK_INDEX</ffdc>
2811- <ffdc>RTT_PARK_FROM_VPD</ffdc>
2812- <ffdc>DIMM_TARGET</ffdc>
2813- <callout>
2814- <hw>
2815- <hwid>VPD_PART</hwid>
2816- <refTarget>MCS_TARGET</refTarget>
2817- </hw>
2818- <priority>HIGH</priority>
2819- </callout>
2820- </hwpError>
2821-
2822 <hwpError>
2823 <rc>RC_MSS_INVALID_RTT_NOM_CALCULATIONS</rc>
2824 <description>
2825--
28262.19.1
2827