| Stewart Smith | 28b0ca5 | 2018-08-16 19:46:03 +1000 | [diff] [blame] | 1 | Release Notes for OpenPower Firmware v2.0.9 |
| 2 | =========================================== |
| 3 | |
| 4 | op-build v2.0.9 was released on Thursday August 16th, 2018 and replaces op-build v2.0.8 as the current stable release in |
| 5 | the 2.0.x series. |
| 6 | |
| 7 | It is recommended that v2.0.9 be used over any previous v2.0.x version on POWER9 systems due to the bug fixes contained within. |
| 8 | |
| 9 | The only update in this release is to skiboot. Skiboot v6.0.8 includes the following bug fixes: |
| 10 | - i2c: Ensure ordering between i2c_request_send() and completion |
| 11 | |
| 12 | i2c_request_send loops waiting for a flag "uc.done" set by |
| 13 | the completion routine, and then look for a result code |
| 14 | also set by that same completion. |
| 15 | |
| 16 | There is no synchronization, the completion can happen on another |
| 17 | processor, so we need to order the stores to uc and the reads |
| 18 | from uc so that uc.done is stored last and tested first using |
| 19 | memory barriers. |
| 20 | - i2c: Fix multiple-enqueue of the same request on NACK |
| 21 | |
| 22 | i2c_request_send() will retry the request if the error is a NAK, |
| 23 | however it forgets to clear the "ud.done" flag. It will thus |
| 24 | loop again and try to re-enqueue the same request causing internal |
| 25 | request list corruption. |
| 26 | - phb4: Disable 32-bit MSI in capi mode |
| 27 | |
| 28 | If a capi device does a DMA write targeting an address lower than 4GB, |
| 29 | it does so through a 32-bit operation, per the PCI spec. In capi mode, |
| 30 | the first TVE entry is configured in bypass mode, so the address is |
| 31 | valid. But with any (bad) luck, the address could be 0xFFFFxxxx, thus |
| 32 | looking like a 32-bit MSI. |
| 33 | |
| 34 | We currently enable both 32-bit and 64-bit MSIs, so the PHB will |
| 35 | interpret the DMA write as a MSI, which very likely results in an EEH |
| 36 | (MSI with a bad payload size). |
| 37 | |
| 38 | We can fix it by disabling 32-bit MSI when switching the PHB to capi |
| 39 | mode. Capi devices are 64-bit. |
| 40 | |
| 41 | - capp: Fix the capp recovery timeout comparison |
| 42 | |
| 43 | The current capp recovery timeout control loop in |
| 44 | do_capp_recovery_scoms() uses a wrong comparison for return value of |
| 45 | tb_compare(). This may cause do_capp_recovery_scoms() to report an |
| 46 | timeout earlier than the 168ms stipulated time. |
| 47 | |
| 48 | The patch fixes this by updating the loop timeout control branch in |
| 49 | do_capp_recovery_scoms() to use the correct enum tb_cmpval. |
| 50 | - phb4/capp: Update DMA read engines set in APC_FSM_READ_MASK based on link-width |
| 51 | |
| 52 | Commit 47c09cdfe7a3("phb4/capp: Calculate STQ/DMA read engines based |
| 53 | on link-width for PEC") update the CAPP init sequence by calculating |
| 54 | the needed STQ/DMA-read engines based on link width and populating it |
| 55 | in XPEC_NEST_CAPP_CNTL register. This however needs to be synchronized |
| 56 | with the value set in CAPP APC FSM Read Machine Mask Register. |
| 57 | |
| 58 | Hence this patch update phb4_init_capp_regs() to calculate the link |
| 59 | width of the stack on PEC2 and populate the same values as previously |
| 60 | populated in PEC CAPP_CNTL register. |
| 61 | |
| 62 | - core/cpu: Call memset with proper cpu_thread offset |
| 63 | |
| 64 | |