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gerrit.openbmc.org / premsjha / op-build / e9dfa4b90bcec2382f862634a4fdbe7dcbacb8d4 / . / openpower / package / hostboot-p10 / 0001-Mvpd-Ekb-ringId-gap-discontinuity-support.patch
blob: 97858a3ded3f6dc181f0e53de2b9b664fdf26625 [file] [log] [blame]
hostboot97ff4642020-05-20 11:46:02 -0500[diff] [blame]1From aaeb72ec680f77eaa8d583b9bd91b62745d025c7 Mon Sep 17 00:00:00 2001
2From: Olsen <cmolsen@us.ibm.com>
3Date: Thu, 6 Feb 2020 08:48:34 -0500
4Subject: [PATCH] Mvpd-Ekb ringId gap-discontinuity support
5
6Making support for the ringId gap that needs to exist between the end
7of the Mvpd RingID group and the beginning of the Ekb RingID group
8in order to be able to append Mvpd rings to the end of the Mvpd
9RingID group without affecting the already assigned RingID enum for
10any of the other existing rings.
11
12Note that the purpose of any RingID grouping, or order, is to:
13- ease debugging the ring images and output traces of ipl_customize,
14- ease the maintaining of the ringId header files.
15
16Enforcing ringId groups comes with an increase in code complexity
17to enable conversion between ringId and rpIndex (i.e., the index of
18of the RING_PROPERTIES list).
19
20Several bugs were found in implementing the above support as there has
21been a built-in assumption in the PPE/Cronus customized putRingUtils
22and ring_traverse codes that the ringId is a uint8 type but which we
23are now exceeding the limit of with this group enforcement.
24
25Also added updated mvpd.dat, based on scandef ver 910007, to better
26match EKB engd's version (which at the time of this merge seems to be
27consistent with 910007).
28- Also added an README file with details about mvpd.dat
29
30Key_Cronus_Test=XIP_REGRESS_SBE_QME
31
32Change-Id: I59eddeff34c3dedf23b092b0cf89ef422e8bb753
33Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/91255
34Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
35Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
36Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
37Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
38---
39 .../chips/common/utils/imageProcs/common_ringId.C | 361 +++++-----
40 .../chips/common/utils/imageProcs/common_ringId.H | 34 +-
41 .../procedures/hwp/accessors/p10_get_mvpd_ring.C | 6 +-
42 .../procedures/hwp/accessors/p10_mvpd_ring_funcs.C | 42 +-
43 .../procedures/hwp/customize/p10_ipl_customize.C | 282 ++++----
44 .../procedures/hwp/customize/p10_qme_customize.C | 281 ++++----
45 .../procedures/hwp/customize/p10_qme_customize.H | 67 +-
46 .../p10/procedures/hwp/pm/p10_hcode_image_build.C | 6 +-
47 .../xml/error_info/p10_qme_customize_errors.xml | 52 +-
48 src/import/chips/p10/utils/imageProcs/p10_ringId.H | 48 +-
49 .../chips/p10/utils/imageProcs/p10_ring_id.H | 194 +++---
50 .../p10/utils/imageProcs/p10_ring_properties.H | 725 +++++++++++----------
51 src/import/chips/p10/utils/imageProcs/p10_tor.C | 75 ++-
52 13 files changed, 1107 insertions(+), 1066 deletions(-)
53
54diff --git a/src/import/chips/common/utils/imageProcs/common_ringId.C b/src/import/chips/common/utils/imageProcs/common_ringId.C
55index 19729ad..904cb38 100644
56--- a/src/import/chips/common/utils/imageProcs/common_ringId.C
57+++ b/src/import/chips/common/utils/imageProcs/common_ringId.C
58@@ -164,19 +164,22 @@ int ringid_get_scanScomAddr( ChipId_t i_chipId,
59 int rc = INFRASTRUCT_RC_SUCCESS;
60 uint32_t l_scanScomAddr = UNDEFINED_SCOM_ADDR;
61
62+ // Get the ring properties (rp) index
63+ RingId_t rpIndex = P10_RID::ringid_convert_ringId_to_rpIndex(i_ringId);
64+
65 switch (i_chipId)
66 {
67 case CID_P10:
68- if (i_ringId >= P10_RID::NUM_RING_IDS)
69+ if (rpIndex >= P10_RID::NUM_RING_IDS)
70 {
71- MY_ERR("ringid_get_scanScomAddr(): ringId(=0x%x) >= NUM_RING_IDS(=0x%x) not"
72- " allowed\n",
73- i_ringId, P10_RID::NUM_RING_IDS);
74+ MY_ERR("ringid_get_scanScomAddr(): rpIndex(=0x%x) >= NUM_RING_IDS(=0x%x) not"
75+ " allowed and ringId=0x%x\n",
76+ rpIndex, P10_RID::NUM_RING_IDS, i_ringId);
77 rc = TOR_INVALID_RING_ID;
78 break;
79 }
80
81- l_scanScomAddr = P10_RID::RING_PROPERTIES[i_ringId].scanScomAddr;
82+ l_scanScomAddr = P10_RID::RING_PROPERTIES[rpIndex].scanScomAddr;
83 break;
84
85 default:
86@@ -198,18 +201,22 @@ int ringid_get_ringClass( ChipId_t i_chipId,
87 int rc = INFRASTRUCT_RC_SUCCESS;
88 RingClass_t l_ringClass = UNDEFINED_RING_CLASS;
89
90+ // Get the ring properties (rp) index
91+ RingId_t rpIndex = P10_RID::ringid_convert_ringId_to_rpIndex(i_ringId);
92+
93 switch (i_chipId)
94 {
95 case CID_P10:
96- if (i_ringId >= P10_RID::NUM_RING_IDS)
97+ if (rpIndex >= P10_RID::NUM_RING_IDS)
98 {
99- MY_ERR("ringid_get_ringClass(): ringId(=0x%x) >= NUM_RING_IDS(=0x%x) not allowed\n",
100- i_ringId, P10_RID::NUM_RING_IDS);
101+ MY_ERR("ringid_get_ringClass(): rpIndex(=0x%x) >= NUM_RING_IDS(=0x%x) not"
102+ " allowed and ringId=0x%x\n",
103+ rpIndex, P10_RID::NUM_RING_IDS, i_ringId);
104 rc = TOR_INVALID_RING_ID;
105 break;
106 }
107
108- l_ringClass = P10_RID::RING_PROPERTIES[i_ringId].ringClass;
109+ l_ringClass = P10_RID::RING_PROPERTIES[rpIndex].ringClass;
110 break;
111
112 default:
113@@ -227,33 +234,33 @@ int ringid_get_ringClass( ChipId_t i_chipId,
114 int ringid_check_ringId( ChipId_t i_chipId,
115 RingId_t i_ringId )
116 {
117- int rc = INFRASTRUCT_RC_SUCCESS;
118+ if ( i_ringId == HOLE_RING_ID )
119+ {
120+ // A hole ring is benign. Let caller decide.
121+ return TOR_HOLE_RING_ID;
122+ }
123+
124+ // Get the ring properties (rp) index
125+ RingId_t rpIndex = P10_RID::ringid_convert_ringId_to_rpIndex(i_ringId);
126
127 switch (i_chipId)
128 {
129 case CID_P10:
130- if ( strcmp(P10_RID::RING_PROPERTIES[i_ringId].ringName, "invalid") == 0 )
131+ if ( rpIndex >= P10_RID::NUM_RING_IDS )
132 {
133- // There are ringId holes. This is harmless. No trace out.
134- rc = TOR_HOLE_RING_ID;
135- }
136- else if ( i_ringId >= P10_RID::NUM_RING_IDS && i_ringId != UNDEFINED_RING_ID )
137- {
138- // This is unlikely to happen, and shouldn't happen, so here we trace out.
139- MY_ERR("ringid_check_ringId(): ringId(=0x%x) >= NUM_RING_IDS(=0x%x) not allowed\n",
140- i_ringId, P10_RID::NUM_RING_IDS);
141- rc = TOR_INVALID_RING_ID;
142+ // Not necessarily an error. Let caller decide.
143+ return TOR_INVALID_RING_ID;
144 }
145
146 break;
147
148 default:
149- MY_ERR("ringid_check_ringId(): Unsupported chipId (=%d) supplied\n", i_chipId);
150- rc = TOR_INVALID_CHIP_ID;
151- break;
152+ MY_ERR("ERROR: ringid_check_ringId: Unsupported chipId(=0x%x) supplied\n",
153+ i_chipId);
154+ return TOR_INVALID_CHIP_ID;
155 }
156
157- return rc;
158+ return TOR_SUCCESS;
159 }
160
161
162@@ -313,10 +320,21 @@ int ringid_get_chipletIndex( ChipId_t i_chipId,
163 MyBool_t ringid_is_mvpd_ring( ChipId_t i_chipId,
164 RingId_t i_ringId )
165 {
166+ // Get the ring properties (rp) index
167+ RingId_t rpIndex = P10_RID::ringid_convert_ringId_to_rpIndex(i_ringId);
168+
169 switch (i_chipId)
170 {
171 case CID_P10:
172- if ( P10_RID::RING_PROPERTIES[i_ringId].ringClass & RCLS_MVPD_MASK )
173+ if (rpIndex >= P10_RID::NUM_RING_IDS)
174+ {
175+ MY_ERR("ringid_is_mvpd_ring(): rpIndex(=0x%x) >= NUM_RING_IDS(=0x%x) not"
176+ " allowed and ringId=0x%x\n",
177+ rpIndex, P10_RID::NUM_RING_IDS, i_ringId);
178+ return UNDEFINED_BOOLEAN;
179+ }
180+
181+ if ( P10_RID::RING_PROPERTIES[rpIndex].ringClass & RCLS_MVPD_MASK )
182 {
183 return true;
184 }
185@@ -325,6 +343,8 @@ MyBool_t ringid_is_mvpd_ring( ChipId_t i_chipId,
186 return false;
187 }
188
189+ break;
190+
191 default:
192 MY_ERR("ringid_is_mvpd_ring(): Unsupported chipId (=%d) supplied\n", i_chipId);
193 return UNDEFINED_BOOLEAN;
194@@ -336,10 +356,21 @@ MyBool_t ringid_is_mvpd_ring( ChipId_t i_chipId,
195 MyBool_t ringid_is_gptr_ring( ChipId_t i_chipId,
196 RingId_t i_ringId )
197 {
198+ // Get the ring properties (rp) index
199+ RingId_t rpIndex = P10_RID::ringid_convert_ringId_to_rpIndex(i_ringId);
200+
201 switch (i_chipId)
202 {
203 case CID_P10:
204- if ( P10_RID::RING_PROPERTIES[i_ringId].ringClass & RMRK_GPTR_OVLY )
205+ if (rpIndex >= P10_RID::NUM_RING_IDS)
206+ {
207+ MY_ERR("ringid_is_gptr_ring(): rpIndex(=0x%x) >= NUM_RING_IDS(=0x%x) not"
208+ " allowed and ringId=0x%x\n",
209+ rpIndex, P10_RID::NUM_RING_IDS, i_ringId);
210+ return UNDEFINED_BOOLEAN;
211+ }
212+
213+ if ( P10_RID::RING_PROPERTIES[rpIndex].ringClass & RMRK_GPTR_OVLY )
214 {
215 return true;
216 }
217@@ -348,6 +379,8 @@ MyBool_t ringid_is_gptr_ring( ChipId_t i_chipId,
218 return false;
219 }
220
221+ break;
222+
223 default:
224 MY_ERR("ringid_is_gptr_ring(): Unsupported chipId (=%d) supplied\n", i_chipId);
225 return UNDEFINED_BOOLEAN;
226@@ -357,13 +390,51 @@ MyBool_t ringid_is_gptr_ring( ChipId_t i_chipId,
227 }
228
229
230+MyBool_t ringid_is_instance_ring( RingId_t i_rpIndex)
231+{
232+ if (i_rpIndex >= P10_RID::NUM_RING_IDS)
233+ {
234+ MY_ERR("ringid_is_instance_ring(): rpIndex(=0x%x) >= NUM_RING_IDS(=0x%x) not allowed\n",
235+ i_rpIndex, P10_RID::NUM_RING_IDS);
236+ return UNDEFINED_BOOLEAN;
237+ }
238+
239+ if ( P10_RID::RING_PROPERTIES[i_rpIndex].idxRing == UNDEFINED_RING_INDEX )
240+ {
241+ return UNDEFINED_BOOLEAN;
242+ }
243+
244+ if ( P10_RID::RING_PROPERTIES[i_rpIndex].idxRing & INSTANCE_RING_MARK )
245+ {
246+ return true;
247+ }
248+ else
249+ {
250+ return false;
251+ }
252+
253+ return UNDEFINED_BOOLEAN;
254+}
255+
256+
257 MyBool_t ringid_has_derivs( ChipId_t i_chipId,
258 RingId_t i_ringId )
259 {
260+ // Get the ring properties (rp) index
261+ RingId_t rpIndex = P10_RID::ringid_convert_ringId_to_rpIndex(i_ringId);
262+
263 switch (i_chipId)
264 {
265 case CID_P10:
266- if ( P10_RID::RING_PROPERTIES[i_ringId].ringClass & RMRK_HAS_DERIVS )
267+ if (rpIndex >= P10_RID::NUM_RING_IDS)
268+ {
269+ MY_ERR("ringid_has_derivs(): rpIndex(=0x%x) >= NUM_RING_IDS(=0x%x) not"
270+ " allowed and ringId=0x%x\n",
271+ rpIndex, P10_RID::NUM_RING_IDS, i_ringId);
272+ return UNDEFINED_BOOLEAN;
273+ }
274+
275+ if ( P10_RID::RING_PROPERTIES[rpIndex].ringClass & RMRK_HAS_DERIVS )
276 {
277 return true;
278 }
279@@ -372,6 +443,8 @@ MyBool_t ringid_has_derivs( ChipId_t i_chipId,
280 return false;
281 }
282
283+ break;
284+
285 default:
286 MY_ERR("ringid_has_derivs(): Unsupported chipId (=%d) supplied\n", i_chipId);
287 return UNDEFINED_BOOLEAN;
288@@ -411,8 +484,9 @@ int ringidGetRootRingId( ChipId_t i_chipId,
289 int rc = INFRASTRUCT_RC_SUCCESS;
290 RingProperties_t* ringProps = NULL;
291 RingId_t numRingIds = UNDEFINED_RING_ID;
292- RingId_t iRingId = UNDEFINED_RING_ID; // ringId loop counter
293- RingId_t l_ringId = UNDEFINED_RING_ID;
294+ RingId_t iRpIndex = UNDEFINED_RING_ID; // Ring properties index counter
295+ RingId_t rpIndexTmp = UNDEFINED_RING_ID; // Temporary RP index for bFound=true
296+ RingId_t l_ringId = UNDEFINED_RING_ID; // Local ringId, eventual output ringId
297 bool bFound = false;
298
299 switch (i_chipId)
300@@ -435,25 +509,26 @@ int ringidGetRootRingId( ChipId_t i_chipId,
301
302 if (!rc)
303 {
304- for ( iRingId = 0; iRingId < numRingIds; iRingId++ )
305+ for ( iRpIndex = 0; iRpIndex < numRingIds; iRpIndex++ )
306 {
307- if ( ringProps[iRingId].scanScomAddr == i_scanScomAddr )
308+ if ( ringProps[iRpIndex].scanScomAddr == i_scanScomAddr )
309 {
310- if ( ringProps[iRingId].ringClass & RMRK_ROOT )
311+ if ( ringProps[iRpIndex].ringClass & RMRK_ROOT )
312 {
313 if (bFound)
314 {
315 MY_ERR("ringidGetRootRingId(): Two rings w/same addr cannot both be"
316 " ROOT_RING. Fix RING_PROPERTIES list for chipId=%d at"
317 " ringId=0x%x and ringId=0x%x\n",
318- i_chipId, l_ringId, iRingId);
319- rc = INFRASTRUCT_RC_CODE_BUG;
320+ i_chipId, rpIndexTmp, iRpIndex);
321 l_ringId = UNDEFINED_RING_ID;
322+ rc = INFRASTRUCT_RC_CODE_BUG;
323 break;
324 }
325 else
326 {
327- l_ringId = iRingId;
328+ rpIndexTmp = iRpIndex;
329+ l_ringId = ringProps[iRpIndex].ringId;
330 bFound = true;
331
332 if (!i_bTest)
333@@ -473,145 +548,6 @@ int ringidGetRootRingId( ChipId_t i_chipId,
334 {
335 // This is not a bug, but do tell caller that scanScomAddr wasn't found.
336 rc = TOR_SCOM_ADDR_NOT_FOUND;
337-
338- if (l_ringId != UNDEFINED_RING_ID)
339- {
340- MY_ERR("ringidGetRootRingId(): Did not find match for scanScomAddr=0x%08x for"
341- " chipId=%d. However, l_ringId=0x%x cannot be different from"
342- " UNDEFINED_RING_ID=0x%x. Fix code!\n",
343- i_scanScomAddr, i_chipId, l_ringId, UNDEFINED_RING_ID);
344- rc = INFRASTRUCT_RC_CODE_BUG;
345- }
346- }
347-
348- o_ringId = l_ringId;
349-
350- return rc;
351-}
352-
353-
354-int ringidGetRingId2( ChipId_t i_chipId,
355- uint32_t i_torMagic,
356- ChipletType_t i_chipletType, // Ignored if only one chiplet in torMagic
357- uint8_t i_idxRing, // The effective ring index within chiplet's
358- // common or instance ring section
359- MyBool_t i_bInstCase,
360- RingId_t& o_ringId,
361- bool i_bTest )
362-{
363- int rc = INFRASTRUCT_RC_SUCCESS;
364- ChipletType_t l_chipletType = UNDEFINED_CHIPLET_TYPE;
365- RingProperties_t* ringProps = NULL;
366- RingId_t numRingIds = UNDEFINED_RING_ID;
367- RingId_t iRingId = UNDEFINED_RING_ID; // ringId loop counter
368- RingId_t l_ringId = UNDEFINED_RING_ID;
369- uint8_t l_idxRing = UNDEFINED_RING_INDEX;
370- bool bFound = false;
371- bool bOverlap = false;
372-
373- // First, select the main ring list we need. And while we're at it,
374- // convert input chipletType, which can be ignored for ring sections (i.e. torMagic)
375- // with only one chiplet, to a valid chipletType
376- switch (i_chipId)
377- {
378- case CID_P10:
379- ringProps = (RingProperties_t*)&P10_RID::RING_PROPERTIES;
380- numRingIds = P10_RID::NUM_RING_IDS;
381-
382- if ( i_torMagic == TOR_MAGIC_SBE ||
383- i_torMagic == TOR_MAGIC_OVRD ||
384- i_torMagic == TOR_MAGIC_OVLY ||
385- i_torMagic == TOR_MAGIC_DYN )
386- {
387- l_chipletType = i_chipletType;
388- }
389- else if ( i_torMagic == TOR_MAGIC_QME )
390- {
391- l_chipletType = P10_RID::EQ_TYPE;
392- }
393- else
394- {
395- MY_ERR("Invalid torMagic(=0x%08x) for chipId=CID_P10x=%d\n", i_torMagic, i_chipId);
396- return TOR_INVALID_MAGIC_NUMBER;
397- }
398-
399- break;
400-
401- default:
402- MY_ERR("ringidGetRingId2(): Unsupported chipId (=%d) supplied\n", i_chipId);
403- rc = TOR_INVALID_CHIP_ID;
404- break;
405- }
406-
407- // Second, convert effective input ring index (which has no instance marker) to the
408- // common/instance specific index
409- l_idxRing = i_bInstCase ?
410- i_idxRing | INSTANCE_RING_MARK :
411- i_idxRing;
412-
413- if (!rc)
414- {
415- for ( iRingId = 0; iRingId < numRingIds; iRingId++ )
416- {
417- if ( ringProps[iRingId].chipletType == l_chipletType &&
418- ringProps[iRingId].idxRing == l_idxRing )
419- {
420- if (bFound)
421- {
422- // Allow ring index overlap between a root and a non-root ring
423- // and let the non-root (i.e., the bucket ring) "win"
424- if ( !bOverlap &&
425- ( (ringProps[iRingId].ringClass & RMRK_ROOT) !=
426- (ringProps[l_ringId].ringClass & RMRK_ROOT) ) )
427- {
428- if ( !(ringProps[iRingId].ringClass & RMRK_ROOT) )
429- {
430- l_ringId = iRingId;
431- }
432- else
433- {
434- // Keep l_ringId as is since it must already be the non-root ring
435- }
436-
437- bOverlap = true; // Indicate we found an overlap match
438-
439- if (!i_bTest)
440- {
441- // Stop testing and break our of ringId loop
442- break;
443- }
444- }
445- else
446- {
447- MY_ERR("ringidGetRingId2(): Two root, or two non-root, rings within a"
448- " chiplet (chipletType=%d) cannot have the same ring index"
449- " (idxRing=%d, bInst=%d). Fix RING_PROPERTIES list for chipId=%d"
450- " at ringId=0x%x and ringId=0x%x\n",
451- l_chipletType, i_idxRing, i_bInstCase, i_chipId, l_ringId, iRingId);
452- rc = INFRASTRUCT_RC_CODE_BUG;
453- l_ringId = UNDEFINED_RING_ID;
454- break;
455- }
456- }
457- else
458- {
459- l_ringId = iRingId;
460- bFound = true; // Indicate we found a first match
461-
462- // Continue searching for ring index overlap due to bucket ring or code bug
463- }
464- }
465- }
466- }
467-
468- if (!rc && !bFound)
469- {
470- MY_ERR("ringidGetRingId2(): Could not find a match for (chipId,chipletType,idxRing,bInst) ="
471- " (%d, %d, %d, %d). Fix RING_PROPERTIES list for chipId=%d (Note, l_ringId=0x%x"
472- " better be equal to UNDEFINED_RING_ID=0x%x)\n",
473- i_chipId, l_chipletType, i_idxRing, i_bInstCase,
474- i_chipId, l_ringId, UNDEFINED_RING_ID);
475- rc = INFRASTRUCT_RC_CODE_BUG;
476 }
477
478 o_ringId = l_ringId;
479@@ -643,16 +579,20 @@ std::map <std::string, ChipId_t> chipTypeToIdMap
480 { "explorer", (ChipId_t)CID_EXPLORER }
481 };
482
483+
484+//
485+// Get ringId from ringName
486+//
487 int ringidGetRingId1( ChipId_t i_chipId,
488 std::string i_ringName,
489 RingId_t& o_ringId,
490 bool i_bTest )
491 {
492- int rc = INFRASTRUCT_RC_SUCCESS;
493+ int rc = TOR_SUCCESS;
494 RingProperties_t* ringProps = NULL;
495 RingId_t numRingIds = UNDEFINED_RING_ID;
496- RingId_t iRingId = UNDEFINED_RING_ID; // ringId loop counter
497- RingId_t l_ringId = UNDEFINED_RING_ID;
498+ RingId_t iRpIndex = UNDEFINED_RING_ID; // Ring properties index counter
499+ RingId_t rpIndex = UNDEFINED_RING_ID; // The matching RP index
500 bool bFound = false;
501
502 switch (i_chipId)
503@@ -668,24 +608,30 @@ int ringidGetRingId1( ChipId_t i_chipId,
504 break;
505 }
506
507- if (!rc)
508+ if (rc)
509+ {
510+ return rc;
511+ }
512+ else
513 {
514- for ( iRingId = 0; iRingId < numRingIds; iRingId++ )
515+ // Search through RING_PROPERTIES for ringName match
516+ for ( iRpIndex = 0; iRpIndex < numRingIds; iRpIndex++ )
517 {
518- if ( !(i_ringName.compare(ringProps[iRingId].ringName)) )
519+ if ( !(i_ringName.compare(ringProps[iRpIndex].ringName)) )
520 {
521 if (bFound)
522 {
523- MY_ERR("ringidGetRingId1(): Two rings cannot have the same ringName=%s. Fix"
524- " RING_PROPERTIES list for chipId=%d at ringId=0x%x and ringId=0x%x\n",
525- i_ringName.c_str(), i_chipId, l_ringId, iRingId);
526- rc = INFRASTRUCT_RC_CODE_BUG;
527- l_ringId = UNDEFINED_RING_ID;
528+ MY_ERR("ringidGetRingId1(): Two rings cannot have the same ringName=%s. Fix"
529+ " RING_PROPERTIES list for chipId=%d at rpIndex=0x%x and"
530+ " rpIndex=0x%x\n",
531+ i_ringName.c_str(), i_chipId, rpIndex, iRpIndex);
532+ rpIndex = UNDEFINED_RING_ID;
533+ rc = TOR_CODE_BUG;
534 break;
535 }
536 else
537 {
538- l_ringId = iRingId;
539+ rpIndex = iRpIndex;
540 bFound = true;
541
542 if (!i_bTest)
543@@ -700,39 +646,62 @@ int ringidGetRingId1( ChipId_t i_chipId,
544 }
545 }
546
547- if (!rc && !bFound)
548+ if (rc)
549+ {
550+ return rc;
551+ }
552+ else if (bFound)
553+ {
554+ o_ringId = ringProps[rpIndex].ringId;
555+ rc = TOR_SUCCESS;
556+ }
557+ else
558 {
559- MY_DBG("ringidGetRingId1(): Did not find match to ringName=%s for chipId=%d."
560- " (Note, l_ringId=0x%x better be equal to UNDEFINED_RING_ID=0x%x)\n",
561- i_ringName.c_str(), i_chipId, l_ringId, UNDEFINED_RING_ID);
562+ MY_DBG("ringidGetRingId1(): Did not find match to ringName=%s for chipId=%u"
563+ " (Note, rpIndex=0x%x better be equal to UNDEFINED_RING_ID=0x%x)\n",
564+ i_ringName.c_str(), i_chipId, rpIndex, UNDEFINED_RING_ID);
565+ o_ringId = UNDEFINED_RING_ID;
566 rc = TOR_RING_NAME_NOT_FOUND;
567 }
568
569- o_ringId = l_ringId;
570-
571 return rc;
572 }
573
574
575+//
576+// Get ringName from ringId
577+//
578 int ringidGetRingName( ChipId_t i_chipId,
579 RingId_t i_ringId,
580 std::string& o_ringName )
581 {
582 int rc = INFRASTRUCT_RC_SUCCESS;
583+ RingProperties_t* ringProps = (RingProperties_t*)&P10_RID::RING_PROPERTIES;
584 std::string l_ringName;
585
586+ // Get the ring properties (rp) index
587+ RingId_t rpIndex = P10_RID::ringid_convert_ringId_to_rpIndex(i_ringId);
588+
589 switch (i_chipId)
590 {
591 case CID_P10:
592- if (i_ringId >= P10_RID::NUM_RING_IDS)
593+ if (rpIndex >= P10_RID::NUM_RING_IDS)
594 {
595- MY_ERR("ringidGetRingName(): ringId(=0x%x) >= NUM_RING_IDS(=0x%x) not allowed\n",
596- i_ringId, P10_RID::NUM_RING_IDS);
597+ MY_ERR("ringidGetRingName(): rpIndex(=0x%x) >= NUM_RING_IDS(=0x%x) not allowed"
598+ " and ringId=0x%x\n",
599+ rpIndex, P10_RID::NUM_RING_IDS, i_ringId);
600 rc = TOR_INVALID_RING_ID;
601 break;
602 }
603
604- l_ringName = (std::string)P10_RID::RING_PROPERTIES[i_ringId].ringName;
605+ l_ringName = (std::string)ringProps[rpIndex].ringName;
606+
607+ if (ringProps[rpIndex].ringId == HOLE_RING_ID)
608+ {
609+ rc = TOR_HOLE_RING_ID;
610+ break;
611+ }
612+
613 break;
614
615 default:
616diff --git a/src/import/chips/common/utils/imageProcs/common_ringId.H b/src/import/chips/common/utils/imageProcs/common_ringId.H
617index 925c321..c2d0e59 100644
618--- a/src/import/chips/common/utils/imageProcs/common_ringId.H
619+++ b/src/import/chips/common/utils/imageProcs/common_ringId.H
620@@ -52,6 +52,7 @@ typedef uint16_t TorOffset_t; // Type for offset value to various TOR obje
621 typedef uint8_t MyBool_t; // false:0, true:1, undefined:UNDEFINED_BOOLEAN
622
623 #define UNDEFINED_RING_ID (RingId_t)0xffff
624+#define HOLE_RING_ID (RingId_t)0xeeee
625 #define UNDEFINED_SCOM_ADDR (uint32_t)0xffffffff
626 #define UNDEFINED_RING_CLASS (RingClass_t)0xffff
627 #define UNDEFINED_CHIPLET_TYPE (ChipletType_t)0xff
628@@ -222,11 +223,12 @@ enum RingMarker
629 RMRK_TIME = (RingClass_t)0b0000000000010000, // Time ring marker bit
630 RMRK_MVPD_PDG = (RingClass_t)0b0000000010000000, // MVPD #G gptr/time ring marker bit
631 RMRK_MVPD_PDP = (RingClass_t)0b0000000100000000, // MVPD #P pll ring marker bit
632- RMRK_MVPD_PDR = (RingClass_t)0b0000001000000000, // MVPD #G repr ring marker bit
633- RMRK_MVPD_NEST = (RingClass_t)0b0000010000000000, // NEST (non-EQ) ring marker bit
634- RMRK_MVPD_EQ = (RingClass_t)0b0000100000000000, // EQ (non-core) ring marker bit
635- RMRK_MVPD_CORE = (RingClass_t)0b0001000000000000, // Core ring marker bit
636- RMRK_SCAN_BY_QME = (RingClass_t)0b0010000000000000, // QME scannable ring marker bit
637+ RMRK_MVPD_PDR = (RingClass_t)0b0000001000000000, // MVPD #R repr ring marker bit
638+ RMRK_MVPD_PDS = (RingClass_t)0b0000010000000000, // MVPD #S dts ring marker bit
639+ RMRK_MVPD_NEST = (RingClass_t)0b0000100000000000, // NEST (non-EQ) ring marker bit
640+ RMRK_MVPD_EQ = (RingClass_t)0b0001000000000000, // EQ (non-core) ring marker bit
641+ RMRK_MVPD_CORE = (RingClass_t)0b0010000000000000, // Core ring marker bit
642+ RMRK_SCAN_BY_QME = (RingClass_t)0b0100000000000000, // QME scannable ring marker bit
643 };
644
645 //
646@@ -245,6 +247,9 @@ enum RingMarker
647 #define RCLS_MVPD_PDR_NEST (RMRK_MVPD_PDR | RMRK_MVPD_NEST)
648 #define RCLS_MVPD_PDR_EQ (RMRK_MVPD_PDR | RMRK_MVPD_EQ)
649 #define RCLS_MVPD_PDR_CORE (RMRK_MVPD_PDR | RMRK_MVPD_CORE)
650+#define RCLS_MVPD_PDS_NEST (RMRK_MVPD_PDS | RMRK_MVPD_NEST)
651+#define RCLS_MVPD_PDS_EQ (RMRK_MVPD_PDS | RMRK_MVPD_EQ)
652+#define RCLS_MVPD_PDS_CORE (RMRK_MVPD_PDS | RMRK_MVPD_CORE)
653 // MVPD keyword mask
654 #define RCLS_MVPD_MASK (RMRK_MVPD_PDG | RMRK_MVPD_PDP | RMRK_MVPD_PDR)
655
656@@ -273,6 +278,7 @@ enum RingRequest
657 typedef struct
658 {
659 #ifndef __PPE__
660+ RingId_t ringId;
661 char ringName[MAX_RING_NAME_LENGTH];
662 uint32_t scanScomAddr;
663 #endif
664@@ -323,7 +329,7 @@ typedef struct
665 #define TOR_INVALID_MAGIC_NUMBER INFRASTRUCT_NOOF_RCS + 2
666 #define TOR_INVALID_CHIP_ID INFRASTRUCT_NOOF_RCS + 3
667 #define TOR_INVALID_CHIPLET_TYPE INFRASTRUCT_NOOF_RCS + 4
668-#define TOR_INVALID_RING_ID INFRASTRUCT_NOOF_RCS + 5
669+#define TOR_INVALID_RING_ID INFRASTRUCT_NOOF_RCS + 5 // ringId falls outside Mvpd and Ekb range
670 #define TOR_INVALID_CHIPLET_ID INFRASTRUCT_NOOF_RCS + 6
671 #define TOR_INVALID_RING_REQUEST INFRASTRUCT_NOOF_RCS + 7
672 #define TOR_UNSUPPORTED_RING_SECTION INFRASTRUCT_NOOF_RCS + 8
673@@ -341,7 +347,7 @@ typedef struct
674 #define TOR_RING_NAME_NOT_FOUND INFRASTRUCT_NOOF_RCS + 20
675 #define TOR_NO_RINGS_FOR_CHIP INFRASTRUCT_NOOF_RCS + 21
676 #define TOR_DYN_RING_NOT_FOUND INFRASTRUCT_NOOF_RCS + 22
677-#define TOR_HOLE_RING_ID INFRASTRUCT_NOOF_RCS + 23
678+#define TOR_HOLE_RING_ID INFRASTRUCT_NOOF_RCS + 23 // ringId is a "hole" ring
679
680 // This function returns the main ring properties list associated w/the chip ID.
681 int ringid_get_ringProps( ChipId_t i_chipId,
682@@ -388,6 +394,9 @@ MyBool_t ringid_is_mvpd_ring( ChipId_t i_chipId,
683 MyBool_t ringid_is_gptr_ring( ChipId_t i_chipId,
684 RingId_t i_ringId );
685
686+// Check if ring is a Common or Instance ring
687+MyBool_t ringid_is_instance_ring( RingId_t i_rpIndex);
688+
689 // Check if ring has derivative, eg if it has bucket rings. Note that the actual
690 // derivative ring itself, eg the *_bucket_n ring, will *not* be marked as derivative.
691 // Only the "root ring", eg that does *not* have the *_bucket_n suffix, will be marked.
692@@ -425,17 +434,6 @@ int ringidGetRootRingId( ChipId_t i_chipId,
693 RingId_t& o_ringId,
694 bool i_bTest = false );
695
696-// This function returns the ringId associated with the effective ring index within a chiplet.
697-// (Note that "effective" means the index is void of the instance marker bit.)
698-int ringidGetRingId2( ChipId_t i_chipId,
699- uint32_t i_torMagic,
700- ChipletType_t i_chipletType, // Ignored if only one chiplet in torMagic
701- uint8_t i_idxRing, // The eEffective ring index within chiplet's
702- // common or instance ring section
703- MyBool_t i_bInstCase, // =0 common ring, =1 instance ring
704- RingId_t& o_ringId,
705- bool i_bTest = false );
706-
707 // This fumction returns the ringClass associated with the ringId.
708 int ringidGetRingClass( ChipId_t i_chipId,
709 RingId_t i_ringId,
710diff --git a/src/import/chips/p10/procedures/hwp/accessors/p10_get_mvpd_ring.C b/src/import/chips/p10/procedures/hwp/accessors/p10_get_mvpd_ring.C
711index d439f9c..353fcf6 100644
712--- a/src/import/chips/p10/procedures/hwp/accessors/p10_get_mvpd_ring.C
713+++ b/src/import/chips/p10/procedures/hwp/accessors/p10_get_mvpd_ring.C
714@@ -5,7 +5,7 @@
715 /* */
716 /* OpenPOWER HostBoot Project */
717 /* */
718-/* Contributors Listed Below - COPYRIGHT 2012,2019 */
719+/* Contributors Listed Below - COPYRIGHT 2012,2020 */
720 /* [+] International Business Machines Corp. */
721 /* */
722 /* */
723@@ -60,7 +60,7 @@ extern "C"
724 {
725 fapi2::ReturnCode l_fapirc;
726
727- FAPI_DBG("getMvpdRing: Called w/ringId=0x%x, chipletSel=0x%8x, size=0x%x",
728+ FAPI_DBG("getMvpdRing: Called w/ringId=0x%x, chipletSel=0x%08x and bufsize=0x%x",
729 i_ringId,
730 i_chipletSel,
731 io_rRingBufsize );
732@@ -76,7 +76,7 @@ extern "C"
733 io_rRingBufsize );
734
735
736- FAPI_DBG("getMvpdRing: exit rc=0x%x",
737+ FAPI_DBG("getMvpdRing: Exit w/rc=0x%08x",
738 static_cast<uint32_t>(l_fapirc) );
739
740 return l_fapirc;
741diff --git a/src/import/chips/p10/procedures/hwp/accessors/p10_mvpd_ring_funcs.C b/src/import/chips/p10/procedures/hwp/accessors/p10_mvpd_ring_funcs.C
742index be8b6ea..da74045 100644
743--- a/src/import/chips/p10/procedures/hwp/accessors/p10_mvpd_ring_funcs.C
744+++ b/src/import/chips/p10/procedures/hwp/accessors/p10_mvpd_ring_funcs.C
745@@ -483,12 +483,10 @@ extern "C"
746 // found it, return pointer to ring
747 *o_pScanData = l_pScanData;
748
749- FAPI_DBG("mvpdRingFuncFindHdr: found RS4 ring for "
750- "chipletSel 0x%08x and ringId %d "
751- "at address 0x%x and with size %d",
752+ FAPI_DBG("mvpdRingFuncFindHdr: Found RS4 ring for chipletSel=0x%08x and"
753+ " ringId=0x%x and ring size=%u",
754 i_chipletSel,
755 i_ringId,
756- *o_pScanData,
757 be16toh((*o_pScanData)->iv_size));
758 }
759 }
760@@ -552,20 +550,19 @@ extern "C"
761 uint32_t l_prevLen;
762 uint32_t l_recordBufLenLeft = i_recordBufLen;
763
764- FAPI_DBG("mvpdRingFuncFind: Called w/chipletSel=0x%08x, ringId=0x%x ",
765+ FAPI_IMP("mvpdRingFuncFind: Enter w/chipletSel=0x%08x and ringId=0x%x ",
766 i_chipletSel,
767 i_ringId);
768
769- // Find first RSA data block in ring (fixed offset defined by
770- // MVPD spec)
771+ // Find first RSA data block in ring (fixed offset defined by MVPD spec)
772 //
773- // First byte in record should be the version number, skip
774- // over this.
775+ // First byte in record's keyword is the version number which we skip
776 //
777- FAPI_DBG( "mvpdRingFuncFind: record version = 0x%x", *i_pRecordBuf );
778 i_pRecordBuf++;
779 l_recordBufLenLeft--;
780
781+ o_rRingLen = 0; // Just making sure this is zero in case of a fail or not found
782+
783 do
784 {
785 // let's track the previous size of the remaining buffer,
786@@ -610,12 +607,6 @@ extern "C"
787 {
788 o_rpRing = (uint8_t*)l_pScanData;
789 o_rRingLen = be16toh(l_pScanData->iv_size);
790-
791- // Dump record info for debug
792- FAPI_DBG("mvpdRingFuncFind:ringId=0x%x chipletSel=0x%08x size=0x%x",
793- i_ringId,
794- i_chipletSel,
795- be16toh(l_pScanData->iv_size));
796 }
797 else
798 {
799@@ -629,13 +620,12 @@ extern "C"
800 // get current error
801 l_fapirc = fapi2::current_err;
802
803- FAPI_DBG("mvpdRingFuncFind: exit *ring= 0x%p", o_rpRing);
804- FAPI_IMP("mvpdRingFuncFind: exit chipletSel=0x%08x, ringId=0x%x size=0x%x"
805- " rc=0x%x",
806+ FAPI_IMP("mvpdRingFuncFind: Exit w/rc=0x%08x for chipletSel=0x%08x, ringId=0x%x and"
807+ " ring size=%u (if size==0, then something failed)",
808+ static_cast<uint32_t>(l_fapirc),
809 i_chipletSel,
810 i_ringId,
811- o_rRingLen,
812- static_cast<uint32_t>(l_fapirc) );
813+ o_rRingLen);
814
815 return l_fapirc;
816 }
817@@ -717,7 +707,7 @@ extern "C"
818 "Test0x80: iv_ringId=0x%x vs i_ringId=0x%x \n"
819 "Test0x80: iv_scanAddr=0x%x vs i_chipletSel=0x%08x \n"
820 "Test0x80: iv_size=0x%x vs i_ringBufsize=0x%x vs sizeof(CompressedScanData)=0x%x \n"
821- "Fail test vector: 0x0x%02x",
822+ "Fail test vector: 0x%02x",
823 be16toh(i_pRingBuf->iv_magic), RS4_MAGIC,
824 be16toh(i_pRingBuf->iv_ringId), i_ringId,
825 be32toh(i_pRingBuf->iv_scanAddr), i_chipletSel,
826@@ -779,7 +769,7 @@ extern "C"
827 }
828
829 // we're good, copy data into the passed-in buffer
830- FAPI_DBG( "mvpdRingFuncGet: memcpy 0x%p 0x%p 0x%x",
831+ FAPI_DBG( "mvpdRingFuncGet: memcpy(0x%p,0x%p,%u)",
832 i_pCallerRingBuf,
833 i_pRing,
834 i_ringLen );
835@@ -824,9 +814,9 @@ extern "C"
836 io_rCallerRingBufLen = i_ringLen;
837 }
838
839- FAPI_DBG( "mvpdRingFuncGet: exit bufsize= 0x%x rc= 0x%x",
840- io_rCallerRingBufLen,
841- static_cast<uint32_t>(l_fapirc) );
842+ FAPI_DBG( "mvpdRingFuncGet: Exit w/rc=0x%08x and w/bufsize=0x%x",
843+ static_cast<uint32_t>(l_fapirc),
844+ io_rCallerRingBufLen );
845
846 return l_fapirc;
847 }
848diff --git a/src/import/chips/p10/procedures/hwp/customize/p10_ipl_customize.C b/src/import/chips/p10/procedures/hwp/customize/p10_ipl_customize.C
849index f5f743b..eeb380b 100644
850--- a/src/import/chips/p10/procedures/hwp/customize/p10_ipl_customize.C
851+++ b/src/import/chips/p10/procedures/hwp/customize/p10_ipl_customize.C
852@@ -44,7 +44,7 @@
853
854 #include <p10_ipl_customize.H>
855 #include <p10_ipl_image.H>
856-#include <p10_ring_id.H>
857+#include <p10_ringId.H>
858 #include <p10_tor.H>
859 #include <p10_scan_compression.H>
860 #include <p10_infrastruct_help.H>
861@@ -187,7 +187,7 @@ fapi2::ReturnCode writePG(
862 set_CHIP_UNIT_POS(l_unit_id).
863 set_PG_INDEX(l_pg_idx).
864 set_IMG_PG_ENTRIES(IMG_PG_ENTRIES),
865- "Code bug: Invalid translation from PERV chip unit position"
866+ "CODE BUG: Invalid translation from PERV chip unit position"
867 " to image PG index: l_pg_idx=%d, IMG_PG_ENTRIES=%d",
868 l_pg_idx, IMG_PG_ENTRIES );
869
870@@ -321,7 +321,7 @@ fapi_try_exit:
871 // void* io_rs4Ring: Contains target RS4 ring on input and final overlaid RS4 ring on output
872 // void* io_workBuf: Work buffer (has final overlaid raw ring on output)
873 // void* i_ovlyRawRing: Raw data+care overlay ring
874-// uint32_t i_ovlyRawSize: Overlay raw ring size
875+// uint32_t i_ovlyRawLength: Overlay raw ring bit length
876 // CompressedScanData* i_rs4RefHdr: Reference ring to get header data from (assumed volatile)
877 // uint8_t i_rs4TypeField: iv_type to be used for final RS4 ring
878 //
879@@ -339,7 +339,7 @@ fapi2::ReturnCode apply_overlay_ring(
880 void* io_rs4Ring,
881 void* io_workBuf,
882 void* i_ovlyRawRing,
883- uint32_t i_ovlyRawSize,
884+ uint32_t i_ovlyRawLength,
885 CompressedScanData* i_rs4RefHeader,
886 uint8_t i_rs4TypeField)
887 {
888@@ -351,11 +351,9 @@ fapi2::ReturnCode apply_overlay_ring(
889 // Pt to our Target/Final raw work buffers
890 uint8_t* dataTgt = (uint8_t*)io_workBuf;
891 uint8_t* careTgt = (uint8_t*)io_workBuf + MAX_RING_BUF_SIZE / 2;
892- uint32_t tgtRawSize = 0;
893+ uint32_t tgtRawLength = 0;
894 MyBool_t bOvrd = UNDEFINED_BOOLEAN;
895
896- FAPI_DBG("Entering apply_overlay_ring");
897-
898 // Copy the key RS4 ref header settings into local struct before we, possibly,
899 // contaminate i_rs4RefHeader as this may be pointing to one of our work
900 // buffers.
901@@ -365,12 +363,15 @@ fapi2::ReturnCode apply_overlay_ring(
902 l_rs4RefHeader.iv_ringId = be16toh(i_rs4RefHeader->iv_ringId);
903 l_rs4RefHeader.iv_scanAddr = be32toh(i_rs4RefHeader->iv_scanAddr);
904
905+ FAPI_DBG("Entering apply_overlay_ring w/ringId=0x%0x and rawLength=%u",
906+ l_rs4RefHeader.iv_ringId, i_ovlyRawLength);
907+
908 // Decompress the ring to apply overlay onto, io_rs4Ring.
909 l_rc = _rs4_decompress(
910 dataTgt,
911 careTgt,
912 MAX_RING_BUF_SIZE / 2, // Max allowable raw ring size (in bytes)
913- &tgtRawSize, // Actual raw ring size (in bits) on return.
914+ &tgtRawLength, // Actual raw ring size (in bits) on return.
915 (CompressedScanData*)io_rs4Ring );
916
917 FAPI_ASSERT( l_rc == INFRASTRUCT_RC_SUCCESS,
918@@ -385,13 +386,13 @@ fapi2::ReturnCode apply_overlay_ring(
919 l_rc, l_rs4RefHeader.iv_ringId, MAX_RING_BUF_SIZE );
920
921 // Compare raw Target and Overlay raw ring lengths
922- FAPI_ASSERT( i_ovlyRawSize == tgtRawSize,
923+ FAPI_ASSERT( i_ovlyRawLength == tgtRawLength,
924 fapi2::XIPC_TARGET_OVLY_RAW_RING_LENGTH_MISMATCH().
925 set_CHIP_TARGET(i_procTarget).
926- set_TARGET_RAW_RING_LENGTH(tgtRawSize).
927- set_OVLY_RAW_RING_LENGTH(i_ovlyRawSize),
928+ set_TARGET_RAW_RING_LENGTH(tgtRawLength).
929+ set_OVLY_RAW_RING_LENGTH(i_ovlyRawLength),
930 "ERROR: Target ring raw length(=%u) and overlay ring raw length(=%u) don't match.",
931- tgtRawSize, i_ovlyRawSize);
932+ tgtRawLength, i_ovlyRawLength);
933
934 // Check ring's iv_type is either override or flush
935 bOvrd = rs4_is_ovrd(&l_rs4RefHeader);
936@@ -413,7 +414,7 @@ fapi2::ReturnCode apply_overlay_ring(
937 //
938 uint32_t i, j;
939
940- for (i = 0; i < tgtRawSize / 8; i++)
941+ for (i = 0; i < tgtRawLength / 8; i++)
942 {
943 if (careOvly[i] > 0)
944 {
945@@ -445,15 +446,15 @@ fapi2::ReturnCode apply_overlay_ring(
946 }
947
948 // Processing remainder of data & care bits (mod 8)
949- if (tgtRawSize % 8)
950+ if (tgtRawLength % 8)
951 {
952- i = tgtRawSize / 8;
953+ i = tgtRawLength / 8;
954
955- careOvly[i] &= ~(0xFF << (8 - (tgtRawSize % 8)));
956+ careOvly[i] &= ~(0xFF << (8 - (tgtRawLength % 8)));
957
958 if (careOvly[i] > 0)
959 {
960- for (j = 0; j < tgtRawSize % 8; j++)
961+ for (j = 0; j < tgtRawLength % 8; j++)
962 {
963 if (careOvly[i] & (0x80 >> j))
964 {
965@@ -486,7 +487,7 @@ fapi2::ReturnCode apply_overlay_ring(
966 MAX_RING_BUF_SIZE,
967 dataTgt,
968 careTgt,
969- tgtRawSize,
970+ tgtRawLength,
971 l_rs4RefHeader.iv_scanAddr,
972 l_rs4RefHeader.iv_ringId,
973 UNDEFINED_RS4_SELECTOR,
974@@ -1103,33 +1104,49 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
975 Rs4Selector_t i_numberOfFeatures,
976 void* i_dynamicRingSection )
977 {
978- ReturnCode l_fapiRc = fapi2::FAPI2_RC_SUCCESS;
979+ ReturnCode l_fapiRc = fapi2::FAPI2_RC_SUCCESS;
980 fapi2::current_err = fapi2::FAPI2_RC_SUCCESS;
981- int l_rc = INFRASTRUCT_RC_SUCCESS;;
982-
983- FAPI_DBG("_fetch_and_insert_vpd_ring: (ringId,chipletSel) = (0x%x,0x%08x)",
984- i_ringId, i_chipletSel);
985+ int l_rc = INFRASTRUCT_RC_SUCCESS;;
986+ RingId_t rpIndex = UNDEFINED_RING_ID;
987+ RingClass_t ringClass = UNDEFINED_RING_CLASS;
988+ TorHeader_t* torHeader = (TorHeader_t*)i_ringSection;
989
990 void* vpdRing = NULL;
991 uint32_t vpdRingSize = 0;
992 void* finalVpdRing = NULL;
993- MvpdKeyword l_mvpdKeyword;
994- uint8_t l_chipletId = (uint8_t)(i_chipletSel >> 24);
995+ MvpdKeyword mvpdKeyword;
996+ uint8_t chipletId = (uint8_t)(i_chipletSel >> 24);
997+
998+ FAPI_DBG("_fetch_and_insert_vpd_ring: (ringId,chipletSel) = (0x%x,0x%08x)",
999+ i_ringId, i_chipletSel);
1000+
1001+ // Check the ringId validity, then get the ring properties (rp) index
1002+ l_rc = ringid_check_ringId( torHeader->chipId, i_ringId);
1003+
1004+ FAPI_ASSERT( l_rc == TOR_SUCCESS,
1005+ fapi2::XIPC_CODE_BUG().
1006+ set_CHIP_TARGET(i_procTarget).
1007+ set_OCCURRENCE(3),
1008+ "CODE BUG(3): ringid_check_ringId() failed w/rc=0x%08x. Calling code must make"
1009+ " sure it passes valid ringId(=0x%x) to _fetch(). Fix calling code.\n",
1010+ l_rc, i_ringId);
1011
1012- RingClass_t l_ringClass = i_ringProps[i_ringId].ringClass;
1013+ rpIndex = ringid_convert_ringId_to_rpIndex( i_ringId);
1014
1015- switch (l_ringClass & RCLS_MVPD_MASK)
1016+ ringClass = i_ringProps[rpIndex].ringClass;
1017+
1018+ switch (ringClass & RCLS_MVPD_MASK)
1019 {
1020 case RMRK_MVPD_PDG: // #G Time rings
1021- l_mvpdKeyword = fapi2::MVPD_KEYWORD_PDG;
1022+ mvpdKeyword = fapi2::MVPD_KEYWORD_PDG;
1023 break;
1024
1025 case RMRK_MVPD_PDP: // #P Pll rings
1026- l_mvpdKeyword = fapi2::MVPD_KEYWORD_PDP;
1027+ mvpdKeyword = fapi2::MVPD_KEYWORD_PDP;
1028 break;
1029
1030 case RMRK_MVPD_PDR: // #R Repair rings
1031- l_mvpdKeyword = fapi2::MVPD_KEYWORD_PDR;
1032+ mvpdKeyword = fapi2::MVPD_KEYWORD_PDR;
1033 break;
1034
1035 default:
1036@@ -1137,11 +1154,11 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
1037 fapi2::XIPC_INVALID_MVPD_RINGCLASS().
1038 set_CHIP_TARGET(i_procTarget).
1039 set_RING_ID(i_ringId).
1040- set_RING_CLASS(l_ringClass).
1041+ set_RING_CLASS(ringClass).
1042 set_KWD_MASK(RCLS_MVPD_MASK),
1043- "Code bug: Unsupported value of ringClass (=0x%4x) or keyword"
1044+ "CODE BUG: Unsupported value of ringClass (=0x%4x) or keyword"
1045 " mask (=0x%4x) for ringId=0x%x",
1046- l_ringClass, RCLS_MVPD_MASK, i_ringId );
1047+ ringClass, RCLS_MVPD_MASK, i_ringId );
1048 break;
1049 }
1050
1051@@ -1158,7 +1175,7 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
1052
1053 l_fapiRc = getMvpdRing( i_procTarget,
1054 MVPD_RECORD_CP00,
1055- l_mvpdKeyword,
1056+ mvpdKeyword,
1057 i_chipletSel,
1058 i_ringId,
1059 (uint8_t*)vpdRing,
1060@@ -1194,7 +1211,7 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
1061 set_CHIPLET_SEL(i_chipletSel).
1062 set_MVPD_CHIPLET_SEL(vpdChipletSel).
1063 set_RING_ID(i_ringId),
1064- "_fetch_and_insert_vpd_ring: Code bug: VPD ring's chipletSel"
1065+ "CODE BUG: _fetch_and_insert_vpd_ring: VPD ring's chipletSel"
1066 " (=0x%08x) doesn't match the requested chipletSel (=0x%08x)",
1067 vpdChipletSel, i_chipletSel );
1068
1069@@ -1203,17 +1220,17 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
1070 fapi2::XIPC_MVPD_RING_SIZE_MESS().
1071 set_CHIP_TARGET(i_procTarget).
1072 set_RING_ID(i_ringId).
1073- set_CHIPLET_ID(l_chipletId).
1074+ set_CHIPLET_ID(chipletId).
1075 set_RING_BUFFER_SIZE(i_ringBufSize1).
1076 set_MVPD_RING_SIZE(vpdRingSize),
1077- "_fetch_and_insert_vpd_ring: Code bug: VPD ring size (=0x%X) exceeds"
1078+ "ERROR: _fetch_and_insert_vpd_ring: MVPD ring size (=0x%X) exceeds"
1079 " allowed ring buffer size (=0x%X)",
1080 vpdRingSize, i_ringBufSize1 );
1081
1082 // Check for Gptr ring in the .overlays section and if found overlay it onto
1083 // the Mvpd-Gptr ring. Further, check for Gptr rings in the .dynamic section
1084 // and if found overlay them onto the previously overlaid Gptr ring.
1085- if ( l_ringClass & RMRK_GPTR_OVLY )
1086+ if ( ringClass & RMRK_GPTR_OVLY )
1087 {
1088 FAPI_TRY( process_gptr_rings(
1089 i_procTarget,
1090@@ -1270,19 +1287,19 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
1091 set_CHIP_TARGET(i_procTarget).
1092 set_LOCAL_RC(l_rc).
1093 set_RING_ID(i_ringId).
1094- set_CHIPLET_ID(l_chipletId).
1095+ set_CHIPLET_ID(chipletId).
1096 set_REDUNDANT(redundant).
1097 set_OCCURRENCE(1),
1098 "ERROR: rs4_redundant failed w/rc=0x%08x or redundant=%u for"
1099 " ringId=0x%x, chipletId=0x%02x, occurrence=1 ",
1100- l_rc, redundant, i_ringId, l_chipletId );
1101+ l_rc, redundant, i_ringId, chipletId );
1102
1103 if (redundant)
1104 {
1105 io_ringStatusInMvpd = RING_REDUNDANT;
1106
1107 FAPI_DBG("Skipping redundant MVPD ring: ringId=0x%x, chipletId=0x%02x ",
1108- i_ringId, l_chipletId);
1109+ i_ringId, chipletId);
1110 fapi2::current_err = RC_XIPC_RING_IS_REDUNDANT;
1111 goto fapi_try_exit;
1112 }
1113@@ -1312,7 +1329,7 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
1114 set_SIZE_OF_THIS_RING(vpdRingSize).
1115 set_MAX_RING_SECTION_SIZE(i_maxRingSectionSize).
1116 set_RING_ID(i_ringId).
1117- set_CHIPLET_ID(l_chipletId).
1118+ set_CHIPLET_ID(chipletId).
1119 set_CURRENT_BOOT_CORE_MASK(io_bootCoreMask),
1120 "Ran out of image buffer space trying to append a ring"
1121 " to the .rings section\n"
1122@@ -1323,7 +1340,7 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
1123 "maxRingSectionSize: %d\n"
1124 "Current bootCoreMask: 0x%08x",
1125 i_ringId,
1126- l_chipletId,
1127+ chipletId,
1128 vpdRingSize,
1129 io_ringSectionSize,
1130 i_maxRingSectionSize,
1131@@ -1335,7 +1352,7 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
1132 i_ringSection,
1133 i_maxRingSectionSize,
1134 i_ringId,
1135- l_chipletId,
1136+ chipletId,
1137 finalVpdRing );
1138
1139 FAPI_ASSERT( l_rc == INFRASTRUCT_RC_SUCCESS,
1140@@ -1347,11 +1364,11 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
1141 "tor_append_ring() failed in sysPhase=%d w/rc=%d for ringId=0x%x",
1142 i_sysPhase, l_rc, i_ringId );
1143
1144- io_ringSectionSize = be32toh(((TorHeader_t*)i_ringSection)->size);
1145+ io_ringSectionSize = be32toh(torHeader->size);
1146
1147 FAPI_IMP("Successfully appended Mvpd ring w/(ringId,chipletId)=(0x%x,0x%02x) and now"
1148 " ringSectionSize=%u",
1149- i_ringId, l_chipletId, io_ringSectionSize);
1150+ i_ringId, chipletId, io_ringSectionSize);
1151 }
1152 else if ((uint32_t)l_fapiRc == RC_MVPD_RING_NOT_FOUND)
1153 {
1154@@ -1362,7 +1379,7 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
1155 // rings we're looking for in Mvpd really should be represented there.
1156 FAPI_DBG("INFO(NOT-A-BUG): _fetch_and_insert_vpd_rings(): The ring w/"
1157 "(ringId,chipletId)=(0x%x,0x%02x) was not found.",
1158- i_ringId, l_chipletId);
1159+ i_ringId, chipletId);
1160
1161 fapi2::current_err = fapi2::FAPI2_RC_SUCCESS;
1162 }
1163@@ -1379,7 +1396,7 @@ fapi2::ReturnCode _fetch_and_insert_vpd_rings(
1164 fapi2::XIPC_MVPD_RING_SIZE_TOO_BIG().
1165 set_CHIP_TARGET(i_procTarget).
1166 set_RING_ID(i_ringId).
1167- set_CHIPLET_ID(l_chipletId).
1168+ set_CHIPLET_ID(chipletId).
1169 set_RING_BUFFER_SIZE(i_ringBufSize1).
1170 set_MVPD_RING_SIZE(vpdRingSize),
1171 "_fetch_and_insert_vpd_ring(): VPD ring size (=0x%X) exceeds"
1172@@ -1443,12 +1460,13 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1173 uint32_t i_ringBufSize2,
1174 void* i_ringBuf3,
1175 uint32_t i_ringBufSize3,
1176- uint32_t& io_bootCoreMask,
1177 std::map<Rs4Selector_t, Rs4Selector_t>& i_idxFeatureMap,
1178 std::map<RingId_t, uint64_t>& io_ringIdFeatureVecMap,
1179 Rs4Selector_t i_numberOfFeatures,
1180 void* i_dynamicRingSection,
1181- uint8_t i_ddLevel )
1182+ uint8_t i_ddLevel,
1183+ RingProperties_t* i_ringProps,
1184+ uint32_t& io_bootCoreMask )
1185 {
1186
1187 ReturnCode l_fapiRc = fapi2::FAPI2_RC_SUCCESS;
1188@@ -1498,45 +1516,34 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1189 // 1- Add all NEST rings
1190 // 2- Add QUAD rings in EC order
1191
1192- RingId_t l_ringId;
1193- RingClass_t l_ringClass;
1194- RingProperties_t* l_ringProps;
1195+ RingId_t rpIndex; // Ring properties (rp) index counter
1196+ RingClass_t ringClass;
1197 ChipletData_t* l_chipletData;
1198 ChipletData_t* l_chipletDataEQ, *l_chipletDataEC;
1199 uint8_t l_chipletId; // Nibbles {0,1} of scanScomAddr
1200 uint32_t l_regionSel; // Nibbles {2,4,5,6} of scanScomAddr (region select target)
1201 uint32_t l_chipletSel; // Combination of chipletId and regionSel
1202
1203- l_rc = ringid_get_ringProps( CID_P10, &l_ringProps);
1204-
1205- FAPI_ASSERT( l_rc == INFRASTRUCT_RC_SUCCESS,
1206- fapi2::XIPC_RINGID_RINGPROPS_ERROR().
1207- set_CHIP_TARGET(i_procTarget).
1208- set_LOCAL_RC(l_rc).
1209- set_OCCURRENCE(1),
1210- "ringid_get_ringProps(): Failed w/rc=%i for occurrence=1",
1211- l_rc );
1212-
1213
1214 // ----------------------------------------------------
1215 // 1- Add all common rings (ie, non-EQ/core repr rings)
1216 // ----------------------------------------------------
1217 l_ringType = COMMON_RING;
1218
1219- for ( l_ringId = 0; l_ringId < NUM_RING_IDS; l_ringId++ )
1220+ for ( rpIndex = 0; rpIndex < NUM_RING_IDS; rpIndex++ )
1221 {
1222
1223- l_ringClass = l_ringProps[l_ringId].ringClass;
1224+ ringClass = i_ringProps[rpIndex].ringClass;
1225
1226- if ( ( l_ringClass != UNDEFINED_RING_CLASS ) &&
1227- ( l_ringClass & RCLS_MVPD_MASK ) &&
1228- ( (l_ringClass & RCLS_MVPD_PDR_EQ) != RCLS_MVPD_PDR_EQ ) &&
1229- ( (l_ringClass & RCLS_MVPD_PDR_CORE) != RCLS_MVPD_PDR_CORE ) )
1230+ if ( ( ringClass != UNDEFINED_RING_CLASS ) &&
1231+ ( ringClass & RCLS_MVPD_MASK ) &&
1232+ ( (ringClass & RCLS_MVPD_PDR_EQ) != RCLS_MVPD_PDR_EQ ) &&
1233+ ( (ringClass & RCLS_MVPD_PDR_CORE) != RCLS_MVPD_PDR_CORE ) )
1234 {
1235 l_rc = ringid_get_chipletProps( CID_P10,
1236 torMagic,
1237 torVersion,
1238- l_ringProps[l_ringId].chipletType,
1239+ i_ringProps[rpIndex].chipletType,
1240 &l_chipletData );
1241
1242 FAPI_ASSERT( l_rc == INFRASTRUCT_RC_SUCCESS,
1243@@ -1545,16 +1552,16 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1244 set_LOCAL_RC(l_rc).
1245 set_TOR_MAGIC(torMagic).
1246 set_TOR_VER(torVersion).
1247- set_CHIPLET_TYPE(l_ringProps[l_ringId].chipletType).
1248- set_RING_ID(l_ringId).
1249+ set_CHIPLET_TYPE(i_ringProps[rpIndex].chipletType).
1250+ set_RING_ID(i_ringProps[rpIndex].ringId).
1251 set_OCCURRENCE(1),
1252 "ringid_get_chipletProps(): Failed w/rc=%i for"
1253 " TOR magic = 0x%04x, TOR version = %d,"
1254 " chipletType = %d, ringId = 0x%x,"
1255 " occurrence=1",
1256 l_rc, torMagic, torVersion,
1257- l_ringProps[l_ringId].chipletType,
1258- l_ringId );
1259+ i_ringProps[rpIndex].chipletType,
1260+ i_ringProps[rpIndex].ringId );
1261
1262 l_chipletId = l_chipletData->chipletBaseId;
1263 l_chipletSel = ((uint32_t)l_chipletId) << 24;
1264@@ -1564,7 +1571,7 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1265 // - Fetch QME scannable VPD rings for QME.
1266
1267 if ( i_sysPhase == SYSPHASE_HB_SBE ||
1268- ( i_sysPhase == SYSPHASE_RT_QME && ( l_ringClass & RMRK_SCAN_BY_QME ) ) )
1269+ ( i_sysPhase == SYSPHASE_RT_QME && ( ringClass & RMRK_SCAN_BY_QME ) ) )
1270 {
1271 l_fapiRc = _fetch_and_insert_vpd_rings (
1272 i_procTarget,
1273@@ -1580,8 +1587,8 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1274 i_ringBufSize2,
1275 i_ringBuf3,
1276 i_ringBufSize3,
1277- l_ringProps,
1278- l_ringId,
1279+ i_ringProps,
1280+ i_ringProps[rpIndex].ringId,
1281 l_chipletSel,
1282 l_ringStatusInMvpd,
1283 l_bImgOutOfSpace,
1284@@ -1630,7 +1637,7 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1285 continue;
1286 }
1287
1288- for ( l_ringId = 0; l_ringId < NUM_RING_IDS; l_ringId++ )
1289+ for ( rpIndex = 0; rpIndex < NUM_RING_IDS; rpIndex++ )
1290 {
1291
1292 //
1293@@ -1641,18 +1648,18 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1294 // consistent, and in case for some reason suddenly the QME is able to
1295 // "scan itself", we consider the RT_QME phase here as well.
1296 //
1297- l_ringClass = l_ringProps[l_ringId].ringClass;
1298+ ringClass = i_ringProps[rpIndex].ringClass;
1299
1300- if ( ( l_ringClass != UNDEFINED_RING_CLASS ) &&
1301- ( (l_ringClass & RCLS_MVPD_PDR_EQ) == RCLS_MVPD_PDR_EQ ) &&
1302+ if ( ( ringClass != UNDEFINED_RING_CLASS ) &&
1303+ ( (ringClass & RCLS_MVPD_PDR_EQ) == RCLS_MVPD_PDR_EQ ) &&
1304 ( i_sysPhase == SYSPHASE_HB_SBE ||
1305- ( i_sysPhase == SYSPHASE_RT_QME && (l_ringClass & RMRK_SCAN_BY_QME) ) ) )
1306+ ( i_sysPhase == SYSPHASE_RT_QME && (ringClass & RMRK_SCAN_BY_QME) ) ) )
1307 {
1308 l_rc = ringid_get_chipletProps(
1309 CID_P10,
1310 torMagic,
1311 torVersion,
1312- l_ringProps[l_ringId].chipletType,
1313+ i_ringProps[rpIndex].chipletType,
1314 &l_chipletDataEQ );
1315
1316 FAPI_ASSERT( l_rc == INFRASTRUCT_RC_SUCCESS,
1317@@ -1661,22 +1668,22 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1318 set_LOCAL_RC(l_rc).
1319 set_TOR_MAGIC(torMagic).
1320 set_TOR_VER(torVersion).
1321- set_CHIPLET_TYPE(l_ringProps[l_ringId].chipletType).
1322- set_RING_ID(l_ringId).
1323+ set_CHIPLET_TYPE(i_ringProps[rpIndex].chipletType).
1324+ set_RING_ID(i_ringProps[rpIndex].ringId).
1325 set_OCCURRENCE(2),
1326 "ringid_get_chipletProps(): Failed w/rc=%i for"
1327 " TOR magic = 0x%04x, TOR version = %d,"
1328 " chipletType = %d, ringId = 0x%x,"
1329 " occurrence=2",
1330 l_rc, torMagic, torVersion,
1331- l_ringProps[l_ringId].chipletType,
1332- l_ringId );
1333+ i_ringProps[rpIndex].chipletType,
1334+ i_ringProps[rpIndex].ringId );
1335
1336 l_chipletId = l_chipletDataEQ->chipletBaseId + eq;
1337 l_chipletSel = ((uint32_t)l_chipletId) << 24;
1338
1339 FAPI_DBG("EQ=%d; chipletId=0x%02x, ringName:%s",
1340- eq, l_chipletId, l_ringProps[l_ringId].ringName);
1341+ eq, l_chipletId, i_ringProps[rpIndex].ringName);
1342
1343 // Update for ring in scan mode
1344 l_ringStatusInMvpd = RING_SCAN;
1345@@ -1695,8 +1702,8 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1346 i_ringBufSize2,
1347 i_ringBuf3,
1348 i_ringBufSize3,
1349- l_ringProps,
1350- l_ringId,
1351+ i_ringProps,
1352+ i_ringProps[rpIndex].ringId,
1353 l_chipletSel,
1354 l_ringStatusInMvpd,
1355 l_bImgOutOfSpace,
1356@@ -1734,7 +1741,7 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1357
1358 } // Done w/fetch_and_insert() current EQ instance ring
1359
1360- } // End of for(l_ringId) for the current eq
1361+ } // End of for(rpIndex) for the current eq
1362
1363 //
1364 // At this point, we're done appending all possible EQ Mvpd rings for current eq.
1365@@ -1752,25 +1759,25 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1366 continue;
1367 }
1368
1369- for ( l_ringId = 0; l_ringId < NUM_RING_IDS; l_ringId++ )
1370+ for ( rpIndex = 0; rpIndex < NUM_RING_IDS; rpIndex++ )
1371 {
1372
1373 //
1374 // Determine if ringId belongs to relevant Mvpd #R EC ringClass. If so,
1375 // then try fetch the ring from Mvpd and append it to ring section.
1376 //
1377- l_ringClass = l_ringProps[l_ringId].ringClass;
1378+ ringClass = i_ringProps[rpIndex].ringClass;
1379
1380- if ( ( l_ringClass != UNDEFINED_RING_CLASS ) &&
1381- ( (l_ringClass & RCLS_MVPD_PDR_CORE) == RCLS_MVPD_PDR_CORE ) &&
1382+ if ( ( ringClass != UNDEFINED_RING_CLASS ) &&
1383+ ( (ringClass & RCLS_MVPD_PDR_CORE) == RCLS_MVPD_PDR_CORE ) &&
1384 ( i_sysPhase == SYSPHASE_HB_SBE ||
1385- ( i_sysPhase == SYSPHASE_RT_QME && (l_ringClass & RMRK_SCAN_BY_QME) ) ) )
1386+ ( i_sysPhase == SYSPHASE_RT_QME && (ringClass & RMRK_SCAN_BY_QME) ) ) )
1387 {
1388 l_rc = ringid_get_chipletProps(
1389 CID_P10,
1390 torMagic,
1391 torVersion,
1392- l_ringProps[l_ringId].chipletType,
1393+ i_ringProps[rpIndex].chipletType,
1394 &l_chipletDataEC );
1395
1396 FAPI_ASSERT( l_rc == INFRASTRUCT_RC_SUCCESS,
1397@@ -1779,16 +1786,16 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1398 set_LOCAL_RC(l_rc).
1399 set_TOR_MAGIC(torMagic).
1400 set_TOR_VER(torVersion).
1401- set_CHIPLET_TYPE(l_ringProps[l_ringId].chipletType).
1402- set_RING_ID(l_ringId).
1403+ set_CHIPLET_TYPE(i_ringProps[rpIndex].chipletType).
1404+ set_RING_ID(i_ringProps[rpIndex].ringId).
1405 set_OCCURRENCE(3),
1406 "ringid_get_chipletProps(): Failed w/rc=%i for"
1407 " TOR magic = 0x%04x, TOR version = %d,"
1408 " chipletType = %d, ringId = 0x%x,"
1409 " occurrence=3",
1410 l_rc, torMagic, torVersion,
1411- l_ringProps[l_ringId].chipletType,
1412- l_ringId );
1413+ i_ringProps[rpIndex].chipletType,
1414+ i_ringProps[rpIndex].ringId );
1415
1416 //
1417 // Calculate chipletSel target "ID" for this particular (eq,quadrant) combo
1418@@ -1804,7 +1811,7 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1419 // in the scanScomAddr, and see if it matches the current quadrant we're in:
1420 // - If there's a match, regionSel will have one bit set,
1421 // - If there's no match, regionSel will be zero.
1422- l_regionSel = l_ringProps[l_ringId].scanScomAddr & l_regionSel;
1423+ l_regionSel = i_ringProps[rpIndex].scanScomAddr & l_regionSel;
1424 // Final chipletSel to look for in Mvpd
1425 l_chipletSel = ( (uint32_t)l_chipletId << 24 ) | l_regionSel;
1426
1427@@ -1816,12 +1823,12 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1428 // ringIds scanScomAddr. Proceed to the next ringId.
1429 FAPI_DBG("EC=%d: chipletSel=0x%08x, ringName=%s (Skipping this ring"
1430 " because we're in wrong quadrant(=%d))",
1431- ec, l_chipletSel, l_ringProps[l_ringId].ringName, quadrant);
1432+ ec, l_chipletSel, i_ringProps[rpIndex].ringName, quadrant);
1433 continue;
1434 }
1435
1436 FAPI_DBG("EC=%d: chipletSel=0x%08x, ringName=%s",
1437- ec, l_chipletSel, l_ringProps[l_ringId].ringName);
1438+ ec, l_chipletSel, i_ringProps[rpIndex].ringName);
1439
1440 // Update for ring in scan mode
1441 l_ringStatusInMvpd = RING_SCAN;
1442@@ -1840,8 +1847,8 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1443 i_ringBufSize2,
1444 i_ringBuf3,
1445 i_ringBufSize3,
1446- l_ringProps,
1447- l_ringId,
1448+ i_ringProps,
1449+ i_ringProps[rpIndex].ringId,
1450 l_chipletSel,
1451 l_ringStatusInMvpd,
1452 l_bImgOutOfSpace,
1453@@ -1887,7 +1894,7 @@ fapi2::ReturnCode fetch_and_insert_vpd_rings(
1454
1455 } // Done inserting current ec core instance ring
1456
1457- } //for(ringId) - Done inserting all core instance rings for current ec core
1458+ } //for(rpIndex) - Done inserting all core instance rings for current ec core
1459
1460 } //for (quadrant=0; quadrant<CORES_PER_QME; quadrant++)
1461
1462@@ -1995,7 +2002,7 @@ fapi_try_exit:
1463 fapi2::XIPC_CODE_BUG().
1464 set_CHIP_TARGET(i_procTarget).
1465 set_OCCURRENCE(1),
1466- "Code bug(1): Incorrect EC mask. Should never get here. Fix code!" );
1467+ "CODE BUG(1): Incorrect EC mask. Should never get here. Fix code!" );
1468 break;
1469 }
1470 }
1471@@ -2397,10 +2404,13 @@ ReturnCode p10_ipl_customize (
1472 uint32_t sizeMvpdCIField = 0;
1473 uint8_t* fullCIData = nullptr;
1474
1475+ RingProperties_t* ringProps = nullptr; // Ring properties list
1476+ RingId_t ringId = UNDEFINED_RING_ID;
1477+ RingId_t rpIndex = UNDEFINED_RING_ID; // Ring properties (rp) index
1478+
1479 uint64_t featureVec = 0; // Dynamic inits feature vector from platform attribute
1480 fapi2::ATTR_SYSTEM_IPL_PHASE_Type l_attrSystemIplPhase;
1481 fapi2::ATTR_CONTAINED_IPL_TYPE_Type l_attrContainedIplType;
1482- RingId_t ringId = UNDEFINED_RING_ID;
1483 std::map< Rs4Selector_t, Rs4Selector_t> idxFeatureMap;
1484 std::map<RingId_t, uint64_t> ringIdFeatureVecMap;
1485 uint8_t* ringIdFeatList = NULL;
1486@@ -2468,7 +2478,7 @@ ReturnCode p10_ipl_customize (
1487 set_CHIP_TARGET(i_procTarget).
1488 set_XIP_RC(l_rc).
1489 set_OCCURRENCE(1),
1490- "p9_xip_image_size() failed w/rc=0x%08x at occurrence=1",
1491+ "p9_xip_image_size() failed (1) w/rc=0x%08x",
1492 (uint32_t)l_rc );
1493
1494 FAPI_DBG("Input image size: %d", l_inputImageSize);
1495@@ -3184,6 +3194,17 @@ ReturnCode p10_ipl_customize (
1496 set_CHIP_TARGET(i_procTarget),
1497 "tor_skeleton_generation failed w/rc=0x%08X", (uint32_t)l_rc );
1498
1499+ // We will be needing the ring properties (rp) list for both Dynamic and Mvpd rings
1500+ l_rc = ringid_get_ringProps( CID_P10, &ringProps);
1501+
1502+ FAPI_ASSERT( l_rc == INFRASTRUCT_RC_SUCCESS,
1503+ fapi2::XIPC_RINGID_RINGPROPS_ERROR().
1504+ set_CHIP_TARGET(i_procTarget).
1505+ set_LOCAL_RC(l_rc).
1506+ set_OCCURRENCE(1),
1507+ "ringid_get_ringProps(): Failed w/rc=%i for occurrence=1",
1508+ l_rc );
1509+
1510 // Now, start tracking the instantaneous actual custom ring section size.
1511 // (Note that we already took a copy of the [max] value of io_ringSectionBufSize
1512 // earlier on into l_ringSectionBufSize, so safe to update this now.)
1513@@ -3261,10 +3282,6 @@ ReturnCode p10_ipl_customize (
1514 // ring becomes the de facto Base ring.
1515 //////////////////////////////////////////////////////////////////////////
1516
1517- // TODO / FIXME: The mapping from bit position in the vector to features
1518- // should be encapsulated in an enum constructed at ekb build
1519- // time.
1520-
1521 //
1522 // Get the feature vector from the platform
1523 //
1524@@ -3405,10 +3422,14 @@ ReturnCode p10_ipl_customize (
1525
1526 dynamicRingSection = (void*)((uint8_t*)i_hwImage + iplImgSection.iv_offset);
1527
1528- for(ringId = 0; ringId < NUM_RING_IDS; ringId++)
1529+ for (rpIndex = 0; rpIndex < NUM_RING_IDS; rpIndex++)
1530 {
1531- // Only process non-Mvpd rings (and which are all assumed to be Common rings)
1532- if ( ringid_is_mvpd_ring(torHeaderBase->chipId, ringId) == true )
1533+ // Get the ringId from the RP list
1534+ ringId = ringProps[rpIndex].ringId;
1535+
1536+ // Only process non-Mvpd (which are all Common rings)
1537+ if ( ringid_is_mvpd_ring(torHeaderBase->chipId, ringId) == true ||
1538+ ringId == HOLE_RING_ID )
1539 {
1540 continue;
1541 }
1542@@ -3416,7 +3437,7 @@ ReturnCode p10_ipl_customize (
1543 l_fapiRc = process_target_and_dynamic_rings(
1544 i_procTarget,
1545 true,//true means next arg is Base ringSection ptr
1546- baseRingSection,//Overloaded (false:RS4 ring in mid-Buf1,true:Base ringSection)
1547+ baseRingSection,//Overloaded (false:RS4 ring in mid-Buf1,true:Base section)
1548 dynamicRingSection,
1549 i_ringBuf1,//On return, contains Base ring overlaid with dynamic rings
1550 i_ringBuf2,
1551@@ -3484,15 +3505,15 @@ ReturnCode p10_ipl_customize (
1552 fapi2::XIPC_CODE_BUG().
1553 set_CHIP_TARGET(i_procTarget).
1554 set_OCCURRENCE(2),
1555- "Code bug(2): Messed up RC handling in assoc code. Fix code!" );
1556+ "CODE BUG(2): Messed up RC handling in assoc code. Fix code!" );
1557 break;
1558 }
1559-
1560 }
1561 }
1562
1563
1564
1565+
1566 //////////////////////////////////////////////////////////////////////////
1567 // CUSTOMIZE item: Append VPD rings to io_ringSectionBuf
1568 // System phase: All phases
1569@@ -3594,12 +3615,13 @@ ReturnCode p10_ipl_customize (
1570 i_ringBufSize2,
1571 i_ringBuf3,
1572 i_ringBufSize3,
1573- io_bootCoreMask,
1574 idxFeatureMap,
1575 ringIdFeatureVecMap,
1576 numberOfFeatures,
1577 dynamicRingSection,
1578- attrDdLevel );
1579+ attrDdLevel,
1580+ ringProps,
1581+ io_bootCoreMask );
1582
1583 FAPI_DBG("-----------------------------------------------------------------------");
1584 FAPI_DBG("bootCoreMask: Requested=0x%08X Final=0x%08X",
1585@@ -3611,8 +3633,8 @@ ReturnCode p10_ipl_customize (
1586
1587 if ((uint32_t)l_fapiRc == RC_XIPC_IMAGE_WOULD_OVERFLOW)
1588 {
1589- FAPI_DBG("p10_ipl_customize(): SBE image is full. Ran out of space appending VPD rings"
1590- " to the .rings section");
1591+ FAPI_DBG("p10_ipl_customize(): SBE image is full. Ran out of space appending"
1592+ " VPD rings to the .rings section");
1593
1594 // Check the bootCoreMask to determine if enough cores have been configured.
1595 uint8_t attrMinReqdEcs = 0;
1596@@ -3670,7 +3692,8 @@ ReturnCode p10_ipl_customize (
1597 set_RING_SECTION_BUF_SIZE(l_ringSectionBufSize).
1598 set_MAX_RING_SECTION_SIZE(l_maxRingSectionSize).
1599 set_OCCURRENCE(2),
1600- "Code bug: ringSectionBufSize(=%d) > maxRingSectionSize(=%d) in HB_SBE (Occurrence 2)",
1601+ "CODE BUG: ringSectionBufSize(=%d) > maxRingSectionSize(=%d) in HB_SBE"
1602+ " (Occurrence 2)",
1603 io_ringSectionBufSize, l_maxRingSectionSize );
1604
1605 FAPI_ASSERT( (l_imageSizeWithoutRings + io_ringSectionBufSize) <= l_maxImageSize,
1606@@ -3679,7 +3702,7 @@ ReturnCode p10_ipl_customize (
1607 set_IMAGE_SIZE_WITHOUT_RINGS(l_imageSizeWithoutRings).
1608 set_RING_SECTION_SIZE(io_ringSectionBufSize).
1609 set_MAX_IMAGE_SIZE(l_maxImageSize),
1610- "Code bug: SBE imageSize would exceed maxImageSize" );
1611+ "CODE BUG: SBE imageSize would exceed maxImageSize" );
1612
1613 FAPI_DBG( "SBE image details: io_ringSectionBufSize=%d, l_imageSizeWithoutRings=%d,"
1614 " l_maxImageSize=%d",
1615@@ -3751,12 +3774,13 @@ ReturnCode p10_ipl_customize (
1616 i_ringBufSize2,
1617 i_ringBuf3,
1618 i_ringBufSize3,
1619- io_bootCoreMask,
1620 idxFeatureMap,
1621 ringIdFeatureVecMap,
1622 numberOfFeatures,
1623 dynamicRingSection,
1624- attrDdLevel );
1625+ attrDdLevel,
1626+ ringProps,
1627+ io_bootCoreMask );
1628
1629 FAPI_DBG("Size of QME .rings section after VPD update: %d", io_ringSectionBufSize );
1630
1631@@ -3788,7 +3812,7 @@ ReturnCode p10_ipl_customize (
1632 set_RING_SECTION_BUF_SIZE(l_ringSectionBufSize).
1633 set_MAX_RING_SECTION_SIZE(l_maxRingSectionSize).
1634 set_OCCURRENCE(3),
1635- "Code bug: QME ring section size(=%d) > maxRingSectionSize(=%d)"
1636+ "CODE BUG: QME ring section size(=%d) > maxRingSectionSize(=%d)"
1637 " in RT_QME (Occurrence 3)",
1638 io_ringSectionBufSize, l_maxRingSectionSize );
1639
1640diff --git a/src/import/chips/p10/procedures/hwp/customize/p10_qme_customize.C b/src/import/chips/p10/procedures/hwp/customize/p10_qme_customize.C
1641index fc645d6..c87fabb 100644
1642--- a/src/import/chips/p10/procedures/hwp/customize/p10_qme_customize.C
1643+++ b/src/import/chips/p10/procedures/hwp/customize/p10_qme_customize.C
1644@@ -43,60 +43,52 @@ using namespace fapi2;
1645
1646 fapi2::ReturnCode p10_qme_customize(
1647 const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_procTarget,
1648- uint8_t* i_bufQmeRings,
1649- CUSTOM_RING_OP i_custOp,
1650- uint8_t* io_bufCustRings,
1651- uint32_t& io_bufCustRingsSize,
1652- uint32_t i_dbgl)
1653+ uint8_t* i_qmeRings, //Input QME ring section
1654+ CUST_RING_OP i_custOp,
1655+ uint8_t* io_bufCustRings, //Buffer for customized output QME ring section
1656+ uint32_t& io_bufCustRingsSize, //In: Max buf size, Out: cust ring section size
1657+ uint32_t i_dbgl )
1658 {
1659- int rc = INFRASTRUCT_RC_SUCCESS;
1660+ int rc = TOR_SUCCESS;
1661
1662- TorHeader_t* torHeaderQme = (TorHeader_t*) i_bufQmeRings;
1663+ TorHeader_t* torHeaderQme = (TorHeader_t*) i_qmeRings;
1664 TorHeader_t* torHeaderCust = (TorHeader_t*) io_bufCustRings;
1665
1666- uint8_t ddLevel;
1667- uint8_t torVersion;
1668- uint32_t torMagic;
1669- uint32_t inputQmeRingsSize;
1670+ uint32_t inputQmeRingsSize = be32toh(torHeaderQme->size);
1671+ uint32_t maxCustRingsSize = io_bufCustRingsSize;
1672
1673- ChipId_t chipId = UNDEFINED_CHIP_ID;
1674+ RingProperties_t* ringProps = nullptr;
1675 ChipletData_t* chipletData;
1676+ RingId_t numRingIds = UNDEFINED_RING_ID;
1677+ RingId_t rpIndex;
1678+ uint8_t chipletId;
1679+ void* nextRing = NULL;
1680+ uint32_t remBufSize;
1681
1682 FAPI_IMP(">> p10_qme_customize ");
1683
1684- ddLevel = torHeaderQme->ddLevel;
1685- torVersion = torHeaderQme->version;
1686- torMagic = be32toh(torHeaderQme->magic);
1687- chipId = torHeaderQme->chipId;
1688- inputQmeRingsSize = be32toh(torHeaderQme->size);
1689-
1690- RingId_t numRings = UNDEFINED_RING_ID; // Number of chiplet common or instance rings
1691- MyBool_t bInstCase = UNDEFINED_BOOLEAN; // 0:COMMON, 1:INSTANCE rings
1692- RingId_t ringId;
1693- uint8_t chipletInstId;
1694-
1695- uint32_t maxCustRingsSize = io_bufCustRingsSize;
1696-
1697- uint8_t iRing;
1698- void* nextRing = NULL;
1699- uint32_t remBufSize;
1700+ // Take note of some key TOR header input data
1701+ uint32_t torMagic = be32toh(torHeaderQme->magic);
1702+ uint8_t torVersion = torHeaderQme->version;
1703+ uint8_t ddLevel = torHeaderQme->ddLevel;
1704+ ChipId_t chipId = torHeaderQme->chipId;
1705
1706 //
1707 // Step 0: Test input parameters
1708 //
1709- FAPI_ASSERT(i_custOp < NUM_CUSTOMIZE_QME_ENTRIES
1710- && i_bufQmeRings != NULL
1711+ FAPI_ASSERT(i_custOp < NUM_QME_CUST_OPS
1712+ && i_qmeRings != NULL
1713 && io_bufCustRings != NULL,
1714 fapi2::QMEC_FUNC_CALL_ARGUMENT_ERROR()
1715 .set_TARGET(i_procTarget)
1716- .set_CUSTOM_RING_OP(i_custOp)
1717- .set_INPUT_QME_RINGS_BUF_PTR(i_bufQmeRings)
1718+ .set_CUST_RING_OP(i_custOp)
1719+ .set_INPUT_QME_RINGS_PTR(i_qmeRings)
1720 .set_CUST_QME_RINGS_BUF_PTR(io_bufCustRings),
1721- "Error: Some arguments in function call are invalid,\n"
1722- " i_custOp=0x%08x, i_bufQmeRings=0x%016llx, io_bufCustRings=0x%016llx.\n",
1723+ "ERROR: Some arguments in function call are invalid:"
1724+ " i_custOp=0x%x, i_qmeRings=0x%016llx, io_bufCustRings=0x%016llx.\n",
1725 i_custOp,
1726- (uintptr_t) i_bufQmeRings,
1727- (uintptr_t) io_bufCustRings);
1728+ (uintptr_t)i_qmeRings,
1729+ (uintptr_t)io_bufCustRings);
1730
1731 FAPI_ASSERT(torMagic == TOR_MAGIC_QME && torVersion == TOR_VERSION,
1732 fapi2::QMEC_TOR_HEADER_MISMATCH()
1733@@ -105,28 +97,26 @@ fapi2::ReturnCode p10_qme_customize(
1734 .set_TOR_MAGIC_QME_DEFINED(TOR_MAGIC_QME)
1735 .set_TOR_VERSION_IN_HEADER(torVersion)
1736 .set_TOR_VERSION_DEFINED(TOR_VERSION),
1737- "Error: TOR Magic or TOR Version not match in TOR header and the defined,\n"
1738- " TOR Magic w/value =0x%08x in TOR header, TOR_MAGIC_QME w/value =0x%08x,\n"
1739- " TOR Version w/value =0x%08x in TOR header, TOR_VERSION w/value =0x%08x.\n",
1740+ "ERROR: TOR Magic or TOR Version in TOR header do not match the defined values:\n"
1741+ " torMagic=0x%08x but TOR_MAGIC_QME=0x%08x\n"
1742+ " torVersion=%u but TOR_VERSION=%u",
1743 torMagic,
1744 TOR_MAGIC_QME,
1745 torVersion,
1746 TOR_VERSION);
1747
1748- // Make sure that the customized buffer size is greater than or
1749- // equal to the size in TOR header in the input QME ring buffer.
1750+ // Check that the max customized buffer size is >= the size of the input TOR ring section
1751 FAPI_ASSERT(maxCustRingsSize >= inputQmeRingsSize,
1752 fapi2::QMEC_RINGS_OUTPUT_BUFFER_TOO_SMALL()
1753 .set_TARGET(i_procTarget)
1754- .set_MAX_CUST_RINGS_BUF_SIZE(maxCustRingsSize)
1755- .set_INPUT_QME_RINGS_BUF_SIZE(inputQmeRingsSize),
1756- "Error: Input QME rings buffer size exceeds max customize ring buffer size,\n"
1757- " maxCustRingsSize=0x%08x, inputQmeRingsSize=0x%08x.\n",
1758+ .set_CUST_QME_RINGS_BUF_SIZE(maxCustRingsSize)
1759+ .set_INPUT_QME_RINGS_SIZE(inputQmeRingsSize)
1760+ .set_CUST_QME_RINGS_SIZE(0xffffffff), //Still undefined
1761+ "ERROR: Max custom QME ring buf size < Input QME rings size:"
1762+ " maxCustRingsSize=0x%08x, inputQmeRingsSize=0x%08x",
1763 maxCustRingsSize,
1764 inputQmeRingsSize);
1765
1766- bInstCase = (i_custOp == CUSTOMIZE_QME_COMMON_RING) ? false : true;
1767-
1768 //
1769 // Step 1: Create TOR skeleton ringSection
1770 // Create the complete ring skeleton, but with empty TOR ring slots (ie, no ring content).
1771@@ -139,12 +129,7 @@ fapi2::ReturnCode p10_qme_customize(
1772 chipId,
1773 i_dbgl);
1774
1775- FAPI_DBG("tor_skeleton_generation() completed w/rc=0x%08x,\n"
1776- " torMagic=0x%08x, torVersion=%u,\n"
1777- " ddLevel=0x%02x and chipId=0x%02x.\n",
1778- rc, torMagic, torVersion, ddLevel, chipId);
1779-
1780- FAPI_ASSERT(rc == INFRASTRUCT_RC_SUCCESS,
1781+ FAPI_ASSERT(rc == TOR_SUCCESS,
1782 fapi2::QMEC_TOR_SKELETON_GEN_ERROR()
1783 .set_TARGET(i_procTarget)
1784 .set_API_RC(rc)
1785@@ -152,130 +137,156 @@ fapi2::ReturnCode p10_qme_customize(
1786 .set_TOR_VER(torVersion)
1787 .set_DD_LEVEL(ddLevel)
1788 .set_CHIP_ID(chipId),
1789- "Error: tor_skeleton_generation() failed w/rc=0x%08x,"
1790- " torMagic=0x%08x, torVersion=%u, ddLevel=0x%02x and chipId=0x%02x\n",
1791+ "ERROR: tor_skeleton_generation() failed w/rc=0x%08x for"
1792+ " torMagic=0x%08x, torVersion=%u, ddLevel=0x%02x and chipId=0x%02x",
1793 rc, torMagic, torVersion, ddLevel, chipId);
1794
1795- //
1796- // Step 2: Add ring content
1797- // Append rings to the end of the [skeleton] TOR ring section and update TOR offset slot
1798- //
1799+ // Get the main ring properties list and the number of RingIDs
1800+ // (Note that we can skip the second rc check since the API only fails if wrong chipId which
1801+ // will be caught by the first rc check)
1802+ rc = ringid_get_ringProps(chipId,
1803+ &ringProps);
1804
1805- // Get all the meta data for this chiplet and its rings
1806+ FAPI_ASSERT(rc == TOR_SUCCESS,
1807+ fapi2::QMEC_RINGID_API_ERROR()
1808+ .set_TARGET(i_procTarget)
1809+ .set_API_RC(rc)
1810+ .set_TOR_MAGIC(torMagic)
1811+ .set_TOR_VER(torVersion)
1812+ .set_RP_INDEX(UNDEFINED_RING_ID)
1813+ .set_RING_ID(UNDEFINED_RING_ID)
1814+ .set_CHIP_ID(chipId)
1815+ .set_OCCURRENCE(1),
1816+ "ERROR: ringid_get_ringProps() failed w/rc=0x%08x\n for",
1817+ " torMagic=0x%08x, torVersion=%u and chipId=0x%02x",
1818+ rc, torMagic, torVersion, chipId);
1819+
1820+ ringid_get_num_ring_ids( chipId,
1821+ &numRingIds );
1822+
1823+ // Get the meta data for the QME chiplet
1824 rc = ringid_get_chipletProps(chipId,
1825 torMagic,
1826 torVersion,
1827 EQ_TYPE,
1828 &chipletData);
1829
1830- FAPI_ASSERT(rc == INFRASTRUCT_RC_SUCCESS,
1831- fapi2::QMEC_RINGID_GET_CHIPLETPROPS_ERROR()
1832+ FAPI_ASSERT(rc == TOR_SUCCESS,
1833+ fapi2::QMEC_RINGID_API_ERROR()
1834 .set_TARGET(i_procTarget)
1835 .set_API_RC(rc)
1836 .set_TOR_MAGIC(torMagic)
1837- .set_TOR_VER(torVersion),
1838- "Error: ringid_get_chipletProps() failed w/rc=0x%08x,\n"
1839- " torMagic=0x%08x and torVersion=%u.\n",
1840- rc, torMagic, torVersion);
1841+ .set_TOR_VER(torVersion)
1842+ .set_RP_INDEX(UNDEFINED_RING_ID)
1843+ .set_RING_ID(UNDEFINED_RING_ID)
1844+ .set_CHIP_ID(chipId)
1845+ .set_OCCURRENCE(2),
1846+ "ERROR: ringid_get_chipletProps() failed w/rc=0x%08x for chipletType=EQ_TYPE,"
1847+ " torMagic=0x%08x, torVersion=%u and chipId=0x%02x",
1848+ rc, torMagic, torVersion, chipId);
1849
1850- chipletInstId = chipletData->chipletBaseId + i_custOp;
1851+ chipletId = chipletData->chipletBaseId + i_custOp;
1852
1853- numRings = bInstCase ?
1854- chipletData->numInstanceRings :
1855- chipletData->numCommonRings;
1856+ //
1857+ // Step 2: Copy and append rings
1858+ //
1859
1860- // Loop through all rings, get ring data for each ring and
1861- // append it to cust ring section.
1862- for (iRing = 0; iRing < numRings; iRing++)
1863+ for (rpIndex = 0; rpIndex < numRingIds; rpIndex++)
1864 {
1865- // Extract ringId from the TOR ring index, iRing.
1866- rc = ringidGetRingId2(chipId,
1867- torMagic,
1868- EQ_TYPE,
1869- iRing,
1870- bInstCase,
1871- ringId,
1872- false);
1873-
1874- FAPI_ASSERT(rc == INFRASTRUCT_RC_SUCCESS,
1875- fapi2::QMEC_RINGID_GET_RINGID2_ERROR()
1876- .set_TARGET(i_procTarget)
1877- .set_API_RC(rc)
1878- .set_TOR_MAGIC(torMagic)
1879- .set_RING_INST_ID(iRing)
1880- .set_INST_CASE(bInstCase)
1881- .set_RING_ID(ringId),
1882- "Error: ringidGetRingId2() failed w/rc=0x%08x,\n"
1883- " torMagic=0x%08x, iRing=%u,\n"
1884- " bInstCase=%u and ringId=0x%x.\n",
1885- rc, torMagic, iRing, bInstCase, ringId);
1886-
1887 io_bufCustRingsSize = be32toh(torHeaderCust->size);
1888 nextRing = (void*) (io_bufCustRings + io_bufCustRingsSize);
1889
1890 // nextRing is portion of io_bufCustRings buffer which is used as
1891- // temporary buffer to pass the ring in i_bufQmeRings from the
1892+ // temporary buffer to pass the ring in i_qmeRings from the
1893 // tor_get_single_ring() function.
1894 // The size of this temporary buffer is captured by remBufSize.
1895- FAPI_ASSERT(maxCustRingsSize > io_bufCustRingsSize,
1896+ FAPI_ASSERT(maxCustRingsSize >= io_bufCustRingsSize,
1897 fapi2::QMEC_RINGS_OUTPUT_BUFFER_TOO_SMALL()
1898- .set_MAX_CUST_RINGS_BUF_SIZE(maxCustRingsSize)
1899- .set_CUST_QME_RINGS_BUF_SIZE(io_bufCustRingsSize),
1900- "Error: QME rings output buffer is not large enough to use part of it for rs4Ring,\n"
1901- " maxCustRingsSize=0x%08x, io_bufCustRingsSize=0x%08x.\n",
1902+ .set_TARGET(i_procTarget)
1903+ .set_CUST_QME_RINGS_BUF_SIZE(maxCustRingsSize)
1904+ .set_INPUT_QME_RINGS_SIZE(inputQmeRingsSize)
1905+ .set_CUST_QME_RINGS_SIZE(io_bufCustRingsSize),
1906+ "ERROR: QME customize rings output buffer is too small since"
1907+ " maxCustRingsSize=0x%08x < io_bufCustRingsSize=0x%08x.",
1908 maxCustRingsSize, io_bufCustRingsSize);
1909
1910 remBufSize = maxCustRingsSize - io_bufCustRingsSize;
1911
1912- // Extract ring data using the ringId.
1913- rc = tor_get_single_ring(i_bufQmeRings,
1914- ddLevel,
1915- ringId,
1916- chipletInstId, //This argument ignored for Common rings.
1917- nextRing,
1918- remBufSize,
1919- i_dbgl);
1920+ //
1921+ // Extract ring
1922+ // But skip it if it doesn't qualify for current custOp context
1923+ //
1924
1925- FAPI_ASSERT(rc == INFRASTRUCT_RC_SUCCESS ||
1926- rc == TOR_RING_IS_EMPTY,
1927- fapi2::QMEC_TOR_GET_SINGLE_RING_ERROR()
1928- .set_TARGET(i_procTarget)
1929- .set_API_RC(rc)
1930- .set_DD_LEVEL(ddLevel)
1931- .set_RING_ID(ringId)
1932- .set_CHIPLET_INST_ID(chipletInstId)
1933- .set_NEXT_RS4RING_BUF_SIZE(remBufSize),
1934- "Error: tor_get_single_ring() failed w/rc=0x%08x, ddLevel=0x%02x,"
1935- " ringId=0x%x, chipletInstId=0x%02x, remBufSize=%u.\n",
1936- rc, ddLevel, ringId, chipletInstId, remBufSize);
1937-
1938- // If ring is empty, skip and check next ring.
1939- if(rc == TOR_RING_IS_EMPTY)
1940+ RingId_t ringId = ringProps[rpIndex].ringId;
1941+ MyBool_t bInstRing = ringid_is_instance_ring(rpIndex);
1942+
1943+ if ( ( bInstRing == true &&
1944+ (i_custOp >= CUST_QME0_INSTANCE_RING && i_custOp <= CUST_QME7_INSTANCE_RING) ) ||
1945+ ( bInstRing == false &&
1946+ (i_custOp == CUST_QME_COMMON_RING) ) )
1947+ {
1948+ rc = tor_get_single_ring(i_qmeRings,
1949+ ddLevel,
1950+ ringId,
1951+ chipletId, //Arg ignored for Common rings
1952+ nextRing,
1953+ remBufSize,
1954+ i_dbgl);
1955+
1956+
1957+ FAPI_ASSERT(rc == TOR_SUCCESS ||
1958+ rc == TOR_RING_IS_EMPTY ||
1959+ rc == TOR_INVALID_CHIPLET_TYPE ||
1960+ rc == TOR_HOLE_RING_ID,
1961+ fapi2::QMEC_TOR_GET_SINGLE_RING_ERROR()
1962+ .set_TARGET(i_procTarget)
1963+ .set_API_RC(rc)
1964+ .set_DD_LEVEL(ddLevel)
1965+ .set_RING_ID(ringId)
1966+ .set_CHIPLET_ID(chipletId)
1967+ .set_REM_BUF_SIZE(remBufSize),
1968+ "ERROR: tor_get_single_ring() failed w/rc=0x%08x, ddLevel=0x%02x,"
1969+ " ringId=0x%x, chipletId=0x%02x, remBufSize=0x%08x\n",
1970+ rc, ddLevel, ringId, chipletId, remBufSize);
1971+
1972+ // If ring is empty, is a hole ring or doesnt belong to QME chiplet => go to next ring
1973+ if( rc == TOR_RING_IS_EMPTY ||
1974+ rc == TOR_INVALID_CHIPLET_TYPE ||
1975+ rc == TOR_HOLE_RING_ID )
1976+ {
1977+ //FAPI_DBG("Skipping ringId=0x%03x for rc=0x%08x", ringId, rc);
1978+ rc = TOR_SUCCESS;
1979+ continue;
1980+ }
1981+ }
1982+ else
1983 {
1984- rc = INFRASTRUCT_RC_SUCCESS;
1985 continue;
1986 }
1987
1988- // Append ring to ring section.
1989+ //
1990+ // Append ring to customized QME ring section.
1991 // Note that this API also updates the header's ring size
1992+ //
1993 rc = tor_append_ring(io_bufCustRings,
1994 maxCustRingsSize,
1995 ringId,
1996- chipletInstId,
1997+ chipletId, //Arg ignored for Common rings
1998 (void*)nextRing,
1999 i_dbgl);
2000
2001- io_bufCustRingsSize = be32toh(torHeaderCust->size);
2002-
2003- FAPI_ASSERT(rc == INFRASTRUCT_RC_SUCCESS,
2004+ FAPI_ASSERT(rc == TOR_SUCCESS,
2005 fapi2::QMEC_TOR_APPEND_RING_ERROR()
2006 .set_TARGET(i_procTarget)
2007 .set_API_RC(rc)
2008- .set_CUST_RINGS_BUF_SIZE(io_bufCustRingsSize)
2009- .set_RING_ID(ringId),
2010- "Error: tor_append_ring() failed w/rc=0x%08x,\n"
2011- " io_bufCustRingsSize=0x%08x, ringId=0x%x.\n",
2012- rc, io_bufCustRingsSize, ringId);
2013+ .set_RING_ID(ringId)
2014+ .set_CHIPLET_ID(chipletId)
2015+ .set_CUST_QME_RINGS_BUF_SIZE(maxCustRingsSize),
2016+ "ERROR: tor_append_ring() failed w/rc=0x%08x for ringId=0x%x,"
2017+ " chipletId=0x%02x and maxCustRingsSize=0x%08x",
2018+ rc, ringId, chipletId, maxCustRingsSize);
2019+
2020+ io_bufCustRingsSize = be32toh(torHeaderCust->size);
2021
2022 }
2023
2024diff --git a/src/import/chips/p10/procedures/hwp/customize/p10_qme_customize.H b/src/import/chips/p10/procedures/hwp/customize/p10_qme_customize.H
2025index b98c891..3d2b527 100644
2026--- a/src/import/chips/p10/procedures/hwp/customize/p10_qme_customize.H
2027+++ b/src/import/chips/p10/procedures/hwp/customize/p10_qme_customize.H
2028@@ -5,7 +5,7 @@
2029 /* */
2030 /* OpenPOWER HostBoot Project */
2031 /* */
2032-/* Contributors Listed Below - COPYRIGHT 2016,2019 */
2033+/* Contributors Listed Below - COPYRIGHT 2016,2020 */
2034 /* [+] International Business Machines Corp. */
2035 /* */
2036 /* */
2037@@ -40,55 +40,50 @@
2038 /**
2039 * @brief various ring customization operation supported by HWP
2040 */
2041-enum CUSTOM_RING_OP
2042+enum CUST_RING_OP
2043 {
2044- CUSTOMIZE_QME0_SPECIFIC_RING = 0x00,
2045- CUSTOMIZE_QME1_SPECIFIC_RING = 0x01,
2046- CUSTOMIZE_QME2_SPECIFIC_RING = 0x02,
2047- CUSTOMIZE_QME3_SPECIFIC_RING = 0x03,
2048- CUSTOMIZE_QME4_SPECIFIC_RING = 0x04,
2049- CUSTOMIZE_QME5_SPECIFIC_RING = 0x05,
2050- CUSTOMIZE_QME6_SPECIFIC_RING = 0x06,
2051- CUSTOMIZE_QME7_SPECIFIC_RING = 0x07,
2052- CUSTOMIZE_QME_COMMON_RING = 0x08,
2053- NUM_CUSTOMIZE_QME_ENTRIES
2054+ CUST_QME0_INSTANCE_RING = 0x00,
2055+ CUST_QME1_INSTANCE_RING = 0x01,
2056+ CUST_QME2_INSTANCE_RING = 0x02,
2057+ CUST_QME3_INSTANCE_RING = 0x03,
2058+ CUST_QME4_INSTANCE_RING = 0x04,
2059+ CUST_QME5_INSTANCE_RING = 0x05,
2060+ CUST_QME6_INSTANCE_RING = 0x06,
2061+ CUST_QME7_INSTANCE_RING = 0x07,
2062+ CUST_QME_COMMON_RING = 0x08,
2063+ NUM_QME_CUST_OPS
2064 };
2065
2066 typedef fapi2::ReturnCode (*p10_qme_customize_FP_t)(
2067 const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_procTarget,
2068- uint8_t* i_bufQmeRings,
2069- CUSTOM_RING_OP i_custOp,
2070- uint8_t* io_bufCustRings,
2071- uint32_t& io_bufCustRingsSize,
2072- uint32_t i_dbgl);
2073+ uint8_t* i_qmeRings,
2074+ CUST_RING_OP i_custOp,
2075+ uint8_t* io_bufCustRings,
2076+ uint32_t& io_bufCustRingsSize,
2077+ uint32_t i_dbgl);
2078
2079 extern "C"
2080 {
2081
2082 /// @brief customizes QME ring section based on input.
2083 /// @param[in] i_procTarget reference to processor chip target.
2084-/// @param[in/out] i_bufQmeRings pointer to a buffer containing all
2085-/// scan rings associated with QME image.
2086-/// @param[in] i_custOp type of customization requested.
2087-/// @param[in/out] io_bufCustRings pointer to a buffer containing
2088-/// customized QME rings.
2089-/// @param[in/out] io_bufCustRingsSize reference.
2090-/// Input - max buffer size, must be greater than or
2091-/// equal to the size in the TOR header of QME
2092-/// ring section in the i_bufQmeRing buffer.
2093-/// output- the actual buffer size of customized QME
2094-/// rings.
2095-/// @param[in] i_dbgl debug level, default value is 0.
2096-/// @return FAPI_RC_SUCCESS if the customization was successful,
2097-/// error code otherwise.
2098+/// @param[in/out] i_qmeRings Pointer to the input QME ring section
2099+/// @param[in] i_custOp Type of customization requested.
2100+/// @param[in/out] io_bufCustRings Pointer to a buffer containing the customized QME rings.
2101+/// @param[in/out] io_bufCustRingsSize Size of customized QME ring section
2102+/// Input - max buffer size, must be >= to the size in the TOR header of
2103+/// the input QME ring section in i_qmeRings
2104+/// Output- the actual size of the customized QME ring section
2105+/// @param[in] i_dbgl Debug level, default value is 0
2106+/// @return FAPI_RC_SUCCESS if the customization was successful, otherwise error code
2107
2108 fapi2::ReturnCode p10_qme_customize(
2109 const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_procTarget,
2110- uint8_t* i_bufQmeRings,
2111- CUSTOM_RING_OP i_custOp,
2112- uint8_t* io_bufCustRings,
2113- uint32_t& io_bufCustRingsSize,
2114- uint32_t i_dbgl = 0);
2115+ uint8_t* i_bufQmeRings,
2116+ CUST_RING_OP i_custOp,
2117+ uint8_t* io_bufCustRings,
2118+ uint32_t& io_bufCustRingsSize,
2119+ uint32_t i_dbgl = 0);
2120
2121 } //extern "C"
2122
2123diff --git a/src/import/chips/p10/procedures/hwp/pm/p10_hcode_image_build.C b/src/import/chips/p10/procedures/hwp/pm/p10_hcode_image_build.C
2124index 0d3441a..d2553cb 100644
2125--- a/src/import/chips/p10/procedures/hwp/pm/p10_hcode_image_build.C
2126+++ b/src/import/chips/p10/procedures/hwp/pm/p10_hcode_image_build.C
2127@@ -1037,7 +1037,7 @@ fapi2::ReturnCode buildQmeSpecificRing( CONST_FAPI2_PROC& i_procTgt, Homerlayout
2128
2129 FAPI_TRY( p10_qme_customize( i_procTgt,
2130 (uint8_t *)i_ringData.iv_pRingBuffer,
2131- ( CUSTOM_RING_OP )l_superChiplet,
2132+ ( CUST_RING_OP )l_superChiplet,
2133 (uint8_t *)i_ringData.iv_pWorkBuf1,
2134 l_workBufSize,
2135 0 ),
2136@@ -1071,7 +1071,7 @@ fapi2::ReturnCode buildQmeSpecificRing( CONST_FAPI2_PROC& i_procTgt, Homerlayout
2137
2138 FAPI_TRY( p10_qme_customize( i_procTgt,
2139 (uint8_t *)i_ringData.iv_pRingBuffer,
2140- ( CUSTOM_RING_OP ) l_superChiplet,
2141+ ( CUST_RING_OP ) l_superChiplet,
2142 (uint8_t *)i_ringData.iv_pWorkBuf1,
2143 l_workBufSize,
2144 0 ),
2145@@ -1236,7 +1236,7 @@ fapi2::ReturnCode buildQmeRing( CONST_FAPI2_PROC& i_procTgt, void * const i_pIma
2146
2147 FAPI_TRY( p10_qme_customize( i_procTgt,
2148 (uint8_t *)i_ringData.iv_pRingBuffer,
2149- CUSTOMIZE_QME_COMMON_RING,
2150+ CUST_QME_COMMON_RING,
2151 (uint8_t *)i_ringData.iv_pWorkBuf1,
2152 l_workBufSize,
2153 0 ),
2154diff --git a/src/import/chips/p10/procedures/xml/error_info/p10_qme_customize_errors.xml b/src/import/chips/p10/procedures/xml/error_info/p10_qme_customize_errors.xml
2155index 39e6611..4057a69 100644
2156--- a/src/import/chips/p10/procedures/xml/error_info/p10_qme_customize_errors.xml
2157+++ b/src/import/chips/p10/procedures/xml/error_info/p10_qme_customize_errors.xml
2158@@ -5,7 +5,7 @@
2159 <!-- -->
2160 <!-- OpenPOWER HostBoot Project -->
2161 <!-- -->
2162-<!-- Contributors Listed Below - COPYRIGHT 2016,2019 -->
2163+<!-- Contributors Listed Below - COPYRIGHT 2016,2020 -->
2164 <!-- [+] International Business Machines Corp. -->
2165 <!-- -->
2166 <!-- -->
2167@@ -26,10 +26,10 @@
2168 <!-- ********************************************************************* -->
2169 <hwpError>
2170 <rc>RC_QMEC_FUNC_CALL_ARGUMENT_ERROR</rc>
2171- <description>Caller bug: Some function call arguments are invalid.</description>
2172+ <description>Some function call arguments are invalid.</description>
2173 <ffdc>TARGET</ffdc>
2174- <ffdc>CUSTOM_RING_OP</ffdc>
2175- <ffdc>INPUT_QME_RINGS_BUF_PTR</ffdc>
2176+ <ffdc>CUST_RING_OP</ffdc>
2177+ <ffdc>INPUT_QME_RINGS_PTR</ffdc>
2178 <ffdc>CUST_QME_RINGS_BUF_PTR</ffdc>
2179 <callout>
2180 <procedure>CODE</procedure>
2181@@ -39,7 +39,7 @@
2182 <!-- ********************************************************************* -->
2183 <hwpError>
2184 <rc>RC_QMEC_TOR_HEADER_MISMATCH</rc>
2185- <description>Caller bug: Data in TOR header does not match.</description>
2186+ <description>Some data in TOR header does not match.</description>
2187 <ffdc>TARGET</ffdc>
2188 <ffdc>TOR_MAGIC_QME_IN_HEADER</ffdc>
2189 <ffdc>TOR_MAGIC_QME_DEFINED</ffdc>
2190@@ -53,11 +53,11 @@
2191 <!-- ********************************************************************* -->
2192 <hwpError>
2193 <rc>RC_QMEC_RINGS_OUTPUT_BUFFER_TOO_SMALL</rc>
2194- <description>Code bug: Input QME rings buffer is not too small.</description>
2195+ <description>Customized QME ring section buffer is too small.</description>
2196 <ffdc>TARGET</ffdc>
2197- <ffdc>MAX_CUST_RINGS_BUF_SIZE</ffdc>
2198- <ffdc>INPUT_QME_RINGS_BUF_SIZE</ffdc>
2199 <ffdc>CUST_QME_RINGS_BUF_SIZE</ffdc>
2200+ <ffdc>INPUT_QME_RINGS_SIZE</ffdc>
2201+ <ffdc>CUST_QME_RINGS_SIZE</ffdc>
2202 <callout>
2203 <procedure>CODE</procedure>
2204 <priority>HIGH</priority>
2205@@ -66,7 +66,7 @@
2206 <!-- ********************************************************************* -->
2207 <hwpError>
2208 <rc>RC_QMEC_TOR_SKELETON_GEN_ERROR</rc>
2209- <description>Code bug: Error with calling tor_skeleton_generation().</description>
2210+ <description>Error with calling tor_skeleton_generation().</description>
2211 <ffdc>TARGET</ffdc>
2212 <ffdc>API_RC</ffdc>
2213 <ffdc>TOR_MAGIC</ffdc>
2214@@ -80,12 +80,16 @@
2215 </hwpError>
2216 <!-- ********************************************************************* -->
2217 <hwpError>
2218- <rc>RC_QMEC_RINGID_GET_CHIPLETPROPS_ERROR</rc>
2219- <description>Code bug: Error with calling ringid_get_chipletProps().</description>
2220+ <rc>RC_QMEC_RINGID_API_ERROR</rc>
2221+ <description>Error with calling ringid_xyz().</description>
2222 <ffdc>TARGET</ffdc>
2223 <ffdc>API_RC</ffdc>
2224 <ffdc>TOR_MAGIC</ffdc>
2225 <ffdc>TOR_VER</ffdc>
2226+ <ffdc>RP_INDEX</ffdc>
2227+ <ffdc>RING_ID</ffdc>
2228+ <ffdc>CHIP_ID</ffdc>
2229+ <ffdc>OCCURRENCE</ffdc>
2230 <callout>
2231 <procedure>CODE</procedure>
2232 <priority>HIGH</priority>
2233@@ -93,14 +97,14 @@
2234 </hwpError>
2235 <!-- ********************************************************************* -->
2236 <hwpError>
2237- <rc>RC_QMEC_RINGID_GET_RINGID2_ERROR</rc>
2238- <description>Code bug: Error with calling ringidGetRingId2().</description>
2239+ <rc>RC_QMEC_TOR_GET_SINGLE_RING_ERROR</rc>
2240+ <description>Code bug: Error with calling tor_get_single_ring().</description>
2241 <ffdc>TARGET</ffdc>
2242 <ffdc>API_RC</ffdc>
2243- <ffdc>TOR_MAGIC</ffdc>
2244- <ffdc>RING_INST_ID</ffdc>
2245- <ffdc>INST_CASE</ffdc>
2246+ <ffdc>DD_LEVEL</ffdc>
2247 <ffdc>RING_ID</ffdc>
2248+ <ffdc>CHIPLET_ID</ffdc>
2249+ <ffdc>REM_BUF_SIZE</ffdc>
2250 <callout>
2251 <procedure>CODE</procedure>
2252 <priority>HIGH</priority>
2253@@ -108,14 +112,13 @@
2254 </hwpError>
2255 <!-- ********************************************************************* -->
2256 <hwpError>
2257- <rc>RC_QMEC_TOR_GET_SINGLE_RING_ERROR</rc>
2258- <description>Code bug: Error with calling tor_get_single_ring().</description>
2259+ <rc>RC_QMEC_TOR_APPEND_RING_ERROR</rc>
2260+ <description>Code bug: Error with calling tor_append_ring().</description>
2261 <ffdc>TARGET</ffdc>
2262 <ffdc>API_RC</ffdc>
2263- <ffdc>DD_LEVEL</ffdc>
2264 <ffdc>RING_ID</ffdc>
2265- <ffdc>CHIPLET_INST_ID</ffdc>
2266- <ffdc>NEXT_RS4RING_BUF_SIZE</ffdc>
2267+ <ffdc>CHIPLET_ID</ffdc>
2268+ <ffdc>CUST_QME_RINGS_BUF_SIZE</ffdc>
2269 <callout>
2270 <procedure>CODE</procedure>
2271 <priority>HIGH</priority>
2272@@ -123,12 +126,11 @@
2273 </hwpError>
2274 <!-- ********************************************************************* -->
2275 <hwpError>
2276- <rc>RC_QMEC_TOR_APPEND_RING_ERROR</rc>
2277- <description>Code bug: Error with calling tor_append_ring().</description>
2278+ <rc>RC_QMEC_CODE_BUG</rc>
2279+ <description>Code bug: Fix code!</description>
2280 <ffdc>TARGET</ffdc>
2281 <ffdc>API_RC</ffdc>
2282- <ffdc>CUST_RINGS_BUF_SIZE</ffdc>
2283- <ffdc>RING_ID</ffdc>
2284+ <ffdc>OCCURRENCE</ffdc>
2285 <callout>
2286 <procedure>CODE</procedure>
2287 <priority>HIGH</priority>
2288diff --git a/src/import/chips/p10/utils/imageProcs/p10_ringId.H b/src/import/chips/p10/utils/imageProcs/p10_ringId.H
2289index b11f806..c020959 100644
2290--- a/src/import/chips/p10/utils/imageProcs/p10_ringId.H
2291+++ b/src/import/chips/p10/utils/imageProcs/p10_ringId.H
2292@@ -54,7 +54,7 @@
2293 // circumstances exist - coordinate with infrastructure team).
2294 // - To allow the MVPD group to expand without affecting the ringId sequence of
2295 // the EKB rings, the beginning of the EKB ring group is pushed out to
2296-// RINGID_START_EKB. **This feature is currently inactive!**
2297+// RINGID_START_EKB.
2298 //
2299 // p10_ring_properties.H
2300 // =====================
2301@@ -118,15 +118,55 @@ enum Chiplets
2302
2303 const ChipletType_t QME_NUM_CHIPLETS = 1;
2304
2305-
2306 #include "p10_ring_properties.H"
2307
2308-static inline const char* ringid_get_ring_name(RingID i_id)
2309+
2310+//
2311+// ringid_convert_ringId_to_ringIndex()
2312+//
2313+// This function converts the enum ringId to the contiguous ringIndex that
2314+// we need for looking up ring metadata in the RING_PROPERTIES list. Since
2315+// we have a gap between the MVPD and EKB group of rings in the main enum
2316+// ringId list, and since we cannot have a huge gap of empty entries in
2317+// the RING_PROPERTIES list as that would be a waste of Seeprom space, we
2318+// convert here the ringId into the ring properties (rp) index, rpIndex.
2319+//
2320+static inline const RingId_t ringid_convert_ringId_to_rpIndex( RingId_t i_ringId )
2321+{
2322+ if ( i_ringId >= RINGID_START_MVPD && i_ringId <= RINGID_END_MVPD )
2323+ {
2324+ return i_ringId - RINGID_START_MVPD + RING_INDEX_START_MVPD;
2325+ }
2326+ else if ( i_ringId >= RINGID_START_EKB && i_ringId <= RINGID_END_EKB )
2327+ {
2328+ return i_ringId - RINGID_START_EKB + RING_INDEX_START_EKB;
2329+ }
2330+ else
2331+ {
2332+ return UNDEFINED_RING_ID;
2333+ }
2334+}
2335+
2336+
2337+static inline const char* ringid_get_ring_name(RingId_t i_ringId)
2338 {
2339 #ifdef __PPE__
2340 return "";
2341 #else
2342- return (i_id < NUM_RING_IDS) ? RING_PROPERTIES[i_id].ringName : "INVALID RING ID";
2343+
2344+ if ( i_ringId >= RINGID_START_MVPD && i_ringId <= RINGID_END_MVPD )
2345+ {
2346+ return RING_PROPERTIES[i_ringId - RINGID_START_MVPD + RING_INDEX_START_MVPD].ringName;
2347+ }
2348+ else if ( i_ringId >= RINGID_START_EKB && i_ringId <= RINGID_END_EKB )
2349+ {
2350+ return RING_PROPERTIES[i_ringId - RINGID_START_EKB + RING_INDEX_START_EKB].ringName;
2351+ }
2352+ else
2353+ {
2354+ return "INVALID RING ID";
2355+ }
2356+
2357 #endif
2358 }
2359
2360diff --git a/src/import/chips/p10/utils/imageProcs/p10_ring_id.H b/src/import/chips/p10/utils/imageProcs/p10_ring_id.H
2361index 7577454..efe5d51 100644
2362--- a/src/import/chips/p10/utils/imageProcs/p10_ring_id.H
2363+++ b/src/import/chips/p10/utils/imageProcs/p10_ring_id.H
2364@@ -198,103 +198,103 @@ enum RingID
2365 NUM_RING_IDS_MVPD = 161,
2366
2367 // EKB Rings:
2368- perv_fure = 161, //0xA1
2369- sbe_fure = 162, //0xA2
2370- occ_fure = 163, //0xA3
2371- perv_dpll_func = 164, //0xA4
2372- perv_dpll_bndy = 165, //0xA5
2373- perv_dpll_time = 166, //0xA6
2374- perv_pll_func = 167, //0xA7
2375- perv_pll_bndy = 168, //0xA8
2376- n0_fure = 169, //0xA9
2377- n1_fure = 170, //0xAA
2378- n1_nmmu1_fure = 171, //0xAB
2379- pci_fure = 172, //0xAC
2380- pci_pll_func = 173, //0xAD
2381- pci_pll_bndy = 174, //0xAE
2382- mc_fure = 175, //0xAF
2383- mc_pll_func = 176, //0xB0
2384- mc_pll_bndy = 177, //0xB1
2385- mc_pll_bndy_bucket_0 = 178, //0xB2
2386- mc_pll_bndy_bucket_1 = 179, //0xB3
2387- mc_pll_bndy_bucket_2 = 180, //0xB4
2388- mc_pll_bndy_bucket_3 = 181, //0xB5
2389- mc_pll_bndy_bucket_4 = 182, //0xB6
2390- pau0_fure = 183, //0xB7
2391- pau0_pau0_fure = 184, //0xB8
2392- pau1_fure = 185, //0xB9
2393- pau1_pau3_fure = 186, //0xBA
2394- pau2_fure = 187, //0xBB
2395- pau2_pau4_fure = 188, //0xBC
2396- pau2_pau5_fure = 189, //0xBD
2397- pau3_fure = 190, //0xBE
2398- pau3_pau6_fure = 191, //0xBF
2399- pau3_pau7_fure = 192, //0xC0
2400- iohs0_fure = 193, //0xC1
2401- iohs0_ndl_fure = 194, //0xC2
2402- iohs0_pdl_fure = 195, //0xC3
2403- iohs0_pll_func = 196, //0xC4
2404- iohs0_pll_bndy = 197, //0xC5
2405- iohs0_pll_bndy_bucket_0 = 198, //0xC6
2406- iohs0_pll_bndy_bucket_1 = 199, //0xC7
2407- iohs0_pll_bndy_bucket_2 = 200, //0xC8
2408- iohs0_pll_bndy_bucket_3 = 201, //0xC9
2409- iohs0_pll_bndy_bucket_4 = 202, //0xCA
2410- iohs0_pll_bndy_bucket_5 = 203, //0xCB
2411- iohs0_pll_bndy_bucket_6 = 204, //0xCC
2412- iohs0_pll_bndy_bucket_7 = 205, //0xCD
2413- iohs1_fure = 206, //0xCE
2414- iohs1_ndl_fure = 207, //0xCF
2415- iohs1_pdl_fure = 208, //0xD0
2416- iohs1_pll_func = 209, //0xD1
2417- iohs2_fure = 210, //0xD2
2418- iohs2_ndl_fure = 211, //0xD3
2419- iohs2_pdl_fure = 212, //0xD4
2420- iohs2_pll_func = 213, //0xD5
2421- iohs3_fure = 214, //0xD6
2422- iohs3_ndl_fure = 215, //0xD7
2423- iohs3_pdl_fure = 216, //0xD8
2424- iohs3_pll_func = 217, //0xD9
2425- iohs4_fure = 218, //0xDA
2426- iohs4_ndl_fure = 219, //0xDB
2427- iohs4_pdl_fure = 220, //0xDC
2428- iohs4_pll_func = 221, //0xDD
2429- iohs5_fure = 222, //0xDE
2430- iohs5_ndl_fure = 223, //0xDF
2431- iohs5_pdl_fure = 224, //0xE0
2432- iohs5_pll_func = 225, //0xE1
2433- iohs6_fure = 226, //0xE2
2434- iohs6_ndl_fure = 227, //0xE3
2435- iohs6_pdl_fure = 228, //0xE4
2436- iohs6_pll_func = 229, //0xE5
2437- iohs7_fure = 230, //0xE6
2438- iohs7_ndl_fure = 231, //0xE7
2439- iohs7_pdl_fure = 232, //0xE8
2440- iohs7_pll_func = 233, //0xE9
2441- eq_fure = 234, //0xEA
2442- eq_cmsk = 235, //0xEB
2443- eq_inex = 236, //0xEC
2444- eq_mode = 237, //0xED
2445- eq_clkadj_fure = 238, //0xEE
2446- eq_clkadj_cmsk = 239, //0xEF
2447- eq_clkadj_inex = 240, //0xF0
2448- eq_clkadj_mode = 241, //0xF1
2449- ec_cl2_fure = 242, //0xF2
2450- ec_cl2_cmsk = 243, //0xF3
2451- ec_cl2_inex = 244, //0xF4
2452- ec_cl2_mode = 245, //0xF5
2453- ec_mma_fure = 246, //0xF6
2454- ec_mma_cmsk = 247, //0xF7
2455- ec_mma_inex = 248, //0xF8
2456- ec_l3_fure = 249, //0xF9
2457- ec_l3_cmsk = 250, //0xFA
2458- ec_l3_inex = 251, //0xFB
2459- ec_l3_mode = 252, //0xFC
2460- n0_abst = 253, //0xFD
2461- n1_abst = 254, //0xFE
2462- n1_nmmu1_abst = 255, //0xFF
2463- ec_cl2_abst = 256, //0x100
2464- ec_mma_abst = 257, //0x101
2465+ perv_fure = 256, //0x100
2466+ sbe_fure = 257, //0x101
2467+ occ_fure = 258, //0x102
2468+ perv_dpll_func = 259, //0x103
2469+ perv_dpll_bndy = 260, //0x104
2470+ perv_dpll_time = 261, //0x105
2471+ perv_pll_func = 262, //0x106
2472+ perv_pll_bndy = 263, //0x107
2473+ n0_fure = 264, //0x108
2474+ n1_fure = 265, //0x109
2475+ n1_nmmu1_fure = 266, //0x10A
2476+ pci_fure = 267, //0x10B
2477+ pci_pll_func = 268, //0x10C
2478+ pci_pll_bndy = 269, //0x10D
2479+ mc_fure = 270, //0x10E
2480+ mc_pll_func = 271, //0x10F
2481+ mc_pll_bndy = 272, //0x110
2482+ mc_pll_bndy_bucket_0 = 273, //0x111
2483+ mc_pll_bndy_bucket_1 = 274, //0x112
2484+ mc_pll_bndy_bucket_2 = 275, //0x113
2485+ mc_pll_bndy_bucket_3 = 276, //0x114
2486+ mc_pll_bndy_bucket_4 = 277, //0x115
2487+ pau0_fure = 278, //0x116
2488+ pau0_pau0_fure = 279, //0x117
2489+ pau1_fure = 280, //0x118
2490+ pau1_pau3_fure = 281, //0x119
2491+ pau2_fure = 282, //0x11A
2492+ pau2_pau4_fure = 283, //0x11B
2493+ pau2_pau5_fure = 284, //0x11C
2494+ pau3_fure = 285, //0x11D
2495+ pau3_pau6_fure = 286, //0x11E
2496+ pau3_pau7_fure = 287, //0x11F
2497+ iohs0_fure = 288, //0x120
2498+ iohs0_ndl_fure = 289, //0x121
2499+ iohs0_pdl_fure = 290, //0x122
2500+ iohs0_pll_func = 291, //0x123
2501+ iohs0_pll_bndy = 292, //0x124
2502+ iohs0_pll_bndy_bucket_0 = 293, //0x125
2503+ iohs0_pll_bndy_bucket_1 = 294, //0x126
2504+ iohs0_pll_bndy_bucket_2 = 295, //0x127
2505+ iohs0_pll_bndy_bucket_3 = 296, //0x128
2506+ iohs0_pll_bndy_bucket_4 = 297, //0x129
2507+ iohs0_pll_bndy_bucket_5 = 298, //0x12A
2508+ iohs0_pll_bndy_bucket_6 = 299, //0x12B
2509+ iohs0_pll_bndy_bucket_7 = 300, //0x12C
2510+ iohs1_fure = 301, //0x12D
2511+ iohs1_ndl_fure = 302, //0x12E
2512+ iohs1_pdl_fure = 303, //0x12F
2513+ iohs1_pll_func = 304, //0x130
2514+ iohs2_fure = 305, //0x131
2515+ iohs2_ndl_fure = 306, //0x132
2516+ iohs2_pdl_fure = 307, //0x133
2517+ iohs2_pll_func = 308, //0x134
2518+ iohs3_fure = 309, //0x135
2519+ iohs3_ndl_fure = 310, //0x136
2520+ iohs3_pdl_fure = 311, //0x137
2521+ iohs3_pll_func = 312, //0x138
2522+ iohs4_fure = 313, //0x139
2523+ iohs4_ndl_fure = 314, //0x13A
2524+ iohs4_pdl_fure = 315, //0x13B
2525+ iohs4_pll_func = 316, //0x13C
2526+ iohs5_fure = 317, //0x13D
2527+ iohs5_ndl_fure = 318, //0x13E
2528+ iohs5_pdl_fure = 319, //0x13F
2529+ iohs5_pll_func = 320, //0x140
2530+ iohs6_fure = 321, //0x141
2531+ iohs6_ndl_fure = 322, //0x142
2532+ iohs6_pdl_fure = 323, //0x143
2533+ iohs6_pll_func = 324, //0x144
2534+ iohs7_fure = 325, //0x145
2535+ iohs7_ndl_fure = 326, //0x146
2536+ iohs7_pdl_fure = 327, //0x147
2537+ iohs7_pll_func = 328, //0x148
2538+ eq_fure = 329, //0x149
2539+ eq_cmsk = 330, //0x14A
2540+ eq_inex = 331, //0x14B
2541+ eq_mode = 332, //0x14C
2542+ eq_clkadj_fure = 333, //0x14D
2543+ eq_clkadj_cmsk = 334, //0x14E
2544+ eq_clkadj_inex = 335, //0x14F
2545+ eq_clkadj_mode = 336, //0x150
2546+ ec_cl2_fure = 337, //0x151
2547+ ec_cl2_cmsk = 338, //0x152
2548+ ec_cl2_inex = 339, //0x153
2549+ ec_cl2_mode = 340, //0x154
2550+ ec_mma_fure = 341, //0x155
2551+ ec_mma_cmsk = 342, //0x156
2552+ ec_mma_inex = 343, //0x157
2553+ ec_l3_fure = 344, //0x158
2554+ ec_l3_cmsk = 345, //0x159
2555+ ec_l3_inex = 346, //0x15A
2556+ ec_l3_mode = 347, //0x15B
2557+ n0_abst = 348, //0x15C
2558+ n1_abst = 349, //0x15D
2559+ n1_nmmu1_abst = 350, //0x15E
2560+ ec_cl2_abst = 351, //0x15F
2561+ ec_mma_abst = 352, //0x160
2562 NUM_RING_IDS_EKB = 97,
2563
2564 NUM_RING_IDS = 258, // = NUM_RING_IDS_MVPD + NUM_RING_IDS_EKB
2565diff --git a/src/import/chips/p10/utils/imageProcs/p10_ring_properties.H b/src/import/chips/p10/utils/imageProcs/p10_ring_properties.H
2566index 63e39f1..514eb68 100644
2567--- a/src/import/chips/p10/utils/imageProcs/p10_ring_properties.H
2568+++ b/src/import/chips/p10/utils/imageProcs/p10_ring_properties.H
2569@@ -26,11 +26,20 @@
2570 #define _P10_RING_PROPERTIES_H_
2571
2572 static const uint8_t RING_TABLE_VERSION_DOC = 22;
2573-static const uint8_t RING_TABLE_VERSION_MVPD = 21;
2574-static const uint8_t RING_TABLE_VERSION_EKB = 21;
2575+static const uint8_t RING_TABLE_VERSION_MVPD = 22;
2576+static const uint8_t RING_TABLE_VERSION_EKB = 22;
2577
2578+// RingID values where the MVPD and EKB rings' enum values start
2579+// (Used in p10_ring_id.H)
2580 #define RINGID_START_MVPD (RingId_t)0
2581-#define RINGID_START_EKB (RingId_t)161
2582+#define RINGID_END_MVPD (RingId_t)160
2583+#define RINGID_START_EKB (RingId_t)256
2584+#define RINGID_END_EKB (RingId_t)352
2585+
2586+// Ring indices where the MVPD and EKB rings' metadata start
2587+// (Used in p10_ring_properties.H (This file))
2588+#define RING_INDEX_START_MVPD (RingId_t)0
2589+#define RING_INDEX_START_EKB (RingId_t)161
2590
2591 namespace PERV
2592 {
2593@@ -600,266 +609,266 @@ static const ChipletData_t g_chipletData =
2594 static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
2595 {
2596 // MVPD Rings:
2597- {"perv_occ_gptr" , 0x01034902, PERV::perv_occ_gptr , PERV_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 0
2598- {"perv_occ_repr" , 0x01034906, PERV::perv_occ_repr , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 1
2599- {"perv_occ_time" , 0x01034907, PERV::perv_occ_time , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 2
2600- {"pib_repr" , 0x01031006, PERV::pib_repr , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 3
2601- {"sbe_gptr" , 0x01032002, PERV::sbe_gptr , PERV_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 4
2602- {"sbe_repr" , 0x01032006, PERV::sbe_repr , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 5
2603- {"sbe_time" , 0x01032007, PERV::sbe_time , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 6
2604- {"invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 7
2605- {"perv_dpll_gptr" , 0x01030062, PERV::perv_dpll_gptr , PERV_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 8
2606- {"perv_pll_gptr" , 0x01030012, PERV::perv_pll_gptr , PERV_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 9
2607- {"n0_gptr" , 0x02036402, N0::n0_gptr , N0_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 10
2608- {"n0_repr" , 0x02036406, N0::n0_repr , N0_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 11
2609- {"n0_time" , 0x02036407, N0::n0_time , N0_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 12
2610- {"n1_gptr" , 0x03035402, N1::n1_gptr , N1_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 13
2611- {"n1_repr" , 0x03035406, N1::n1_repr , N1_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 14
2612- {"n1_time" , 0x03035407, N1::n1_time , N1_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 15
2613- {"n1_nmmu1_gptr" , 0x03030202, N1::n1_nmmu1_gptr , N1_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 16
2614- {"n1_nmmu1_repr" , 0x03030206, N1::n1_nmmu1_repr , N1_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 17
2615- {"n1_nmmu1_time" , 0x03030207, N1::n1_nmmu1_time , N1_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 18
2616- {"pci_gptr" , 0x08037F82, PCI::pci_gptr , PCI_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 19
2617- {"pci_repr" , 0x08037F86, PCI::pci_repr , PCI_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 20
2618- {"pci_time" , 0x08037F87, PCI::pci_time , PCI_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 21
2619- {"pci_pll_gptr" , 0x08030012, PCI::pci_pll_gptr , PCI_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 22
2620- {"mc_gptr" , 0x0C036F02, MC::mc_gptr , MC_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 23
2621- {"mc_repr" , 0x0C036F06, MC::mc_repr , MC_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 24
2622- {"mc_time" , 0x0C036F07, MC::mc_time , MC_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 25
2623- {"mc_pll_gptr" , 0x0C030012, MC::mc_pll_gptr , MC_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 26
2624- {"pau0_gptr" , 0x10034302, PAU0::pau0_gptr , PAU0_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 27
2625- {"pau0_repr" , 0x10034306, PAU0::pau0_repr , PAU0_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 28
2626- {"pau0_time" , 0x10034307, PAU0::pau0_time , PAU0_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 29
2627- {"pau0_pau0_gptr" , 0x10032002, PAU0::pau0_pau0_gptr , PAU0_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 30
2628- {"pau0_pau0_repr" , 0x10032006, PAU0::pau0_pau0_repr , PAU0_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 31
2629- {"pau0_pau0_time" , 0x10032007, PAU0::pau0_pau0_time , PAU0_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 32
2630- {"pau1_gptr" , 0x11034302, PAU1::pau1_gptr , PAU1_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 33
2631- {"pau1_repr" , 0x11034306, PAU1::pau1_repr , PAU1_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 34
2632- {"pau1_time" , 0x11034307, PAU1::pau1_time , PAU1_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 35
2633- {"pau1_pau3_gptr" , 0x11032002, PAU1::pau1_pau3_gptr , PAU1_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 36
2634- {"pau1_pau3_repr" , 0x11032006, PAU1::pau1_pau3_repr , PAU1_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 37
2635- {"pau1_pau3_time" , 0x11032007, PAU1::pau1_pau3_time , PAU1_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 38
2636- {"pau2_gptr" , 0x12034302, PAU2::pau2_gptr , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 39
2637- {"pau2_repr" , 0x12034306, PAU2::pau2_repr , PAU2_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 40
2638- {"pau2_time" , 0x12034307, PAU2::pau2_time , PAU2_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 41
2639- {"pau2_pau4_gptr" , 0x12032002, PAU2::pau2_pau4_gptr , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 42
2640- {"pau2_pau4_repr" , 0x12032006, PAU2::pau2_pau4_repr , PAU2_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 43
2641- {"pau2_pau4_time" , 0x12032007, PAU2::pau2_pau4_time , PAU2_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 44
2642- {"pau2_pau5_gptr" , 0x12031002, PAU2::pau2_pau5_gptr , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 45
2643- {"pau2_pau5_repr" , 0x12031006, PAU2::pau2_pau5_repr , PAU2_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 46
2644- {"pau2_pau5_time" , 0x12031007, PAU2::pau2_pau5_time , PAU2_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 47
2645- {"pau3_gptr" , 0x13034302, PAU3::pau3_gptr , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 48
2646- {"pau3_repr" , 0x13034306, PAU3::pau3_repr , PAU3_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 49
2647- {"pau3_time" , 0x13034307, PAU3::pau3_time , PAU3_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 50
2648- {"pau3_pau6_gptr" , 0x13032002, PAU3::pau3_pau6_gptr , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 51
2649- {"pau3_pau6_repr" , 0x13032006, PAU3::pau3_pau6_repr , PAU3_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 52
2650- {"pau3_pau6_time" , 0x13032007, PAU3::pau3_pau6_time , PAU3_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 53
2651- {"pau3_pau7_gptr" , 0x13031002, PAU3::pau3_pau7_gptr , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 54
2652- {"pau3_pau7_repr" , 0x13031006, PAU3::pau3_pau7_repr , PAU3_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 55
2653- {"pau3_pau7_time" , 0x13031007, PAU3::pau3_pau7_time , PAU3_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 56
2654- {"iohs0_gptr" , 0x18036002, AXON0::iohs0_gptr , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 57
2655- {"iohs0_repr" , 0x18036006, AXON0::iohs0_repr , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 58
2656- {"iohs0_time" , 0x18036007, AXON0::iohs0_time , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 59
2657- {"iohs0_ndl_gptr" , 0x18030402, AXON0::iohs0_ndl_gptr , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 60
2658- {"iohs0_ndl_repr" , 0x18030406, AXON0::iohs0_ndl_repr , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 61
2659- {"iohs0_ndl_time" , 0x18030407, AXON0::iohs0_ndl_time , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 62
2660- {"iohs0_pdl_gptr" , 0x18030202, AXON0::iohs0_pdl_gptr , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 63
2661- {"iohs0_pdl_repr" , 0x18030206, AXON0::iohs0_pdl_repr , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 64
2662- {"iohs0_pdl_time" , 0x18030207, AXON0::iohs0_pdl_time , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 65
2663- {"iohs0_pll_gptr" , 0x18030012, AXON0::iohs0_pll_gptr , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 66
2664- {"iohs1_gptr" , 0x19036002, AXON1::iohs1_gptr , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 67
2665- {"iohs1_repr" , 0x19036006, AXON1::iohs1_repr , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 68
2666- {"iohs1_time" , 0x19036007, AXON1::iohs1_time , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 69
2667- {"iohs1_ndl_gptr" , 0x19030402, AXON1::iohs1_ndl_gptr , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 70
2668- {"iohs1_ndl_repr" , 0x19030406, AXON1::iohs1_ndl_repr , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 71
2669- {"iohs1_ndl_time" , 0x19030407, AXON1::iohs1_ndl_time , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 72
2670- {"iohs1_pdl_gptr" , 0x19030202, AXON1::iohs1_pdl_gptr , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 73
2671- {"iohs1_pdl_repr" , 0x19030206, AXON1::iohs1_pdl_repr , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 74
2672- {"iohs1_pdl_time" , 0x19030207, AXON1::iohs1_pdl_time , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 75
2673- {"iohs1_pll_gptr" , 0x19030012, AXON1::iohs1_pll_gptr , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 76
2674- {"iohs2_gptr" , 0x1A036002, AXON2::iohs2_gptr , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 77
2675- {"iohs2_repr" , 0x1A036006, AXON2::iohs2_repr , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 78
2676- {"iohs2_time" , 0x1A036007, AXON2::iohs2_time , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 79
2677- {"iohs2_ndl_gptr" , 0x1A030402, AXON2::iohs2_ndl_gptr , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 80
2678- {"iohs2_ndl_repr" , 0x1A030406, AXON2::iohs2_ndl_repr , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 81
2679- {"iohs2_ndl_time" , 0x1A030407, AXON2::iohs2_ndl_time , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 82
2680- {"iohs2_pdl_gptr" , 0x1A030202, AXON2::iohs2_pdl_gptr , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 83
2681- {"iohs2_pdl_repr" , 0x1A030206, AXON2::iohs2_pdl_repr , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 84
2682- {"iohs2_pdl_time" , 0x1A030207, AXON2::iohs2_pdl_time , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 85
2683- {"iohs2_pll_gptr" , 0x1A030012, AXON2::iohs2_pll_gptr , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 86
2684- {"iohs3_gptr" , 0x1B036002, AXON3::iohs3_gptr , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 87
2685- {"iohs3_repr" , 0x1B036006, AXON3::iohs3_repr , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 88
2686- {"iohs3_time" , 0x1B036007, AXON3::iohs3_time , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 89
2687- {"iohs3_ndl_gptr" , 0x1B030402, AXON3::iohs3_ndl_gptr , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 90
2688- {"iohs3_ndl_repr" , 0x1B030406, AXON3::iohs3_ndl_repr , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 91
2689- {"iohs3_ndl_time" , 0x1B030407, AXON3::iohs3_ndl_time , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 92
2690- {"iohs3_pdl_gptr" , 0x1B030202, AXON3::iohs3_pdl_gptr , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 93
2691- {"iohs3_pdl_repr" , 0x1B030206, AXON3::iohs3_pdl_repr , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 94
2692- {"iohs3_pdl_time" , 0x1B030207, AXON3::iohs3_pdl_time , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 95
2693- {"iohs3_pll_gptr" , 0x1B030012, AXON3::iohs3_pll_gptr , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 96
2694- {"iohs4_gptr" , 0x1C036002, AXON4::iohs4_gptr , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 97
2695- {"iohs4_repr" , 0x1C036006, AXON4::iohs4_repr , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 98
2696- {"iohs4_time" , 0x1C036007, AXON4::iohs4_time , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 99
2697- {"iohs4_ndl_gptr" , 0x1C030402, AXON4::iohs4_ndl_gptr , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 100
2698- {"iohs4_ndl_repr" , 0x1C030406, AXON4::iohs4_ndl_repr , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 101
2699- {"iohs4_ndl_time" , 0x1C030407, AXON4::iohs4_ndl_time , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 102
2700- {"iohs4_pdl_gptr" , 0x1C030202, AXON4::iohs4_pdl_gptr , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 103
2701- {"iohs4_pdl_repr" , 0x1C030206, AXON4::iohs4_pdl_repr , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 104
2702- {"iohs4_pdl_time" , 0x1C030207, AXON4::iohs4_pdl_time , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 105
2703- {"iohs4_pll_gptr" , 0x1C030012, AXON4::iohs4_pll_gptr , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 106
2704- {"iohs5_gptr" , 0x1D036002, AXON5::iohs5_gptr , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 107
2705- {"iohs5_repr" , 0x1D036006, AXON5::iohs5_repr , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 108
2706- {"iohs5_time" , 0x1D036007, AXON5::iohs5_time , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 109
2707- {"iohs5_ndl_gptr" , 0x1D030402, AXON5::iohs5_ndl_gptr , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 110
2708- {"iohs5_ndl_repr" , 0x1D030406, AXON5::iohs5_ndl_repr , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 111
2709- {"iohs5_ndl_time" , 0x1D030407, AXON5::iohs5_ndl_time , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 112
2710- {"iohs5_pdl_gptr" , 0x1D030202, AXON5::iohs5_pdl_gptr , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 113
2711- {"iohs5_pdl_repr" , 0x1D030206, AXON5::iohs5_pdl_repr , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 114
2712- {"iohs5_pdl_time" , 0x1D030207, AXON5::iohs5_pdl_time , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 115
2713- {"iohs5_pll_gptr" , 0x1D030012, AXON5::iohs5_pll_gptr , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 116
2714- {"iohs6_gptr" , 0x1E036002, AXON6::iohs6_gptr , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 117
2715- {"iohs6_repr" , 0x1E036006, AXON6::iohs6_repr , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 118
2716- {"iohs6_time" , 0x1E036007, AXON6::iohs6_time , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 119
2717- {"iohs6_ndl_gptr" , 0x1E030402, AXON6::iohs6_ndl_gptr , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 120
2718- {"iohs6_ndl_repr" , 0x1E030406, AXON6::iohs6_ndl_repr , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 121
2719- {"iohs6_ndl_time" , 0x1E030407, AXON6::iohs6_ndl_time , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 122
2720- {"iohs6_pdl_gptr" , 0x1E030202, AXON6::iohs6_pdl_gptr , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 123
2721- {"iohs6_pdl_repr" , 0x1E030206, AXON6::iohs6_pdl_repr , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 124
2722- {"iohs6_pdl_time" , 0x1E030207, AXON6::iohs6_pdl_time , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 125
2723- {"iohs6_pll_gptr" , 0x1E030012, AXON6::iohs6_pll_gptr , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 126
2724- {"iohs7_gptr" , 0x1F036002, AXON7::iohs7_gptr , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 127
2725- {"iohs7_repr" , 0x1F036006, AXON7::iohs7_repr , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 128
2726- {"iohs7_time" , 0x1F036007, AXON7::iohs7_time , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 129
2727- {"iohs7_ndl_gptr" , 0x1F030402, AXON7::iohs7_ndl_gptr , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 130
2728- {"iohs7_ndl_repr" , 0x1F030406, AXON7::iohs7_ndl_repr , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 131
2729- {"iohs7_ndl_time" , 0x1F030407, AXON7::iohs7_ndl_time , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 132
2730- {"iohs7_pdl_gptr" , 0x1F030202, AXON7::iohs7_pdl_gptr , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 133
2731- {"iohs7_pdl_repr" , 0x1F030206, AXON7::iohs7_pdl_repr , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 134
2732- {"iohs7_pdl_time" , 0x1F030207, AXON7::iohs7_pdl_time , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 135
2733- {"iohs7_pll_gptr" , 0x1F030012, AXON7::iohs7_pll_gptr , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 136
2734- {"eq_gptr" , 0x20034022, EQ::eq_gptr , EQ_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 137
2735- {"eq_repr" , 0x20034026, EQ::eq_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_EQ }, // 138
2736- {"eq_time" , 0x20034027, EQ::eq_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 139
2737- {"eq_clkadj_gptr" , 0x20030012, EQ::eq_clkadj_gptr , EQ_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 140
2738- {"eq_clkadj_repr" , 0x20030016, EQ::eq_clkadj_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_EQ }, // 141
2739- {"eq_clkadj_time" , 0x20030017, EQ::eq_clkadj_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 142
2740- {"ec_cl2_gptr" , 0x20032002, EQ::ec_cl2_gptr , EQ_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY | RMRK_SCAN_BY_QME }, // 143
2741- {"ec_cl2_repr" , 0x20032006, EQ::ec_cl2_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 144
2742- {"ec_cl2_time" , 0x20032007, EQ::ec_cl2_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME | RMRK_SCAN_BY_QME }, // 145
2743- {"ec1_cl2_repr" , 0x20031006, EQ::ec1_cl2_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 146
2744- {"ec2_cl2_repr" , 0x20030806, EQ::ec2_cl2_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 147
2745- {"ec3_cl2_repr" , 0x20030406, EQ::ec3_cl2_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 148
2746- {"ec_mma_gptr" , 0x20830002, EQ::ec_mma_gptr , EQ_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY | RMRK_SCAN_BY_QME }, // 149
2747- {"ec_mma_repr" , 0x20830006, EQ::ec_mma_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 150
2748- {"ec_mma_time" , 0x20830007, EQ::ec_mma_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME | RMRK_SCAN_BY_QME }, // 151
2749- {"ec1_mma_repr" , 0x20430006, EQ::ec1_mma_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 152
2750- {"ec2_mma_repr" , 0x20230006, EQ::ec2_mma_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 153
2751- {"ec3_mma_repr" , 0x20130006, EQ::ec3_mma_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 154
2752- {"ec_l3_gptr" , 0x20030202, EQ::ec_l3_gptr , EQ_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY | RMRK_SCAN_BY_QME }, // 155
2753- {"ec_l3_repr" , 0x20030206, EQ::ec_l3_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 156
2754- {"ec_l3_time" , 0x20030207, EQ::ec_l3_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME | RMRK_SCAN_BY_QME }, // 157
2755- {"ec1_l3_repr" , 0x20030106, EQ::ec1_l3_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 158
2756- {"ec2_l3_repr" , 0x20030086, EQ::ec2_l3_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 159
2757- {"ec3_l3_repr" , 0x20030046, EQ::ec3_l3_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 160
2758+ {perv_occ_gptr , "perv_occ_gptr" , 0x01034902, PERV::perv_occ_gptr , PERV_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 0
2759+ {perv_occ_repr , "perv_occ_repr" , 0x01034906, PERV::perv_occ_repr , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 1
2760+ {perv_occ_time , "perv_occ_time" , 0x01034907, PERV::perv_occ_time , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 2
2761+ {pib_repr , "pib_repr" , 0x01031006, PERV::pib_repr , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 3
2762+ {sbe_gptr , "sbe_gptr" , 0x01032002, PERV::sbe_gptr , PERV_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 4
2763+ {sbe_repr , "sbe_repr" , 0x01032006, PERV::sbe_repr , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 5
2764+ {sbe_time , "sbe_time" , 0x01032007, PERV::sbe_time , PERV_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 6
2765+ {HOLE_RING_ID , "invalid" , UNDEFINED_SCOM_ADDR, UNDEFINED_RING_INDEX , UNDEFINED_CHIPLET_TYPE, UNDEFINED_RING_CLASS }, // 7
2766+ {perv_dpll_gptr , "perv_dpll_gptr" , 0x01030062, PERV::perv_dpll_gptr , PERV_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 8
2767+ {perv_pll_gptr , "perv_pll_gptr" , 0x01030012, PERV::perv_pll_gptr , PERV_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 9
2768+ {n0_gptr , "n0_gptr" , 0x02036402, N0::n0_gptr , N0_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 10
2769+ {n0_repr , "n0_repr" , 0x02036406, N0::n0_repr , N0_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 11
2770+ {n0_time , "n0_time" , 0x02036407, N0::n0_time , N0_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 12
2771+ {n1_gptr , "n1_gptr" , 0x03035402, N1::n1_gptr , N1_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 13
2772+ {n1_repr , "n1_repr" , 0x03035406, N1::n1_repr , N1_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 14
2773+ {n1_time , "n1_time" , 0x03035407, N1::n1_time , N1_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 15
2774+ {n1_nmmu1_gptr , "n1_nmmu1_gptr" , 0x03030202, N1::n1_nmmu1_gptr , N1_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 16
2775+ {n1_nmmu1_repr , "n1_nmmu1_repr" , 0x03030206, N1::n1_nmmu1_repr , N1_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 17
2776+ {n1_nmmu1_time , "n1_nmmu1_time" , 0x03030207, N1::n1_nmmu1_time , N1_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 18
2777+ {pci_gptr , "pci_gptr" , 0x08037F82, PCI::pci_gptr , PCI_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 19
2778+ {pci_repr , "pci_repr" , 0x08037F86, PCI::pci_repr , PCI_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 20
2779+ {pci_time , "pci_time" , 0x08037F87, PCI::pci_time , PCI_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 21
2780+ {pci_pll_gptr , "pci_pll_gptr" , 0x08030012, PCI::pci_pll_gptr , PCI_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 22
2781+ {mc_gptr , "mc_gptr" , 0x0C036F02, MC::mc_gptr , MC_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 23
2782+ {mc_repr , "mc_repr" , 0x0C036F06, MC::mc_repr , MC_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 24
2783+ {mc_time , "mc_time" , 0x0C036F07, MC::mc_time , MC_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 25
2784+ {mc_pll_gptr , "mc_pll_gptr" , 0x0C030012, MC::mc_pll_gptr , MC_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 26
2785+ {pau0_gptr , "pau0_gptr" , 0x10034302, PAU0::pau0_gptr , PAU0_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 27
2786+ {pau0_repr , "pau0_repr" , 0x10034306, PAU0::pau0_repr , PAU0_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 28
2787+ {pau0_time , "pau0_time" , 0x10034307, PAU0::pau0_time , PAU0_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 29
2788+ {pau0_pau0_gptr , "pau0_pau0_gptr" , 0x10032002, PAU0::pau0_pau0_gptr , PAU0_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 30
2789+ {pau0_pau0_repr , "pau0_pau0_repr" , 0x10032006, PAU0::pau0_pau0_repr , PAU0_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 31
2790+ {pau0_pau0_time , "pau0_pau0_time" , 0x10032007, PAU0::pau0_pau0_time , PAU0_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 32
2791+ {pau1_gptr , "pau1_gptr" , 0x11034302, PAU1::pau1_gptr , PAU1_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 33
2792+ {pau1_repr , "pau1_repr" , 0x11034306, PAU1::pau1_repr , PAU1_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 34
2793+ {pau1_time , "pau1_time" , 0x11034307, PAU1::pau1_time , PAU1_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 35
2794+ {pau1_pau3_gptr , "pau1_pau3_gptr" , 0x11032002, PAU1::pau1_pau3_gptr , PAU1_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 36
2795+ {pau1_pau3_repr , "pau1_pau3_repr" , 0x11032006, PAU1::pau1_pau3_repr , PAU1_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 37
2796+ {pau1_pau3_time , "pau1_pau3_time" , 0x11032007, PAU1::pau1_pau3_time , PAU1_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 38
2797+ {pau2_gptr , "pau2_gptr" , 0x12034302, PAU2::pau2_gptr , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 39
2798+ {pau2_repr , "pau2_repr" , 0x12034306, PAU2::pau2_repr , PAU2_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 40
2799+ {pau2_time , "pau2_time" , 0x12034307, PAU2::pau2_time , PAU2_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 41
2800+ {pau2_pau4_gptr , "pau2_pau4_gptr" , 0x12032002, PAU2::pau2_pau4_gptr , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 42
2801+ {pau2_pau4_repr , "pau2_pau4_repr" , 0x12032006, PAU2::pau2_pau4_repr , PAU2_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 43
2802+ {pau2_pau4_time , "pau2_pau4_time" , 0x12032007, PAU2::pau2_pau4_time , PAU2_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 44
2803+ {pau2_pau5_gptr , "pau2_pau5_gptr" , 0x12031002, PAU2::pau2_pau5_gptr , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 45
2804+ {pau2_pau5_repr , "pau2_pau5_repr" , 0x12031006, PAU2::pau2_pau5_repr , PAU2_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 46
2805+ {pau2_pau5_time , "pau2_pau5_time" , 0x12031007, PAU2::pau2_pau5_time , PAU2_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 47
2806+ {pau3_gptr , "pau3_gptr" , 0x13034302, PAU3::pau3_gptr , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 48
2807+ {pau3_repr , "pau3_repr" , 0x13034306, PAU3::pau3_repr , PAU3_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 49
2808+ {pau3_time , "pau3_time" , 0x13034307, PAU3::pau3_time , PAU3_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 50
2809+ {pau3_pau6_gptr , "pau3_pau6_gptr" , 0x13032002, PAU3::pau3_pau6_gptr , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 51
2810+ {pau3_pau6_repr , "pau3_pau6_repr" , 0x13032006, PAU3::pau3_pau6_repr , PAU3_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 52
2811+ {pau3_pau6_time , "pau3_pau6_time" , 0x13032007, PAU3::pau3_pau6_time , PAU3_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 53
2812+ {pau3_pau7_gptr , "pau3_pau7_gptr" , 0x13031002, PAU3::pau3_pau7_gptr , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 54
2813+ {pau3_pau7_repr , "pau3_pau7_repr" , 0x13031006, PAU3::pau3_pau7_repr , PAU3_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 55
2814+ {pau3_pau7_time , "pau3_pau7_time" , 0x13031007, PAU3::pau3_pau7_time , PAU3_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 56
2815+ {iohs0_gptr , "iohs0_gptr" , 0x18036002, AXON0::iohs0_gptr , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 57
2816+ {iohs0_repr , "iohs0_repr" , 0x18036006, AXON0::iohs0_repr , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 58
2817+ {iohs0_time , "iohs0_time" , 0x18036007, AXON0::iohs0_time , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 59
2818+ {iohs0_ndl_gptr , "iohs0_ndl_gptr" , 0x18030402, AXON0::iohs0_ndl_gptr , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 60
2819+ {iohs0_ndl_repr , "iohs0_ndl_repr" , 0x18030406, AXON0::iohs0_ndl_repr , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 61
2820+ {iohs0_ndl_time , "iohs0_ndl_time" , 0x18030407, AXON0::iohs0_ndl_time , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 62
2821+ {iohs0_pdl_gptr , "iohs0_pdl_gptr" , 0x18030202, AXON0::iohs0_pdl_gptr , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 63
2822+ {iohs0_pdl_repr , "iohs0_pdl_repr" , 0x18030206, AXON0::iohs0_pdl_repr , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 64
2823+ {iohs0_pdl_time , "iohs0_pdl_time" , 0x18030207, AXON0::iohs0_pdl_time , AXON0_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 65
2824+ {iohs0_pll_gptr , "iohs0_pll_gptr" , 0x18030012, AXON0::iohs0_pll_gptr , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 66
2825+ {iohs1_gptr , "iohs1_gptr" , 0x19036002, AXON1::iohs1_gptr , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 67
2826+ {iohs1_repr , "iohs1_repr" , 0x19036006, AXON1::iohs1_repr , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 68
2827+ {iohs1_time , "iohs1_time" , 0x19036007, AXON1::iohs1_time , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 69
2828+ {iohs1_ndl_gptr , "iohs1_ndl_gptr" , 0x19030402, AXON1::iohs1_ndl_gptr , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 70
2829+ {iohs1_ndl_repr , "iohs1_ndl_repr" , 0x19030406, AXON1::iohs1_ndl_repr , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 71
2830+ {iohs1_ndl_time , "iohs1_ndl_time" , 0x19030407, AXON1::iohs1_ndl_time , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 72
2831+ {iohs1_pdl_gptr , "iohs1_pdl_gptr" , 0x19030202, AXON1::iohs1_pdl_gptr , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 73
2832+ {iohs1_pdl_repr , "iohs1_pdl_repr" , 0x19030206, AXON1::iohs1_pdl_repr , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 74
2833+ {iohs1_pdl_time , "iohs1_pdl_time" , 0x19030207, AXON1::iohs1_pdl_time , AXON1_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 75
2834+ {iohs1_pll_gptr , "iohs1_pll_gptr" , 0x19030012, AXON1::iohs1_pll_gptr , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 76
2835+ {iohs2_gptr , "iohs2_gptr" , 0x1A036002, AXON2::iohs2_gptr , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 77
2836+ {iohs2_repr , "iohs2_repr" , 0x1A036006, AXON2::iohs2_repr , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 78
2837+ {iohs2_time , "iohs2_time" , 0x1A036007, AXON2::iohs2_time , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 79
2838+ {iohs2_ndl_gptr , "iohs2_ndl_gptr" , 0x1A030402, AXON2::iohs2_ndl_gptr , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 80
2839+ {iohs2_ndl_repr , "iohs2_ndl_repr" , 0x1A030406, AXON2::iohs2_ndl_repr , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 81
2840+ {iohs2_ndl_time , "iohs2_ndl_time" , 0x1A030407, AXON2::iohs2_ndl_time , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 82
2841+ {iohs2_pdl_gptr , "iohs2_pdl_gptr" , 0x1A030202, AXON2::iohs2_pdl_gptr , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 83
2842+ {iohs2_pdl_repr , "iohs2_pdl_repr" , 0x1A030206, AXON2::iohs2_pdl_repr , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 84
2843+ {iohs2_pdl_time , "iohs2_pdl_time" , 0x1A030207, AXON2::iohs2_pdl_time , AXON2_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 85
2844+ {iohs2_pll_gptr , "iohs2_pll_gptr" , 0x1A030012, AXON2::iohs2_pll_gptr , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 86
2845+ {iohs3_gptr , "iohs3_gptr" , 0x1B036002, AXON3::iohs3_gptr , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 87
2846+ {iohs3_repr , "iohs3_repr" , 0x1B036006, AXON3::iohs3_repr , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 88
2847+ {iohs3_time , "iohs3_time" , 0x1B036007, AXON3::iohs3_time , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 89
2848+ {iohs3_ndl_gptr , "iohs3_ndl_gptr" , 0x1B030402, AXON3::iohs3_ndl_gptr , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 90
2849+ {iohs3_ndl_repr , "iohs3_ndl_repr" , 0x1B030406, AXON3::iohs3_ndl_repr , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 91
2850+ {iohs3_ndl_time , "iohs3_ndl_time" , 0x1B030407, AXON3::iohs3_ndl_time , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 92
2851+ {iohs3_pdl_gptr , "iohs3_pdl_gptr" , 0x1B030202, AXON3::iohs3_pdl_gptr , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 93
2852+ {iohs3_pdl_repr , "iohs3_pdl_repr" , 0x1B030206, AXON3::iohs3_pdl_repr , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 94
2853+ {iohs3_pdl_time , "iohs3_pdl_time" , 0x1B030207, AXON3::iohs3_pdl_time , AXON3_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 95
2854+ {iohs3_pll_gptr , "iohs3_pll_gptr" , 0x1B030012, AXON3::iohs3_pll_gptr , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 96
2855+ {iohs4_gptr , "iohs4_gptr" , 0x1C036002, AXON4::iohs4_gptr , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 97
2856+ {iohs4_repr , "iohs4_repr" , 0x1C036006, AXON4::iohs4_repr , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 98
2857+ {iohs4_time , "iohs4_time" , 0x1C036007, AXON4::iohs4_time , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 99
2858+ {iohs4_ndl_gptr , "iohs4_ndl_gptr" , 0x1C030402, AXON4::iohs4_ndl_gptr , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 100
2859+ {iohs4_ndl_repr , "iohs4_ndl_repr" , 0x1C030406, AXON4::iohs4_ndl_repr , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 101
2860+ {iohs4_ndl_time , "iohs4_ndl_time" , 0x1C030407, AXON4::iohs4_ndl_time , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 102
2861+ {iohs4_pdl_gptr , "iohs4_pdl_gptr" , 0x1C030202, AXON4::iohs4_pdl_gptr , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 103
2862+ {iohs4_pdl_repr , "iohs4_pdl_repr" , 0x1C030206, AXON4::iohs4_pdl_repr , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 104
2863+ {iohs4_pdl_time , "iohs4_pdl_time" , 0x1C030207, AXON4::iohs4_pdl_time , AXON4_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 105
2864+ {iohs4_pll_gptr , "iohs4_pll_gptr" , 0x1C030012, AXON4::iohs4_pll_gptr , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 106
2865+ {iohs5_gptr , "iohs5_gptr" , 0x1D036002, AXON5::iohs5_gptr , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 107
2866+ {iohs5_repr , "iohs5_repr" , 0x1D036006, AXON5::iohs5_repr , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 108
2867+ {iohs5_time , "iohs5_time" , 0x1D036007, AXON5::iohs5_time , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 109
2868+ {iohs5_ndl_gptr , "iohs5_ndl_gptr" , 0x1D030402, AXON5::iohs5_ndl_gptr , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 110
2869+ {iohs5_ndl_repr , "iohs5_ndl_repr" , 0x1D030406, AXON5::iohs5_ndl_repr , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 111
2870+ {iohs5_ndl_time , "iohs5_ndl_time" , 0x1D030407, AXON5::iohs5_ndl_time , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 112
2871+ {iohs5_pdl_gptr , "iohs5_pdl_gptr" , 0x1D030202, AXON5::iohs5_pdl_gptr , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 113
2872+ {iohs5_pdl_repr , "iohs5_pdl_repr" , 0x1D030206, AXON5::iohs5_pdl_repr , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 114
2873+ {iohs5_pdl_time , "iohs5_pdl_time" , 0x1D030207, AXON5::iohs5_pdl_time , AXON5_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 115
2874+ {iohs5_pll_gptr , "iohs5_pll_gptr" , 0x1D030012, AXON5::iohs5_pll_gptr , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 116
2875+ {iohs6_gptr , "iohs6_gptr" , 0x1E036002, AXON6::iohs6_gptr , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 117
2876+ {iohs6_repr , "iohs6_repr" , 0x1E036006, AXON6::iohs6_repr , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 118
2877+ {iohs6_time , "iohs6_time" , 0x1E036007, AXON6::iohs6_time , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 119
2878+ {iohs6_ndl_gptr , "iohs6_ndl_gptr" , 0x1E030402, AXON6::iohs6_ndl_gptr , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 120
2879+ {iohs6_ndl_repr , "iohs6_ndl_repr" , 0x1E030406, AXON6::iohs6_ndl_repr , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 121
2880+ {iohs6_ndl_time , "iohs6_ndl_time" , 0x1E030407, AXON6::iohs6_ndl_time , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 122
2881+ {iohs6_pdl_gptr , "iohs6_pdl_gptr" , 0x1E030202, AXON6::iohs6_pdl_gptr , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 123
2882+ {iohs6_pdl_repr , "iohs6_pdl_repr" , 0x1E030206, AXON6::iohs6_pdl_repr , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 124
2883+ {iohs6_pdl_time , "iohs6_pdl_time" , 0x1E030207, AXON6::iohs6_pdl_time , AXON6_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 125
2884+ {iohs6_pll_gptr , "iohs6_pll_gptr" , 0x1E030012, AXON6::iohs6_pll_gptr , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 126
2885+ {iohs7_gptr , "iohs7_gptr" , 0x1F036002, AXON7::iohs7_gptr , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 127
2886+ {iohs7_repr , "iohs7_repr" , 0x1F036006, AXON7::iohs7_repr , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 128
2887+ {iohs7_time , "iohs7_time" , 0x1F036007, AXON7::iohs7_time , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 129
2888+ {iohs7_ndl_gptr , "iohs7_ndl_gptr" , 0x1F030402, AXON7::iohs7_ndl_gptr , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 130
2889+ {iohs7_ndl_repr , "iohs7_ndl_repr" , 0x1F030406, AXON7::iohs7_ndl_repr , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 131
2890+ {iohs7_ndl_time , "iohs7_ndl_time" , 0x1F030407, AXON7::iohs7_ndl_time , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 132
2891+ {iohs7_pdl_gptr , "iohs7_pdl_gptr" , 0x1F030202, AXON7::iohs7_pdl_gptr , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 133
2892+ {iohs7_pdl_repr , "iohs7_pdl_repr" , 0x1F030206, AXON7::iohs7_pdl_repr , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDR_NEST }, // 134
2893+ {iohs7_pdl_time , "iohs7_pdl_time" , 0x1F030207, AXON7::iohs7_pdl_time , AXON7_TYPE, RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 135
2894+ {iohs7_pll_gptr , "iohs7_pll_gptr" , 0x1F030012, AXON7::iohs7_pll_gptr , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 136
2895+ {eq_gptr , "eq_gptr" , 0x20034022, EQ::eq_gptr , EQ_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 137
2896+ {eq_repr , "eq_repr" , 0x20034026, EQ::eq_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_EQ }, // 138
2897+ {eq_time , "eq_time" , 0x20034027, EQ::eq_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 139
2898+ {eq_clkadj_gptr , "eq_clkadj_gptr" , 0x20030012, EQ::eq_clkadj_gptr , EQ_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY }, // 140
2899+ {eq_clkadj_repr , "eq_clkadj_repr" , 0x20030016, EQ::eq_clkadj_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_EQ }, // 141
2900+ {eq_clkadj_time , "eq_clkadj_time" , 0x20030017, EQ::eq_clkadj_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME }, // 142
2901+ {ec_cl2_gptr , "ec_cl2_gptr" , 0x20032002, EQ::ec_cl2_gptr , EQ_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY | RMRK_SCAN_BY_QME }, // 143
2902+ {ec_cl2_repr , "ec_cl2_repr" , 0x20032006, EQ::ec_cl2_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 144
2903+ {ec_cl2_time , "ec_cl2_time" , 0x20032007, EQ::ec_cl2_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME | RMRK_SCAN_BY_QME }, // 145
2904+ {ec1_cl2_repr , "ec1_cl2_repr" , 0x20031006, EQ::ec1_cl2_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 146
2905+ {ec2_cl2_repr , "ec2_cl2_repr" , 0x20030806, EQ::ec2_cl2_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 147
2906+ {ec3_cl2_repr , "ec3_cl2_repr" , 0x20030406, EQ::ec3_cl2_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 148
2907+ {ec_mma_gptr , "ec_mma_gptr" , 0x20830002, EQ::ec_mma_gptr , EQ_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY | RMRK_SCAN_BY_QME }, // 149
2908+ {ec_mma_repr , "ec_mma_repr" , 0x20830006, EQ::ec_mma_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 150
2909+ {ec_mma_time , "ec_mma_time" , 0x20830007, EQ::ec_mma_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME | RMRK_SCAN_BY_QME }, // 151
2910+ {ec1_mma_repr , "ec1_mma_repr" , 0x20430006, EQ::ec1_mma_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 152
2911+ {ec2_mma_repr , "ec2_mma_repr" , 0x20230006, EQ::ec2_mma_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 153
2912+ {ec3_mma_repr , "ec3_mma_repr" , 0x20130006, EQ::ec3_mma_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 154
2913+ {ec_l3_gptr , "ec_l3_gptr" , 0x20030202, EQ::ec_l3_gptr , EQ_TYPE , RMRK_ROOT | RCLS_EKB_MVPD_PDG_OVLY | RMRK_SCAN_BY_QME }, // 155
2914+ {ec_l3_repr , "ec_l3_repr" , 0x20030206, EQ::ec_l3_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 156
2915+ {ec_l3_time , "ec_l3_time" , 0x20030207, EQ::ec_l3_time , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDG_TIME | RMRK_SCAN_BY_QME }, // 157
2916+ {ec1_l3_repr , "ec1_l3_repr" , 0x20030106, EQ::ec1_l3_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 158
2917+ {ec2_l3_repr , "ec2_l3_repr" , 0x20030086, EQ::ec2_l3_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 159
2918+ {ec3_l3_repr , "ec3_l3_repr" , 0x20030046, EQ::ec3_l3_repr , EQ_TYPE , RMRK_ROOT | RCLS_MVPD_PDR_CORE | RMRK_SCAN_BY_QME }, // 160
2919
2920 // EKB Rings:
2921- {"perv_fure" , 0x0103410F, PERV::perv_fure , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 161
2922- {"sbe_fure" , 0x0103200F, PERV::sbe_fure , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 162
2923- {"occ_fure" , 0x0103080F, PERV::occ_fure , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 163
2924- {"perv_dpll_func" , 0x01030060, PERV::perv_dpll_func , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 164
2925- {"perv_dpll_bndy" , 0x01030068, PERV::perv_dpll_bndy , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 165
2926- {"perv_dpll_time" , 0x01030067, PERV::perv_dpll_time , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 166
2927- {"perv_pll_func" , 0x01030010, PERV::perv_pll_func , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 167
2928- {"perv_pll_bndy" , 0x01030018, PERV::perv_pll_bndy , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 168
2929- {"n0_fure" , 0x0203640F, N0::n0_fure , N0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 169
2930- {"n1_fure" , 0x0303540F, N1::n1_fure , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 170
2931- {"n1_nmmu1_fure" , 0x0303020F, N1::n1_nmmu1_fure , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 171
2932- {"pci_fure" , 0x08037F8F, PCI::pci_fure , PCI_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 172
2933- {"pci_pll_func" , 0x08030010, PCI::pci_pll_func , PCI_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 173
2934- {"pci_pll_bndy" , 0x08030018, PCI::pci_pll_bndy , PCI_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 174
2935- {"mc_fure" , 0x0C036F0F, MC::mc_fure , MC_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 175
2936- {"mc_pll_func" , 0x0C030010, MC::mc_pll_func , MC_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 176
2937- {"mc_pll_bndy" , 0x0C030018, MC::mc_pll_bndy , MC_TYPE , RMRK_ROOT | RMRK_HAS_DERIVS | RCLS_EKB_RINGS }, // 177
2938- {"mc_pll_bndy_bucket_0" , 0x0C030018, MC::mc_pll_bndy_bucket_0 , MC_TYPE , RCLS_EKB_RINGS }, // 178
2939- {"mc_pll_bndy_bucket_1" , 0x0C030018, MC::mc_pll_bndy_bucket_1 , MC_TYPE , RCLS_EKB_RINGS }, // 179
2940- {"mc_pll_bndy_bucket_2" , 0x0C030018, MC::mc_pll_bndy_bucket_2 , MC_TYPE , RCLS_EKB_RINGS }, // 180
2941- {"mc_pll_bndy_bucket_3" , 0x0C030018, MC::mc_pll_bndy_bucket_3 , MC_TYPE , RCLS_EKB_RINGS }, // 181
2942- {"mc_pll_bndy_bucket_4" , 0x0C030018, MC::mc_pll_bndy_bucket_4 , MC_TYPE , RCLS_EKB_RINGS }, // 182
2943- {"pau0_fure" , 0x1003430F, PAU0::pau0_fure , PAU0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 183
2944- {"pau0_pau0_fure" , 0x1003200F, PAU0::pau0_pau0_fure , PAU0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 184
2945- {"pau1_fure" , 0x1103430F, PAU1::pau1_fure , PAU1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 185
2946- {"pau1_pau3_fure" , 0x1103200F, PAU1::pau1_pau3_fure , PAU1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 186
2947- {"pau2_fure" , 0x1203430F, PAU2::pau2_fure , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 187
2948- {"pau2_pau4_fure" , 0x1203200F, PAU2::pau2_pau4_fure , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 188
2949- {"pau2_pau5_fure" , 0x1203100F, PAU2::pau2_pau5_fure , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 189
2950- {"pau3_fure" , 0x1303430F, PAU3::pau3_fure , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 190
2951- {"pau3_pau6_fure" , 0x1303200F, PAU3::pau3_pau6_fure , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 191
2952- {"pau3_pau7_fure" , 0x1303100F, PAU3::pau3_pau7_fure , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 192
2953- {"iohs0_fure" , 0x1803600F, AXON0::iohs0_fure , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 193
2954- {"iohs0_ndl_fure" , 0x1803040F, AXON0::iohs0_ndl_fure , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 194
2955- {"iohs0_pdl_fure" , 0x1803020F, AXON0::iohs0_pdl_fure , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 195
2956- {"iohs0_pll_func" , 0x18030010, AXON0::iohs0_pll_func , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 196
2957- {"iohs0_pll_bndy" , 0x18030018, AXON0::iohs0_pll_bndy , AXON0_TYPE, RMRK_ROOT | RMRK_HAS_DERIVS | RCLS_EKB_RINGS }, // 197
2958- {"iohs0_pll_bndy_bucket_0" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_0, AXON0_TYPE, RCLS_EKB_RINGS }, // 198
2959- {"iohs0_pll_bndy_bucket_1" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_1, AXON0_TYPE, RCLS_EKB_RINGS }, // 199
2960- {"iohs0_pll_bndy_bucket_2" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_2, AXON0_TYPE, RCLS_EKB_RINGS }, // 200
2961- {"iohs0_pll_bndy_bucket_3" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_3, AXON0_TYPE, RCLS_EKB_RINGS }, // 201
2962- {"iohs0_pll_bndy_bucket_4" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_4, AXON0_TYPE, RCLS_EKB_RINGS }, // 202
2963- {"iohs0_pll_bndy_bucket_5" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_5, AXON0_TYPE, RCLS_EKB_RINGS }, // 203
2964- {"iohs0_pll_bndy_bucket_6" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_6, AXON0_TYPE, RCLS_EKB_RINGS }, // 204
2965- {"iohs0_pll_bndy_bucket_7" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_7, AXON0_TYPE, RCLS_EKB_RINGS }, // 205
2966- {"iohs1_fure" , 0x1903600F, AXON1::iohs1_fure , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 206
2967- {"iohs1_ndl_fure" , 0x1903040F, AXON1::iohs1_ndl_fure , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 207
2968- {"iohs1_pdl_fure" , 0x1903020F, AXON1::iohs1_pdl_fure , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 208
2969- {"iohs1_pll_func" , 0x19030010, AXON1::iohs1_pll_func , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 209
2970- {"iohs2_fure" , 0x1A03600F, AXON2::iohs2_fure , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 210
2971- {"iohs2_ndl_fure" , 0x1A03040F, AXON2::iohs2_ndl_fure , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 211
2972- {"iohs2_pdl_fure" , 0x1A03020F, AXON2::iohs2_pdl_fure , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 212
2973- {"iohs2_pll_func" , 0x1A030010, AXON2::iohs2_pll_func , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 213
2974- {"iohs3_fure" , 0x1B03600F, AXON3::iohs3_fure , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 214
2975- {"iohs3_ndl_fure" , 0x1B03040F, AXON3::iohs3_ndl_fure , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 215
2976- {"iohs3_pdl_fure" , 0x1B03020F, AXON3::iohs3_pdl_fure , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 216
2977- {"iohs3_pll_func" , 0x1B030010, AXON3::iohs3_pll_func , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 217
2978- {"iohs4_fure" , 0x1C03600F, AXON4::iohs4_fure , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 218
2979- {"iohs4_ndl_fure" , 0x1C03040F, AXON4::iohs4_ndl_fure , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 219
2980- {"iohs4_pdl_fure" , 0x1C03020F, AXON4::iohs4_pdl_fure , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 220
2981- {"iohs4_pll_func" , 0x1C030010, AXON4::iohs4_pll_func , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 221
2982- {"iohs5_fure" , 0x1D03600F, AXON5::iohs5_fure , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 222
2983- {"iohs5_ndl_fure" , 0x1D03040F, AXON5::iohs5_ndl_fure , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 223
2984- {"iohs5_pdl_fure" , 0x1D03020F, AXON5::iohs5_pdl_fure , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 224
2985- {"iohs5_pll_func" , 0x1D030010, AXON5::iohs5_pll_func , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 225
2986- {"iohs6_fure" , 0x1E03600F, AXON6::iohs6_fure , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 226
2987- {"iohs6_ndl_fure" , 0x1E03040F, AXON6::iohs6_ndl_fure , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 227
2988- {"iohs6_pdl_fure" , 0x1E03020F, AXON6::iohs6_pdl_fure , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 228
2989- {"iohs6_pll_func" , 0x1E030010, AXON6::iohs6_pll_func , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 229
2990- {"iohs7_fure" , 0x1F03600F, AXON7::iohs7_fure , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 230
2991- {"iohs7_ndl_fure" , 0x1F03040F, AXON7::iohs7_ndl_fure , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 231
2992- {"iohs7_pdl_fure" , 0x1F03020F, AXON7::iohs7_pdl_fure , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 232
2993- {"iohs7_pll_func" , 0x1F030010, AXON7::iohs7_pll_func , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 233
2994- {"eq_fure" , 0x2003402F, EQ::eq_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 234
2995- {"eq_cmsk" , 0x2003402A, EQ::eq_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 235
2996- {"eq_inex" , 0x2003402B, EQ::eq_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 236
2997- {"eq_mode" , 0x20034021, EQ::eq_mode , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 237
2998- {"eq_clkadj_fure" , 0x2003001F, EQ::eq_clkadj_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 238
2999- {"eq_clkadj_cmsk" , 0x2003001A, EQ::eq_clkadj_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 239
3000- {"eq_clkadj_inex" , 0x2003001B, EQ::eq_clkadj_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 240
3001- {"eq_clkadj_mode" , 0x20030011, EQ::eq_clkadj_mode , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 241
3002- {"ec_cl2_fure" , 0x2003200F, EQ::ec_cl2_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 242
3003- {"ec_cl2_cmsk" , 0x2003200A, EQ::ec_cl2_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 243
3004- {"ec_cl2_inex" , 0x2003200B, EQ::ec_cl2_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 244
3005- {"ec_cl2_mode" , 0x20032001, EQ::ec_cl2_mode , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 245
3006- {"ec_mma_fure" , 0x2083000F, EQ::ec_mma_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 246
3007- {"ec_mma_cmsk" , 0x2083000A, EQ::ec_mma_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 247
3008- {"ec_mma_inex" , 0x2083000B, EQ::ec_mma_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 248
3009- {"ec_l3_fure" , 0x2003020F, EQ::ec_l3_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 249
3010- {"ec_l3_cmsk" , 0x2003020A, EQ::ec_l3_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 250
3011- {"ec_l3_inex" , 0x2003020B, EQ::ec_l3_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 251
3012- {"ec_l3_mode" , 0x20030201, EQ::ec_l3_mode , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 252
3013- {"n0_abst" , 0x02036405, N0::n0_abst , N0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 253
3014- {"n1_abst" , 0x03035405, N1::n1_abst , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 254
3015- {"n1_nmmu1_abst" , 0x03030205, N1::n1_nmmu1_abst , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 255
3016- {"ec_cl2_abst" , 0x20032005, EQ::ec_cl2_abst , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 256
3017- {"ec_mma_abst" , 0x20830005, EQ::ec_mma_abst , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 257
3018+ {perv_fure , "perv_fure" , 0x0103410F, PERV::perv_fure , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 256
3019+ {sbe_fure , "sbe_fure" , 0x0103200F, PERV::sbe_fure , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 257
3020+ {occ_fure , "occ_fure" , 0x0103080F, PERV::occ_fure , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 258
3021+ {perv_dpll_func , "perv_dpll_func" , 0x01030060, PERV::perv_dpll_func , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 259
3022+ {perv_dpll_bndy , "perv_dpll_bndy" , 0x01030068, PERV::perv_dpll_bndy , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 260
3023+ {perv_dpll_time , "perv_dpll_time" , 0x01030067, PERV::perv_dpll_time , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 261
3024+ {perv_pll_func , "perv_pll_func" , 0x01030010, PERV::perv_pll_func , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 262
3025+ {perv_pll_bndy , "perv_pll_bndy" , 0x01030018, PERV::perv_pll_bndy , PERV_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 263
3026+ {n0_fure , "n0_fure" , 0x0203640F, N0::n0_fure , N0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 264
3027+ {n1_fure , "n1_fure" , 0x0303540F, N1::n1_fure , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 265
3028+ {n1_nmmu1_fure , "n1_nmmu1_fure" , 0x0303020F, N1::n1_nmmu1_fure , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 266
3029+ {pci_fure , "pci_fure" , 0x08037F8F, PCI::pci_fure , PCI_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 267
3030+ {pci_pll_func , "pci_pll_func" , 0x08030010, PCI::pci_pll_func , PCI_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 268
3031+ {pci_pll_bndy , "pci_pll_bndy" , 0x08030018, PCI::pci_pll_bndy , PCI_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 269
3032+ {mc_fure , "mc_fure" , 0x0C036F0F, MC::mc_fure , MC_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 270
3033+ {mc_pll_func , "mc_pll_func" , 0x0C030010, MC::mc_pll_func , MC_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 271
3034+ {mc_pll_bndy , "mc_pll_bndy" , 0x0C030018, MC::mc_pll_bndy , MC_TYPE , RMRK_ROOT | RMRK_HAS_DERIVS | RCLS_EKB_RINGS }, // 272
3035+ {mc_pll_bndy_bucket_0 , "mc_pll_bndy_bucket_0" , 0x0C030018, MC::mc_pll_bndy_bucket_0 , MC_TYPE , RCLS_EKB_RINGS }, // 273
3036+ {mc_pll_bndy_bucket_1 , "mc_pll_bndy_bucket_1" , 0x0C030018, MC::mc_pll_bndy_bucket_1 , MC_TYPE , RCLS_EKB_RINGS }, // 274
3037+ {mc_pll_bndy_bucket_2 , "mc_pll_bndy_bucket_2" , 0x0C030018, MC::mc_pll_bndy_bucket_2 , MC_TYPE , RCLS_EKB_RINGS }, // 275
3038+ {mc_pll_bndy_bucket_3 , "mc_pll_bndy_bucket_3" , 0x0C030018, MC::mc_pll_bndy_bucket_3 , MC_TYPE , RCLS_EKB_RINGS }, // 276
3039+ {mc_pll_bndy_bucket_4 , "mc_pll_bndy_bucket_4" , 0x0C030018, MC::mc_pll_bndy_bucket_4 , MC_TYPE , RCLS_EKB_RINGS }, // 277
3040+ {pau0_fure , "pau0_fure" , 0x1003430F, PAU0::pau0_fure , PAU0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 278
3041+ {pau0_pau0_fure , "pau0_pau0_fure" , 0x1003200F, PAU0::pau0_pau0_fure , PAU0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 279
3042+ {pau1_fure , "pau1_fure" , 0x1103430F, PAU1::pau1_fure , PAU1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 280
3043+ {pau1_pau3_fure , "pau1_pau3_fure" , 0x1103200F, PAU1::pau1_pau3_fure , PAU1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 281
3044+ {pau2_fure , "pau2_fure" , 0x1203430F, PAU2::pau2_fure , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 282
3045+ {pau2_pau4_fure , "pau2_pau4_fure" , 0x1203200F, PAU2::pau2_pau4_fure , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 283
3046+ {pau2_pau5_fure , "pau2_pau5_fure" , 0x1203100F, PAU2::pau2_pau5_fure , PAU2_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 284
3047+ {pau3_fure , "pau3_fure" , 0x1303430F, PAU3::pau3_fure , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 285
3048+ {pau3_pau6_fure , "pau3_pau6_fure" , 0x1303200F, PAU3::pau3_pau6_fure , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 286
3049+ {pau3_pau7_fure , "pau3_pau7_fure" , 0x1303100F, PAU3::pau3_pau7_fure , PAU3_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 287
3050+ {iohs0_fure , "iohs0_fure" , 0x1803600F, AXON0::iohs0_fure , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 288
3051+ {iohs0_ndl_fure , "iohs0_ndl_fure" , 0x1803040F, AXON0::iohs0_ndl_fure , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 289
3052+ {iohs0_pdl_fure , "iohs0_pdl_fure" , 0x1803020F, AXON0::iohs0_pdl_fure , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 290
3053+ {iohs0_pll_func , "iohs0_pll_func" , 0x18030010, AXON0::iohs0_pll_func , AXON0_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 291
3054+ {iohs0_pll_bndy , "iohs0_pll_bndy" , 0x18030018, AXON0::iohs0_pll_bndy , AXON0_TYPE, RMRK_ROOT | RMRK_HAS_DERIVS | RCLS_EKB_RINGS }, // 292
3055+ {iohs0_pll_bndy_bucket_0, "iohs0_pll_bndy_bucket_0" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_0, AXON0_TYPE, RCLS_EKB_RINGS }, // 293
3056+ {iohs0_pll_bndy_bucket_1, "iohs0_pll_bndy_bucket_1" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_1, AXON0_TYPE, RCLS_EKB_RINGS }, // 294
3057+ {iohs0_pll_bndy_bucket_2, "iohs0_pll_bndy_bucket_2" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_2, AXON0_TYPE, RCLS_EKB_RINGS }, // 295
3058+ {iohs0_pll_bndy_bucket_3, "iohs0_pll_bndy_bucket_3" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_3, AXON0_TYPE, RCLS_EKB_RINGS }, // 296
3059+ {iohs0_pll_bndy_bucket_4, "iohs0_pll_bndy_bucket_4" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_4, AXON0_TYPE, RCLS_EKB_RINGS }, // 297
3060+ {iohs0_pll_bndy_bucket_5, "iohs0_pll_bndy_bucket_5" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_5, AXON0_TYPE, RCLS_EKB_RINGS }, // 298
3061+ {iohs0_pll_bndy_bucket_6, "iohs0_pll_bndy_bucket_6" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_6, AXON0_TYPE, RCLS_EKB_RINGS }, // 299
3062+ {iohs0_pll_bndy_bucket_7, "iohs0_pll_bndy_bucket_7" , 0x18030018, AXON0::iohs0_pll_bndy_bucket_7, AXON0_TYPE, RCLS_EKB_RINGS }, // 300
3063+ {iohs1_fure , "iohs1_fure" , 0x1903600F, AXON1::iohs1_fure , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 301
3064+ {iohs1_ndl_fure , "iohs1_ndl_fure" , 0x1903040F, AXON1::iohs1_ndl_fure , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 302
3065+ {iohs1_pdl_fure , "iohs1_pdl_fure" , 0x1903020F, AXON1::iohs1_pdl_fure , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 303
3066+ {iohs1_pll_func , "iohs1_pll_func" , 0x19030010, AXON1::iohs1_pll_func , AXON1_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 304
3067+ {iohs2_fure , "iohs2_fure" , 0x1A03600F, AXON2::iohs2_fure , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 305
3068+ {iohs2_ndl_fure , "iohs2_ndl_fure" , 0x1A03040F, AXON2::iohs2_ndl_fure , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 306
3069+ {iohs2_pdl_fure , "iohs2_pdl_fure" , 0x1A03020F, AXON2::iohs2_pdl_fure , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 307
3070+ {iohs2_pll_func , "iohs2_pll_func" , 0x1A030010, AXON2::iohs2_pll_func , AXON2_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 308
3071+ {iohs3_fure , "iohs3_fure" , 0x1B03600F, AXON3::iohs3_fure , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 309
3072+ {iohs3_ndl_fure , "iohs3_ndl_fure" , 0x1B03040F, AXON3::iohs3_ndl_fure , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 310
3073+ {iohs3_pdl_fure , "iohs3_pdl_fure" , 0x1B03020F, AXON3::iohs3_pdl_fure , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 311
3074+ {iohs3_pll_func , "iohs3_pll_func" , 0x1B030010, AXON3::iohs3_pll_func , AXON3_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 312
3075+ {iohs4_fure , "iohs4_fure" , 0x1C03600F, AXON4::iohs4_fure , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 313
3076+ {iohs4_ndl_fure , "iohs4_ndl_fure" , 0x1C03040F, AXON4::iohs4_ndl_fure , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 314
3077+ {iohs4_pdl_fure , "iohs4_pdl_fure" , 0x1C03020F, AXON4::iohs4_pdl_fure , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 315
3078+ {iohs4_pll_func , "iohs4_pll_func" , 0x1C030010, AXON4::iohs4_pll_func , AXON4_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 316
3079+ {iohs5_fure , "iohs5_fure" , 0x1D03600F, AXON5::iohs5_fure , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 317
3080+ {iohs5_ndl_fure , "iohs5_ndl_fure" , 0x1D03040F, AXON5::iohs5_ndl_fure , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 318
3081+ {iohs5_pdl_fure , "iohs5_pdl_fure" , 0x1D03020F, AXON5::iohs5_pdl_fure , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 319
3082+ {iohs5_pll_func , "iohs5_pll_func" , 0x1D030010, AXON5::iohs5_pll_func , AXON5_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 320
3083+ {iohs6_fure , "iohs6_fure" , 0x1E03600F, AXON6::iohs6_fure , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 321
3084+ {iohs6_ndl_fure , "iohs6_ndl_fure" , 0x1E03040F, AXON6::iohs6_ndl_fure , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 322
3085+ {iohs6_pdl_fure , "iohs6_pdl_fure" , 0x1E03020F, AXON6::iohs6_pdl_fure , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 323
3086+ {iohs6_pll_func , "iohs6_pll_func" , 0x1E030010, AXON6::iohs6_pll_func , AXON6_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 324
3087+ {iohs7_fure , "iohs7_fure" , 0x1F03600F, AXON7::iohs7_fure , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 325
3088+ {iohs7_ndl_fure , "iohs7_ndl_fure" , 0x1F03040F, AXON7::iohs7_ndl_fure , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 326
3089+ {iohs7_pdl_fure , "iohs7_pdl_fure" , 0x1F03020F, AXON7::iohs7_pdl_fure , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 327
3090+ {iohs7_pll_func , "iohs7_pll_func" , 0x1F030010, AXON7::iohs7_pll_func , AXON7_TYPE, RMRK_ROOT | RCLS_EKB_RINGS }, // 328
3091+ {eq_fure , "eq_fure" , 0x2003402F, EQ::eq_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 329
3092+ {eq_cmsk , "eq_cmsk" , 0x2003402A, EQ::eq_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 330
3093+ {eq_inex , "eq_inex" , 0x2003402B, EQ::eq_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 331
3094+ {eq_mode , "eq_mode" , 0x20034021, EQ::eq_mode , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 332
3095+ {eq_clkadj_fure , "eq_clkadj_fure" , 0x2003001F, EQ::eq_clkadj_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 333
3096+ {eq_clkadj_cmsk , "eq_clkadj_cmsk" , 0x2003001A, EQ::eq_clkadj_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 334
3097+ {eq_clkadj_inex , "eq_clkadj_inex" , 0x2003001B, EQ::eq_clkadj_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 335
3098+ {eq_clkadj_mode , "eq_clkadj_mode" , 0x20030011, EQ::eq_clkadj_mode , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 336
3099+ {ec_cl2_fure , "ec_cl2_fure" , 0x2003200F, EQ::ec_cl2_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 337
3100+ {ec_cl2_cmsk , "ec_cl2_cmsk" , 0x2003200A, EQ::ec_cl2_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 338
3101+ {ec_cl2_inex , "ec_cl2_inex" , 0x2003200B, EQ::ec_cl2_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 339
3102+ {ec_cl2_mode , "ec_cl2_mode" , 0x20032001, EQ::ec_cl2_mode , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 340
3103+ {ec_mma_fure , "ec_mma_fure" , 0x2083000F, EQ::ec_mma_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 341
3104+ {ec_mma_cmsk , "ec_mma_cmsk" , 0x2083000A, EQ::ec_mma_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 342
3105+ {ec_mma_inex , "ec_mma_inex" , 0x2083000B, EQ::ec_mma_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 343
3106+ {ec_l3_fure , "ec_l3_fure" , 0x2003020F, EQ::ec_l3_fure , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 344
3107+ {ec_l3_cmsk , "ec_l3_cmsk" , 0x2003020A, EQ::ec_l3_cmsk , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 345
3108+ {ec_l3_inex , "ec_l3_inex" , 0x2003020B, EQ::ec_l3_inex , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 346
3109+ {ec_l3_mode , "ec_l3_mode" , 0x20030201, EQ::ec_l3_mode , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS | RMRK_SCAN_BY_QME }, // 347
3110+ {n0_abst , "n0_abst" , 0x02036405, N0::n0_abst , N0_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 348
3111+ {n1_abst , "n1_abst" , 0x03035405, N1::n1_abst , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 349
3112+ {n1_nmmu1_abst , "n1_nmmu1_abst" , 0x03030205, N1::n1_nmmu1_abst , N1_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 350
3113+ {ec_cl2_abst , "ec_cl2_abst" , 0x20032005, EQ::ec_cl2_abst , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 351
3114+ {ec_mma_abst , "ec_mma_abst" , 0x20830005, EQ::ec_mma_abst , EQ_TYPE , RMRK_ROOT | RCLS_EKB_RINGS }, // 352
3115 };
3116 #endif
3117
3118@@ -1030,103 +1039,103 @@ static const RingProperties_t RING_PROPERTIES[NUM_RING_IDS] =
3119 {EQ::ec3_l3_repr , EQ_TYPE }, // 160
3120
3121 // EKB Rings:
3122- {PERV::perv_fure , PERV_TYPE }, // 161
3123- {PERV::sbe_fure , PERV_TYPE }, // 162
3124- {PERV::occ_fure , PERV_TYPE }, // 163
3125- {PERV::perv_dpll_func , PERV_TYPE }, // 164
3126- {PERV::perv_dpll_bndy , PERV_TYPE }, // 165
3127- {PERV::perv_dpll_time , PERV_TYPE }, // 166
3128- {PERV::perv_pll_func , PERV_TYPE }, // 167
3129- {PERV::perv_pll_bndy , PERV_TYPE }, // 168
3130- {N0::n0_fure , N0_TYPE }, // 169
3131- {N1::n1_fure , N1_TYPE }, // 170
3132- {N1::n1_nmmu1_fure , N1_TYPE }, // 171
3133- {PCI::pci_fure , PCI_TYPE }, // 172
3134- {PCI::pci_pll_func , PCI_TYPE }, // 173
3135- {PCI::pci_pll_bndy , PCI_TYPE }, // 174
3136- {MC::mc_fure , MC_TYPE }, // 175
3137- {MC::mc_pll_func , MC_TYPE }, // 176
3138- {MC::mc_pll_bndy , MC_TYPE }, // 177
3139- {MC::mc_pll_bndy_bucket_0 , MC_TYPE }, // 178
3140- {MC::mc_pll_bndy_bucket_1 , MC_TYPE }, // 179
3141- {MC::mc_pll_bndy_bucket_2 , MC_TYPE }, // 180
3142- {MC::mc_pll_bndy_bucket_3 , MC_TYPE }, // 181
3143- {MC::mc_pll_bndy_bucket_4 , MC_TYPE }, // 182
3144- {PAU0::pau0_fure , PAU0_TYPE }, // 183
3145- {PAU0::pau0_pau0_fure , PAU0_TYPE }, // 184
3146- {PAU1::pau1_fure , PAU1_TYPE }, // 185
3147- {PAU1::pau1_pau3_fure , PAU1_TYPE }, // 186
3148- {PAU2::pau2_fure , PAU2_TYPE }, // 187
3149- {PAU2::pau2_pau4_fure , PAU2_TYPE }, // 188
3150- {PAU2::pau2_pau5_fure , PAU2_TYPE }, // 189
3151- {PAU3::pau3_fure , PAU3_TYPE }, // 190
3152- {PAU3::pau3_pau6_fure , PAU3_TYPE }, // 191
3153- {PAU3::pau3_pau7_fure , PAU3_TYPE }, // 192
3154- {AXON0::iohs0_fure , AXON0_TYPE}, // 193
3155- {AXON0::iohs0_ndl_fure , AXON0_TYPE}, // 194
3156- {AXON0::iohs0_pdl_fure , AXON0_TYPE}, // 195
3157- {AXON0::iohs0_pll_func , AXON0_TYPE}, // 196
3158- {AXON0::iohs0_pll_bndy , AXON0_TYPE}, // 197
3159- {AXON0::iohs0_pll_bndy_bucket_0, AXON0_TYPE}, // 198
3160- {AXON0::iohs0_pll_bndy_bucket_1, AXON0_TYPE}, // 199
3161- {AXON0::iohs0_pll_bndy_bucket_2, AXON0_TYPE}, // 200
3162- {AXON0::iohs0_pll_bndy_bucket_3, AXON0_TYPE}, // 201
3163- {AXON0::iohs0_pll_bndy_bucket_4, AXON0_TYPE}, // 202
3164- {AXON0::iohs0_pll_bndy_bucket_5, AXON0_TYPE}, // 203
3165- {AXON0::iohs0_pll_bndy_bucket_6, AXON0_TYPE}, // 204
3166- {AXON0::iohs0_pll_bndy_bucket_7, AXON0_TYPE}, // 205
3167- {AXON1::iohs1_fure , AXON1_TYPE}, // 206
3168- {AXON1::iohs1_ndl_fure , AXON1_TYPE}, // 207
3169- {AXON1::iohs1_pdl_fure , AXON1_TYPE}, // 208
3170- {AXON1::iohs1_pll_func , AXON1_TYPE}, // 209
3171- {AXON2::iohs2_fure , AXON2_TYPE}, // 210
3172- {AXON2::iohs2_ndl_fure , AXON2_TYPE}, // 211
3173- {AXON2::iohs2_pdl_fure , AXON2_TYPE}, // 212
3174- {AXON2::iohs2_pll_func , AXON2_TYPE}, // 213
3175- {AXON3::iohs3_fure , AXON3_TYPE}, // 214
3176- {AXON3::iohs3_ndl_fure , AXON3_TYPE}, // 215
3177- {AXON3::iohs3_pdl_fure , AXON3_TYPE}, // 216
3178- {AXON3::iohs3_pll_func , AXON3_TYPE}, // 217
3179- {AXON4::iohs4_fure , AXON4_TYPE}, // 218
3180- {AXON4::iohs4_ndl_fure , AXON4_TYPE}, // 219
3181- {AXON4::iohs4_pdl_fure , AXON4_TYPE}, // 220
3182- {AXON4::iohs4_pll_func , AXON4_TYPE}, // 221
3183- {AXON5::iohs5_fure , AXON5_TYPE}, // 222
3184- {AXON5::iohs5_ndl_fure , AXON5_TYPE}, // 223
3185- {AXON5::iohs5_pdl_fure , AXON5_TYPE}, // 224
3186- {AXON5::iohs5_pll_func , AXON5_TYPE}, // 225
3187- {AXON6::iohs6_fure , AXON6_TYPE}, // 226
3188- {AXON6::iohs6_ndl_fure , AXON6_TYPE}, // 227
3189- {AXON6::iohs6_pdl_fure , AXON6_TYPE}, // 228
3190- {AXON6::iohs6_pll_func , AXON6_TYPE}, // 229
3191- {AXON7::iohs7_fure , AXON7_TYPE}, // 230
3192- {AXON7::iohs7_ndl_fure , AXON7_TYPE}, // 231
3193- {AXON7::iohs7_pdl_fure , AXON7_TYPE}, // 232
3194- {AXON7::iohs7_pll_func , AXON7_TYPE}, // 233
3195- {EQ::eq_fure , EQ_TYPE }, // 234
3196- {EQ::eq_cmsk , EQ_TYPE }, // 235
3197- {EQ::eq_inex , EQ_TYPE }, // 236
3198- {EQ::eq_mode , EQ_TYPE }, // 237
3199- {EQ::eq_clkadj_fure , EQ_TYPE }, // 238
3200- {EQ::eq_clkadj_cmsk , EQ_TYPE }, // 239
3201- {EQ::eq_clkadj_inex , EQ_TYPE }, // 240
3202- {EQ::eq_clkadj_mode , EQ_TYPE }, // 241
3203- {EQ::ec_cl2_fure , EQ_TYPE }, // 242
3204- {EQ::ec_cl2_cmsk , EQ_TYPE }, // 243
3205- {EQ::ec_cl2_inex , EQ_TYPE }, // 244
3206- {EQ::ec_cl2_mode , EQ_TYPE }, // 245
3207- {EQ::ec_mma_fure , EQ_TYPE }, // 246
3208- {EQ::ec_mma_cmsk , EQ_TYPE }, // 247
3209- {EQ::ec_mma_inex , EQ_TYPE }, // 248
3210- {EQ::ec_l3_fure , EQ_TYPE }, // 249
3211- {EQ::ec_l3_cmsk , EQ_TYPE }, // 250
3212- {EQ::ec_l3_inex , EQ_TYPE }, // 251
3213- {EQ::ec_l3_mode , EQ_TYPE }, // 252
3214- {N0::n0_abst , N0_TYPE }, // 253
3215- {N1::n1_abst , N1_TYPE }, // 254
3216- {N1::n1_nmmu1_abst , N1_TYPE }, // 255
3217- {EQ::ec_cl2_abst , EQ_TYPE }, // 256
3218- {EQ::ec_mma_abst , EQ_TYPE }, // 257
3219+ {PERV::perv_fure , PERV_TYPE }, // 256
3220+ {PERV::sbe_fure , PERV_TYPE }, // 257
3221+ {PERV::occ_fure , PERV_TYPE }, // 258
3222+ {PERV::perv_dpll_func , PERV_TYPE }, // 259
3223+ {PERV::perv_dpll_bndy , PERV_TYPE }, // 260
3224+ {PERV::perv_dpll_time , PERV_TYPE }, // 261
3225+ {PERV::perv_pll_func , PERV_TYPE }, // 262
3226+ {PERV::perv_pll_bndy , PERV_TYPE }, // 263
3227+ {N0::n0_fure , N0_TYPE }, // 264
3228+ {N1::n1_fure , N1_TYPE }, // 265
3229+ {N1::n1_nmmu1_fure , N1_TYPE }, // 266
3230+ {PCI::pci_fure , PCI_TYPE }, // 267
3231+ {PCI::pci_pll_func , PCI_TYPE }, // 268
3232+ {PCI::pci_pll_bndy , PCI_TYPE }, // 269
3233+ {MC::mc_fure , MC_TYPE }, // 270
3234+ {MC::mc_pll_func , MC_TYPE }, // 271
3235+ {MC::mc_pll_bndy , MC_TYPE }, // 272
3236+ {MC::mc_pll_bndy_bucket_0 , MC_TYPE }, // 273
3237+ {MC::mc_pll_bndy_bucket_1 , MC_TYPE }, // 274
3238+ {MC::mc_pll_bndy_bucket_2 , MC_TYPE }, // 275
3239+ {MC::mc_pll_bndy_bucket_3 , MC_TYPE }, // 276
3240+ {MC::mc_pll_bndy_bucket_4 , MC_TYPE }, // 277
3241+ {PAU0::pau0_fure , PAU0_TYPE }, // 278
3242+ {PAU0::pau0_pau0_fure , PAU0_TYPE }, // 279
3243+ {PAU1::pau1_fure , PAU1_TYPE }, // 280
3244+ {PAU1::pau1_pau3_fure , PAU1_TYPE }, // 281
3245+ {PAU2::pau2_fure , PAU2_TYPE }, // 282
3246+ {PAU2::pau2_pau4_fure , PAU2_TYPE }, // 283
3247+ {PAU2::pau2_pau5_fure , PAU2_TYPE }, // 284
3248+ {PAU3::pau3_fure , PAU3_TYPE }, // 285
3249+ {PAU3::pau3_pau6_fure , PAU3_TYPE }, // 286
3250+ {PAU3::pau3_pau7_fure , PAU3_TYPE }, // 287
3251+ {AXON0::iohs0_fure , AXON0_TYPE}, // 288
3252+ {AXON0::iohs0_ndl_fure , AXON0_TYPE}, // 289
3253+ {AXON0::iohs0_pdl_fure , AXON0_TYPE}, // 290
3254+ {AXON0::iohs0_pll_func , AXON0_TYPE}, // 291
3255+ {AXON0::iohs0_pll_bndy , AXON0_TYPE}, // 292
3256+ {AXON0::iohs0_pll_bndy_bucket_0, AXON0_TYPE}, // 293
3257+ {AXON0::iohs0_pll_bndy_bucket_1, AXON0_TYPE}, // 294
3258+ {AXON0::iohs0_pll_bndy_bucket_2, AXON0_TYPE}, // 295
3259+ {AXON0::iohs0_pll_bndy_bucket_3, AXON0_TYPE}, // 296
3260+ {AXON0::iohs0_pll_bndy_bucket_4, AXON0_TYPE}, // 297
3261+ {AXON0::iohs0_pll_bndy_bucket_5, AXON0_TYPE}, // 298
3262+ {AXON0::iohs0_pll_bndy_bucket_6, AXON0_TYPE}, // 299
3263+ {AXON0::iohs0_pll_bndy_bucket_7, AXON0_TYPE}, // 300
3264+ {AXON1::iohs1_fure , AXON1_TYPE}, // 301
3265+ {AXON1::iohs1_ndl_fure , AXON1_TYPE}, // 302
3266+ {AXON1::iohs1_pdl_fure , AXON1_TYPE}, // 303
3267+ {AXON1::iohs1_pll_func , AXON1_TYPE}, // 304
3268+ {AXON2::iohs2_fure , AXON2_TYPE}, // 305
3269+ {AXON2::iohs2_ndl_fure , AXON2_TYPE}, // 306
3270+ {AXON2::iohs2_pdl_fure , AXON2_TYPE}, // 307
3271+ {AXON2::iohs2_pll_func , AXON2_TYPE}, // 308
3272+ {AXON3::iohs3_fure , AXON3_TYPE}, // 309
3273+ {AXON3::iohs3_ndl_fure , AXON3_TYPE}, // 310
3274+ {AXON3::iohs3_pdl_fure , AXON3_TYPE}, // 311
3275+ {AXON3::iohs3_pll_func , AXON3_TYPE}, // 312
3276+ {AXON4::iohs4_fure , AXON4_TYPE}, // 313
3277+ {AXON4::iohs4_ndl_fure , AXON4_TYPE}, // 314
3278+ {AXON4::iohs4_pdl_fure , AXON4_TYPE}, // 315
3279+ {AXON4::iohs4_pll_func , AXON4_TYPE}, // 316
3280+ {AXON5::iohs5_fure , AXON5_TYPE}, // 317
3281+ {AXON5::iohs5_ndl_fure , AXON5_TYPE}, // 318
3282+ {AXON5::iohs5_pdl_fure , AXON5_TYPE}, // 319
3283+ {AXON5::iohs5_pll_func , AXON5_TYPE}, // 320
3284+ {AXON6::iohs6_fure , AXON6_TYPE}, // 321
3285+ {AXON6::iohs6_ndl_fure , AXON6_TYPE}, // 322
3286+ {AXON6::iohs6_pdl_fure , AXON6_TYPE}, // 323
3287+ {AXON6::iohs6_pll_func , AXON6_TYPE}, // 324
3288+ {AXON7::iohs7_fure , AXON7_TYPE}, // 325
3289+ {AXON7::iohs7_ndl_fure , AXON7_TYPE}, // 326
3290+ {AXON7::iohs7_pdl_fure , AXON7_TYPE}, // 327
3291+ {AXON7::iohs7_pll_func , AXON7_TYPE}, // 328
3292+ {EQ::eq_fure , EQ_TYPE }, // 329
3293+ {EQ::eq_cmsk , EQ_TYPE }, // 330
3294+ {EQ::eq_inex , EQ_TYPE }, // 331
3295+ {EQ::eq_mode , EQ_TYPE }, // 332
3296+ {EQ::eq_clkadj_fure , EQ_TYPE }, // 333
3297+ {EQ::eq_clkadj_cmsk , EQ_TYPE }, // 334
3298+ {EQ::eq_clkadj_inex , EQ_TYPE }, // 335
3299+ {EQ::eq_clkadj_mode , EQ_TYPE }, // 336
3300+ {EQ::ec_cl2_fure , EQ_TYPE }, // 337
3301+ {EQ::ec_cl2_cmsk , EQ_TYPE }, // 338
3302+ {EQ::ec_cl2_inex , EQ_TYPE }, // 339
3303+ {EQ::ec_cl2_mode , EQ_TYPE }, // 340
3304+ {EQ::ec_mma_fure , EQ_TYPE }, // 341
3305+ {EQ::ec_mma_cmsk , EQ_TYPE }, // 342
3306+ {EQ::ec_mma_inex , EQ_TYPE }, // 343
3307+ {EQ::ec_l3_fure , EQ_TYPE }, // 344
3308+ {EQ::ec_l3_cmsk , EQ_TYPE }, // 345
3309+ {EQ::ec_l3_inex , EQ_TYPE }, // 346
3310+ {EQ::ec_l3_mode , EQ_TYPE }, // 347
3311+ {N0::n0_abst , N0_TYPE }, // 348
3312+ {N1::n1_abst , N1_TYPE }, // 349
3313+ {N1::n1_nmmu1_abst , N1_TYPE }, // 350
3314+ {EQ::ec_cl2_abst , EQ_TYPE }, // 351
3315+ {EQ::ec_mma_abst , EQ_TYPE }, // 352
3316 };
3317 #endif // __PPE__
3318
3319diff --git a/src/import/chips/p10/utils/imageProcs/p10_tor.C b/src/import/chips/p10/utils/imageProcs/p10_tor.C
3320index 2a5009a..c89c707 100644
3321--- a/src/import/chips/p10/utils/imageProcs/p10_tor.C
3322+++ b/src/import/chips/p10/utils/imageProcs/p10_tor.C
3323@@ -60,6 +60,7 @@ int _tor_access_ring( void* io_ringSection, // Ring section ptr
3324 TorOffset_t ringOffset16; // Offset to actual ring container (for PUT operation)
3325 uint32_t torSlotNum; // TOR slot number (within a chiplet section)
3326 uint32_t rs4Size; // Size of RS4 ring container/block.
3327+ RingId_t rpIndex = UNDEFINED_RING_ID;
3328 RingId_t numRings;
3329 ChipletType_t chipletType = UNDEFINED_CHIPLET_TYPE;
3330 ChipletType_t chipletIndex = UNDEFINED_CHIPLET_TYPE; // Effective chiplet index
3331@@ -85,7 +86,13 @@ int _tor_access_ring( void* io_ringSection, // Ring section ptr
3332 return rc;
3333 }
3334
3335- chipletType = ringProps[i_ringId].chipletType;
3336+ // Get the ring properties (rp) index
3337+ rpIndex = ringid_convert_ringId_to_rpIndex(i_ringId);
3338+
3339+ // Note: Prior to entering _tor_access_ring(), we must call _tor_header_check()
3340+ // which also verifies valid ringId. So no need to check ringId again.
3341+
3342+ chipletType = ringProps[rpIndex].chipletType;
3343
3344 //
3345 // Get all other metadata for the chipletType
3346@@ -131,7 +138,7 @@ int _tor_access_ring( void* io_ringSection, // Ring section ptr
3347 //
3348 // Determine whether Common or Instance section based on the INSTANCE_RING_MARK
3349 //
3350- if ( ringProps[i_ringId].idxRing & INSTANCE_RING_MARK )
3351+ if ( ringProps[rpIndex].idxRing & INSTANCE_RING_MARK )
3352 {
3353 bInstCase = 1;
3354 }
3355@@ -144,7 +151,7 @@ int _tor_access_ring( void* io_ringSection, // Ring section ptr
3356 chipletData->numInstanceRings :
3357 chipletData->numCommonRings;
3358
3359- idxRingEff = ringProps[i_ringId].idxRing & INSTANCE_RING_MASK; // Always safe
3360+ idxRingEff = ringProps[rpIndex].idxRing & INSTANCE_RING_MASK; // Always safe
3361
3362 //
3363 // Check that chipletId is within chiplet's range (Note that we care only about Instance
3364@@ -371,18 +378,15 @@ int _tor_header_and_ring_check( void* i_ringSection, // Ring section
3365
3366 if ( rc != TOR_SUCCESS )
3367 {
3368- if ( rc == TOR_HOLE_RING_ID )
3369- {
3370- // "hole" ring. Not an error. No info to retrieve.
3371- return rc;
3372- }
3373- else if ( rc == TOR_INVALID_RING_ID || rc == TOR_INVALID_CHIP_ID )
3374+ // Only trace out what we know could be an error.
3375+ if ( rc == TOR_INVALID_CHIP_ID )
3376 {
3377- MY_ERR("ERROR: TOR ringId check: ringid_check_ringId() failed w/rc=0x%08x\n"
3378- " So either invalid ringId(=0x%x) or invalid chipId(=0x%x)\n",
3379- rc, i_ringId, torHeader->chipId);
3380- return rc;
3381+ MY_ERR("ERROR: TOR ringId check: ringid_check_ringId() failed w/rc=0x%08x"
3382+ " which is an invalid chipId(=0x%x)\n",
3383+ rc, torHeader->chipId);
3384 }
3385+
3386+ return rc;
3387 }
3388
3389 // Check TOR header
3390@@ -438,12 +442,18 @@ int tor_get_single_ring ( void* i_ringSection, // Ring section ptr
3391 i_dbgl );
3392
3393 // Explanation to the "list" of RCs that we exclude from tracing out:
3394- // TOR_HOLE_RING_ID: Normal scenario when rings are removed from the ring list
3395- if ( rc &&
3396- rc != TOR_HOLE_RING_ID )
3397+ // TOR_HOLE_RING_ID: Can happen if a ring has been removed from the ring list
3398+ // TOR_INVALID_RING_ID: CAn happen if caller carelessly cycles through ringIds
3399+ if ( rc )
3400 {
3401- MY_ERR("ERROR: tor_get_single_ring(): _tor_header_and_ring_check() failed w/rc=0x%08x\n",
3402- rc);
3403+ if ( rc != TOR_HOLE_RING_ID &&
3404+ rc != TOR_INVALID_RING_ID )
3405+ {
3406+ MY_ERR("ERROR: tor_get_single_ring: _tor_header_and_ring_check() failed"
3407+ " w/rc=0x%08x\n",
3408+ rc);
3409+ }
3410+
3411 return rc;
3412 }
3413
3414@@ -458,8 +468,6 @@ int tor_get_single_ring ( void* i_ringSection, // Ring section ptr
3415
3416 // Explanation to the "list" of RCs that we exclude from tracing out:
3417 // TOR_RING_IS_EMPTY: Normal scenario (will occur frequently).
3418- // TOR_HOLE_RING_ID: Normal scenario when rings are removed from the ring list
3419- // and leaves behind a "hole".
3420 // TOR_RING_HAS_NO_TOR_SLOT: Will be caused a lot by ipl_image_tool, but is an error if
3421 // called by any other user.
3422 // TOR_INVALID_CHIPLET_ID: Not necessarily an error as a user may be sweeping through a
3423@@ -472,13 +480,12 @@ int tor_get_single_ring ( void* i_ringSection, // Ring section ptr
3424 // in both ipl_image_tool and ipl_customize (RT_QME phase).
3425 if ( rc &&
3426 rc != TOR_RING_IS_EMPTY &&
3427- rc != TOR_HOLE_RING_ID &&
3428 rc != TOR_RING_HAS_NO_TOR_SLOT &&
3429 rc != TOR_INVALID_CHIPLET_ID &&
3430 rc != TOR_INVALID_CHIPLET_TYPE )
3431 {
3432- MY_ERR("ERROR: tor_get_single_ring(): _tor_access_ring() failed w/rc=0x%08x\n", rc);
3433-
3434+ MY_ERR("ERROR: tor_get_single_ring: _tor_access_ring() failed w/rc=0x%08x\n",
3435+ rc);
3436 return rc;
3437 }
3438
3439@@ -507,7 +514,7 @@ int tor_append_ring( void* io_ringSection, // Ring section ptr
3440
3441 if (rc)
3442 {
3443- MY_ERR("ERROR: tor_append_ring(): _tor_header_and_ring_check() failed w/rc=0x%08x\n",
3444+ MY_ERR("ERROR: tor_append_ring: _tor_header_and_ring_check() failed w/rc=0x%08x\n",
3445 rc);
3446 return rc;
3447 }
3448@@ -539,7 +546,7 @@ int tor_append_ring( void* io_ringSection, // Ring section ptr
3449 if ( rc &&
3450 rc != TOR_INVALID_CHIPLET_TYPE )
3451 {
3452- MY_ERR("ERROR: tor_append_ring(): _tor_access_ring() failed w/rc=0x%08x for"
3453+ MY_ERR("ERROR: tor_append_ring: _tor_access_ring() failed w/rc=0x%08x for"
3454 " ringId=0x%x\n",
3455 rc, i_ringId);
3456 return rc;
3457@@ -768,19 +775,15 @@ int dyn_get_ring( void* i_ringSection,
3458
3459 if ( rc != TOR_SUCCESS )
3460 {
3461- if ( rc == TOR_HOLE_RING_ID )
3462+ // Only trace out what we know could be an error.
3463+ if ( rc == TOR_INVALID_CHIP_ID )
3464 {
3465- // "hole" ring. Not an error. No info to retrieve.
3466- return rc;
3467+ MY_ERR("ERROR: dyn_get_ring: ringid_check_ringId() failed w/rc=0x%08x"
3468+ " which is an invalid chipId(=0x%x)\n",
3469+ rc, torHeader->chipId);
3470 }
3471- else if ( rc == TOR_INVALID_RING_ID || rc == TOR_INVALID_CHIP_ID )
3472- {
3473- MY_ERR("ERROR: dyn_get_ring(): ringid_check_ringId() failed w/rc=0x%08x\n"
3474- " So either invalid ringId(=0x%x) or invalid chipId(=0x%x)\n",
3475- rc, i_ringId, torHeader->chipId);
3476
3477- return rc;
3478- }
3479+ return rc;
3480 }
3481
3482 // TOR header check
3483@@ -791,7 +794,7 @@ int dyn_get_ring( void* i_ringSection,
3484 torHeader->ddLevel != i_ddLevel ||
3485 torHeader->rtVersion != RING_TABLE_VERSION_HWIMG )
3486 {
3487- MY_ERR("ERROR: dyn_get_ring(): TOR header check failed as follows:\n"
3488+ MY_ERR("ERROR: dyn_get_ring: TOR header check failed as follows:\n"
3489 " torHeader->magic(=0x%08x) != TOR_MAGIC_DYN(=0x%08x)\n"
3490 " torHeader->version(=%u) != TOR_VERSION(=%u)\n"
3491 " torHeader->ddLevel(=0x%02x) != i_ddLevel(=0x%02x)\n"
3492--
34931.8.2.2
3494