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37 <div class="section" id="release-notes-for-openpower-firmware-v2-0-5">
38<h1>Release Notes for OpenPower Firmware v2.0.5<a class="headerlink" href="#release-notes-for-openpower-firmware-v2-0-5" title="Permalink to this headline"></a></h1>
39<p>op-build v2.0.5 was released on Thursday July 19th, 2018 and replaces op-build v2.0.4 as the current stable release in the 2.0.x series.</p>
40<p>It is recommended that v2.0.4 be used over any previous v2.0.x version due to the bug fixes contained within.</p>
41<div class="section" id="updated-packages">
42<h2>Updated Packages<a class="headerlink" href="#updated-packages" title="Permalink to this headline"></a></h2>
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54<th class="head">Platforms</th>
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58<tr class="row-even"><td>skiboot</td>
59<td>v6.0.5</td>
60<td>v6.0.6</td>
61<td>openpower_mambo, firestone, firenze, garrison,
62zaius, p9dsu, palmetto, pseries, vesnin,
63witherspoon, habanero, openpower_p9_mambo, zz,
64barreleye, romulus</td>
65</tr>
66</tbody>
67</table>
68</div>
69<div class="section" id="skiboot-changes">
70<h2>Skiboot changes<a class="headerlink" href="#skiboot-changes" title="Permalink to this headline"></a></h2>
71<ul>
72<li><p class="first">phb4/CAPI: Reallocate PEC2 DMA-Read engines to improve GPU-Direct bandwidth</p>
73<p>We reallocate additional 16/8 DMA-Read engines allocated to stack0/1
74on PEC2 respectively. This is needed to improve bandwidth available to
75the Mellanox CX5 adapter when trying to read GPU memory (GPU-Direct).</p>
76<p>If kernel cxl driver indicates a request to allocate maximum possible
77DMA read engines when calling enable_capi_mode() and card is attached
78to PEC2/stack0 slot then we assume its a Mellanox CX5 adapter. We then
79allocate additional 16/8 extra DMA read engines to stack0 and stack1
80respectively on PEC2. This is done by populating the
81XPEC_PCI_PRDSTKOVR and XPEC_NEST_READ_STACK_OVERRIDE as suggested by
82the h/w team.</p>
83</li>
84<li><p class="first">phb4: Disable nodal scoped DMA accesses when PB pump mode is enabled</p>
85<p>By default when a PCIe device issues a read request via the PHB it is first
86issued with nodal scope. When accessing GPU memory the NPU does not know at the
87time of response if the requested memory page is off node or not. Therefore
88every read of GPU memory by a PHB is retried with larger scope which introduces
89bandwidth and latency issues.</p>
90<p>On smaller boxes which have pump mode enabled nodal and group scoped reads are
91treated the same and both types of request are broadcast to one chip. Therefore
92we can avoid the retry by disabling nodal scope on the PHB for these boxes. On
93larger boxes nodal (single chip) and group (multiple chip) scoped reads are
94treated differently. Therefore we avoid disabling nodal scope on large boxes
95which have pump mode disabled to avoid all PHB requests being broadcast to
96multiple chips.</p>
97</li>
98<li><p class="first">npu2/hw-procedures: Enable parity and credit overflow checks</p>
99<p>Enable these error checking features by setting the appropriate bits in
100our one-off initialization of each “NTL Misc Config 2” register.</p>
101<p>The exception is NDL RX parity checking, which should be disabled during
102the link training procedures.</p>
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