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38<h1>Release Notes for OpenPower Firmware v2.0.9<a class="headerlink" href="#release-notes-for-openpower-firmware-v2-0-9" title="Permalink to this headline"></a></h1>
39<p>op-build v2.0.9 was released on Thursday August 16th, 2018 and replaces op-build v2.0.8 as the current stable release in
40the 2.0.x series.</p>
41<p>It is recommended that v2.0.9 be used over any previous v2.0.x version on POWER9 systems due to the bug fixes contained within.</p>
42<p>The only update in this release is to skiboot. Skiboot v6.0.8 includes the following bug fixes:</p>
43<ul>
44<li><p class="first">i2c: Ensure ordering between i2c_request_send() and completion</p>
45<p>i2c_request_send loops waiting for a flag “uc.done” set by
46the completion routine, and then look for a result code
47also set by that same completion.</p>
48<p>There is no synchronization, the completion can happen on another
49processor, so we need to order the stores to uc and the reads
50from uc so that uc.done is stored last and tested first using
51memory barriers.</p>
52</li>
53<li><p class="first">i2c: Fix multiple-enqueue of the same request on NACK</p>
54<p>i2c_request_send() will retry the request if the error is a NAK,
55however it forgets to clear the “ud.done” flag. It will thus
56loop again and try to re-enqueue the same request causing internal
57request list corruption.</p>
58</li>
59<li><p class="first">phb4: Disable 32-bit MSI in capi mode</p>
60<p>If a capi device does a DMA write targeting an address lower than 4GB,
61it does so through a 32-bit operation, per the PCI spec. In capi mode,
62the first TVE entry is configured in bypass mode, so the address is
63valid. But with any (bad) luck, the address could be 0xFFFFxxxx, thus
64looking like a 32-bit MSI.</p>
65<p>We currently enable both 32-bit and 64-bit MSIs, so the PHB will
66interpret the DMA write as a MSI, which very likely results in an EEH
67(MSI with a bad payload size).</p>
68<p>We can fix it by disabling 32-bit MSI when switching the PHB to capi
69mode. Capi devices are 64-bit.</p>
70</li>
71<li><p class="first">capp: Fix the capp recovery timeout comparison</p>
72<p>The current capp recovery timeout control loop in
73do_capp_recovery_scoms() uses a wrong comparison for return value of
74tb_compare(). This may cause do_capp_recovery_scoms() to report an
75timeout earlier than the 168ms stipulated time.</p>
76<p>The patch fixes this by updating the loop timeout control branch in
77do_capp_recovery_scoms() to use the correct enum tb_cmpval.</p>
78</li>
79<li><p class="first">phb4/capp: Update DMA read engines set in APC_FSM_READ_MASK based on link-width</p>
80<p>Commit 47c09cdfe7a3(“phb4/capp: Calculate STQ/DMA read engines based
81on link-width for PEC”) update the CAPP init sequence by calculating
82the needed STQ/DMA-read engines based on link width and populating it
83in XPEC_NEST_CAPP_CNTL register. This however needs to be synchronized
84with the value set in CAPP APC FSM Read Machine Mask Register.</p>
85<p>Hence this patch update phb4_init_capp_regs() to calculate the link
86width of the stack on PEC2 and populate the same values as previously
87populated in PEC CAPP_CNTL register.</p>
88</li>
89<li><p class="first">core/cpu: Call memset with proper cpu_thread offset</p>
90</li>
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