| Brad Bishop | 286d45c | 2018-10-02 15:21:57 -0400 | [diff] [blame^] | 1 | From 646fe1dbaca06f2fe2df4c0da3fa20e0aff0a4ec Mon Sep 17 00:00:00 2001 |
| 2 | From: Nagaraju Mekala <nagaraju.mekala@xilinx.com> |
| 3 | Date: Sat, 26 Aug 2017 19:21:56 -0700 |
| 4 | Subject: [PATCH] MicroBlaze remove bitfield instructions macros |
| 5 | |
| 6 | Remove the conditions in the bit field expand macros to generate the |
| 7 | instructions in structure bit-field usecases |
| 8 | |
| 9 | ChangeLog: |
| 10 | |
| 11 | 2018-08-16 Nagaraju Mekala <nagaraju.mekala@xilinx.com> |
| 12 | |
| 13 | * gcc/config/microblaze/microblaze.md: |
| 14 | remove the expand constraints |
| 15 | |
| 16 | Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> |
| 17 | Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> |
| 18 | Upstream-Status: Pending |
| 19 | --- |
| 20 | gcc/config/microblaze/microblaze.md | 40 +++++-------------------------------- |
| 21 | 1 file changed, 5 insertions(+), 35 deletions(-) |
| 22 | |
| 23 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
| 24 | index 68c3b22bd4..ef53c3069e 100644 |
| 25 | --- a/gcc/config/microblaze/microblaze.md |
| 26 | +++ b/gcc/config/microblaze/microblaze.md |
| 27 | @@ -2482,25 +2482,8 @@ |
| 28 | (match_operand:SI 2 "immediate_operand" "I") |
| 29 | (match_operand:SI 3 "immediate_operand" "I")))] |
| 30 | "TARGET_HAS_BITFIELD" |
| 31 | -" |
| 32 | -{ |
| 33 | - unsigned HOST_WIDE_INT len = UINTVAL (operands[2]); |
| 34 | - unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]); |
| 35 | - |
| 36 | - if ((len == 0) || (pos + len > 32) ) |
| 37 | - FAIL; |
| 38 | - |
| 39 | - ;;if (!register_operand (operands[1], VOIDmode)) |
| 40 | - ;; FAIL; |
| 41 | - if (operands[0] == operands[1]) |
| 42 | - FAIL; |
| 43 | - if (GET_CODE (operands[1]) == ASHIFT) |
| 44 | - FAIL; |
| 45 | -;; operands[2] = GEN_INT(INTVAL(operands[2])+1 ); |
| 46 | - emit_insn (gen_extv_32 (operands[0], operands[1], |
| 47 | - operands[2], operands[3])); |
| 48 | - DONE; |
| 49 | -}") |
| 50 | +"" |
| 51 | +) |
| 52 | |
| 53 | (define_insn "extv_32" |
| 54 | [(set (match_operand:SI 0 "register_operand" "=r") |
| 55 | @@ -2518,22 +2501,9 @@ |
| 56 | (match_operand:SI 1 "immediate_operand" "I") |
| 57 | (match_operand:SI 2 "immediate_operand" "I")) |
| 58 | (match_operand:SI 3 "register_operand" "r"))] |
| 59 | - "TARGET_HAS_BITFIELD" |
| 60 | - " |
| 61 | -{ |
| 62 | - unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); |
| 63 | - unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); |
| 64 | - |
| 65 | - if (len <= 0 || pos + len > 32) |
| 66 | - FAIL; |
| 67 | - |
| 68 | - ;;if (!register_operand (operands[0], VOIDmode)) |
| 69 | - ;; FAIL; |
| 70 | - |
| 71 | - emit_insn (gen_insv_32 (operands[0], operands[1], |
| 72 | - operands[2], operands[3])); |
| 73 | - DONE; |
| 74 | -}") |
| 75 | +"TARGET_HAS_BITFIELD" |
| 76 | +"" |
| 77 | +) |
| 78 | |
| 79 | (define_insn "insv_32" |
| 80 | [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") |
| 81 | -- |
| 82 | 2.14.2 |
| 83 | |