| Brad Bishop | 286d45c | 2018-10-02 15:21:57 -0400 | [diff] [blame] | 1 | From 732b5a44a0a032da5ebb775b5df2ee2a36af988f Mon Sep 17 00:00:00 2001 |
| 2 | From: Nathan Rossi <nathan@nathanrossi.com> |
| 3 | Date: Sun, 5 Nov 2017 22:17:39 +1000 |
| 4 | Subject: [PATCH] MicroBlaze fix mask for barrel shift instructions |
| 5 | |
| 6 | As of v10.0 the bsi (bslli/bsrai/bsrli/bsefi/bsifi) instructions have |
| 7 | bits 16 and 17 defined as 'Insert' and 'Extract' respectively to support |
| 8 | bit field insert/extract operations. For the bslli/bsrai/bsrli |
| 9 | instructions these bits must be 0, as such update the opcode mask so |
| 10 | that the bslli/bsrai/bsrli instructions do not also match the bsefi and |
| 11 | bsifi instructions. |
| 12 | |
| 13 | Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> |
| 14 | Upstream-Status: Pending |
| 15 | |
| 16 | --- |
| 17 | opcodes/microblaze-opc.h | 6 +++--- |
| 18 | 1 file changed, 3 insertions(+), 3 deletions(-) |
| 19 | |
| 20 | diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h |
| 21 | index 4bc400a..9482d81 100644 |
| 22 | --- a/opcodes/microblaze-opc.h |
| 23 | +++ b/opcodes/microblaze-opc.h |
| 24 | @@ -161,9 +161,9 @@ struct op_code_struct |
| 25 | {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst }, |
| 26 | {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst }, |
| 27 | {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst }, |
| 28 | - {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst }, |
| 29 | - {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst }, |
| 30 | - {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst }, |
| 31 | + {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst }, |
| 32 | + {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst }, |
| 33 | + {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst }, |
| 34 | {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst }, |
| 35 | {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst }, |
| 36 | {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst }, |