blob: 1d877be6870188c611270e8de3b87f9c48217153 [file] [log] [blame]
Brad Bishop286d45c2018-10-02 15:21:57 -04001From 0c740ddd203433ef8d979348c085269f8b97cbfc Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:50 -0700
4Subject: [PATCH] MicroBlaze fixing the bug in the bit-field instruction.
5
6Bit field instruction should be generated only if mcpu >10.0
7
8Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
9Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
10Upstream-Status: Pending
11---
12 gcc/config/microblaze/microblaze.c | 3 +++
13 gcc/config/microblaze/microblaze.h | 2 ++
14 2 files changed, 5 insertions(+)
15
16diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
17index 55dba83882..4f6d399bba 100644
18--- a/gcc/config/microblaze/microblaze.c
19+++ b/gcc/config/microblaze/microblaze.c
20@@ -159,6 +159,9 @@ int microblaze_no_unsafe_delay;
21 /* Set to one if the targeted core has the CLZ insn. */
22 int microblaze_has_clz = 0;
23
24+/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
25+int microblaze_has_bitfield = 0;
26+
27 /* Which CPU pipeline do we use. We haven't really standardized on a CPU
28 version having only a particular type of pipeline. There can still be
29 options on the CPU to scale pipeline features up or down. :(
30diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
31index 3f48e48f10..712525f856 100644
32--- a/gcc/config/microblaze/microblaze.h
33+++ b/gcc/config/microblaze/microblaze.h
34@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[];
35
36 extern int microblaze_no_unsafe_delay;
37 extern int microblaze_has_clz;
38+extern int microblaze_has_bitfield;
39 extern enum pipeline_type microblaze_pipe;
40
41 #define OBJECT_FORMAT_ELF
42@@ -62,6 +63,7 @@ extern enum pipeline_type microblaze_pipe;
43
44 /* Do we have CLZ? */
45 #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz)
46+#define TARGET_HAS_BITFIELD (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
47
48 /* The default is to support PIC. */
49 #define TARGET_SUPPORTS_PIC 1
50--
512.14.2
52