Andrew Geissler | a9ff2b3 | 2020-10-16 10:11:54 -0500 | [diff] [blame] | 1 | From 1bbf48097cf2da98e03139b499a5a74bc68e6abc Mon Sep 17 00:00:00 2001 |
| 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
| 3 | Date: Tue, 17 Jan 2017 17:11:04 +0530 |
| 4 | Subject: [PATCH 20/58] [Patch,microblaze]: Inline Expansion of fsqrt builtin. |
| 5 | |
| 6 | The changes are made in the patch for the inline expansion of |
| 7 | the fsqrt builtin with fqrt instruction. The sqrt math function |
| 8 | takes double as argument and return double as argument. The |
| 9 | pattern is selected while expanding the unary op through |
| 10 | expand_unop which passes DFmode and the DFmode pattern was |
| 11 | not there returning zero. Thus the sqrt math function is not |
| 12 | inlined and expanded. The pattern with DFmode argument is added. |
| 13 | Also the source and destination argument is not same the DF |
| 14 | through two different consecutive registers with lower 32 bit |
| 15 | is the argument passed to sqrt and the higher 32 bit is zero. |
| 16 | If the source and destinations are different the DFmode 64 bits |
| 17 | registers is not set properly giving the problem in runtime. Such |
| 18 | changes are taken care in the implementation of the pattern for |
| 19 | DFmode for inline expansion of the sqrt. |
| 20 | |
| 21 | ChangeLog: |
| 22 | 2015-06-16 Ajit Agarwal <ajitkum@xilinx.com> |
| 23 | Nagaraju Mekala <nmekala@xilinx.com> |
| 24 | |
| 25 | * config/microblaze/microblaze.md (sqrtdf2): New |
| 26 | pattern. |
| 27 | |
| 28 | Signed-off-by:Ajit Agarwal ajitkum@xilinx.com |
| 29 | Nagaraju Mekala nmekala@xilinx.com |
| 30 | --- |
| 31 | gcc/config/microblaze/microblaze.md | 14 ++++++++++++++ |
| 32 | 1 file changed, 14 insertions(+) |
| 33 | |
| 34 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
| 35 | index 8f9baec826b..986d9c3aa25 100644 |
| 36 | --- a/gcc/config/microblaze/microblaze.md |
| 37 | +++ b/gcc/config/microblaze/microblaze.md |
| 38 | @@ -451,6 +451,20 @@ |
| 39 | (set_attr "mode" "SF") |
| 40 | (set_attr "length" "4")]) |
| 41 | |
| 42 | +(define_insn "sqrtdf2" |
| 43 | + [(set (match_operand:DF 0 "register_operand" "=d") |
| 44 | + (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] |
| 45 | + "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" |
| 46 | + { |
| 47 | + if (REGNO (operands[0]) == REGNO (operands[1])) |
| 48 | + return "fsqrt\t%0,%1"; |
| 49 | + else |
| 50 | + return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; |
| 51 | + } |
| 52 | + [(set_attr "type" "fsqrt") |
| 53 | + (set_attr "mode" "SF") |
| 54 | + (set_attr "length" "4")]) |
| 55 | + |
| 56 | (define_insn "fix_truncsfsi2" |
| 57 | [(set (match_operand:SI 0 "register_operand" "=d") |
| 58 | (fix:SI (match_operand:SF 1 "register_operand" "d")))] |
| 59 | -- |
| 60 | 2.17.1 |
| 61 | |