| Brad Bishop | 26bdd44 | 2019-08-16 17:08:17 -0400 | [diff] [blame] | 1 | From bcbfd9f69d858306a080aa7213e96ca6eca66106 Mon Sep 17 00:00:00 2001 |
| 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
| 3 | Date: Fri, 29 Mar 2019 12:08:39 +0530 |
| 4 | Subject: [PATCH 58/61] [Patch,Microblaze] : We will check the possibility of |
| 5 | peephole2 optimization,if we can then we will fix the compiler issue. |
| 6 | |
| 7 | --- |
| 8 | gcc/config/microblaze/microblaze.md | 63 ++++++++++++++++++++++--------------- |
| 9 | 1 file changed, 38 insertions(+), 25 deletions(-) |
| 10 | |
| 11 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
| 12 | index 88aee9e..8bd175f 100644 |
| 13 | --- a/gcc/config/microblaze/microblaze.md |
| 14 | +++ b/gcc/config/microblaze/microblaze.md |
| 15 | @@ -880,31 +880,44 @@ |
| 16 | (set_attr "mode" "SI") |
| 17 | (set_attr "length" "4")]) |
| 18 | |
| 19 | -(define_peephole2 |
| 20 | - [(set (match_operand:SI 0 "register_operand") |
| 21 | - (fix:SI (match_operand:SF 1 "register_operand"))) |
| 22 | - (set (pc) |
| 23 | - (if_then_else (match_operator 2 "ordered_comparison_operator" |
| 24 | - [(match_operand:SI 3 "register_operand") |
| 25 | - (match_operand:SI 4 "arith_operand")]) |
| 26 | - (label_ref (match_operand 5)) |
| 27 | - (pc)))] |
| 28 | - "TARGET_HARD_FLOAT && !TARGET_MB_64" |
| 29 | - [(set (match_dup 1) (match_dup 3))] |
| 30 | - |
| 31 | - { |
| 32 | - rtx condition; |
| 33 | - rtx cmp_op0 = operands[3]; |
| 34 | - rtx cmp_op1 = operands[4]; |
| 35 | - rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); |
| 36 | - |
| 37 | - emit_insn (gen_cstoresf4 (comp_reg, operands[2], |
| 38 | - gen_rtx_REG (SFmode, REGNO (cmp_op0)), |
| 39 | - gen_rtx_REG (SFmode, REGNO (cmp_op1)))); |
| 40 | - condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); |
| 41 | - emit_jump_insn (gen_condjump (condition, operands[5])); |
| 42 | - } |
| 43 | -) |
| 44 | +;; peephole2 optimization will be done only if fint and if-then-else |
| 45 | +;; are dependent.added condition for the same. |
| 46 | +;; if they are dependent then gcc is giving "flow control insn inside a basic block" |
| 47 | +;; testcase: |
| 48 | +;; volatile float vec = 1.0; |
| 49 | +;; volatile int ci = 2; |
| 50 | +;; register int cj = (int)(vec); |
| 51 | +;;// ci=cj; |
| 52 | +;;// if (ci <0) { |
| 53 | +;; if (cj < 0) { |
| 54 | +;; ci = 0; |
| 55 | +;; } |
| 56 | +;; commenting for now.we will check the possibility of this optimization later |
| 57 | + |
| 58 | +;;(define_peephole2 |
| 59 | +;; [(set (match_operand:SI 0 "register_operand") |
| 60 | +;; (fix:SI (match_operand:SF 1 "register_operand"))) |
| 61 | +;; (set (pc) |
| 62 | +;; (if_then_else (match_operator 2 "ordered_comparison_operator" |
| 63 | +;; [(match_operand:SI 3 "register_operand") |
| 64 | +;; (match_operand:SI 4 "arith_operand")]) |
| 65 | +;; (label_ref (match_operand 5)) |
| 66 | +;; (pc)))] |
| 67 | +;; "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))" |
| 68 | +;; [(set (match_dup 1) (match_dup 3))] |
| 69 | +;; { |
| 70 | +;; rtx condition; |
| 71 | +;; rtx cmp_op0 = operands[3]; |
| 72 | +;; rtx cmp_op1 = operands[4]; |
| 73 | +;; rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); |
| 74 | +;; |
| 75 | +;; emit_insn (gen_cstoresf4 (comp_reg, operands[2], |
| 76 | +;; gen_rtx_REG (SFmode, REGNO (cmp_op0)), |
| 77 | +;; gen_rtx_REG (SFmode, REGNO (cmp_op1)))); |
| 78 | +;; condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); |
| 79 | +;; emit_jump_insn (gen_condjump (condition, operands[5])); |
| 80 | +;; } |
| 81 | +;;) |
| 82 | |
| 83 | ;;---------------------------------------------------------------- |
| 84 | ;; Negation and one's complement |
| 85 | -- |
| 86 | 2.7.4 |
| 87 | |