blob: b517fd1d04dfa6b503a24e5f6c6092dc97ac4e31 [file] [log] [blame]
Thang Q. Nguyen93407872020-12-10 08:49:53 +00001From 5c45537b1d74c22cd95c196bf261b3ee3aa4856f Mon Sep 17 00:00:00 2001
2From: Quan Nguyen <quan@os.amperecomputing.com>
3Date: Thu, 12 Nov 2020 13:42:43 +0700
4Subject: [PATCH 2/2] ARM: dts: aspeed: Add device tree for Ampere's Mt. Jade
5 BMC
6
7The Mt. Jade BMC is an ASPEED AST2500-based BMC for the Mt. Jade
8hardware reference platform with Ampere's Altra Processor Family.
9
10Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
11Reviewed-by: Joel Stanley <joel@jms.id.au>
12Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
13Signed-off-by: Phong Vo <phong@os.amperecomputing.com>
14Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com>
15---
16 arch/arm/boot/dts/Makefile | 1 +
17 .../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 558 ++++++++++++++++++
18 2 files changed, 559 insertions(+)
19 create mode 100644 arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
20
21diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
22index 9f9f3e49132a..5da5e8f93554 100644
23--- a/arch/arm/boot/dts/Makefile
24+++ b/arch/arm/boot/dts/Makefile
25@@ -1398,6 +1398,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
26 aspeed-ast2500-evb.dtb \
27 aspeed-ast2600-evb.dtb \
28 aspeed-bmc-amd-ethanolx.dtb \
29+ aspeed-bmc-ampere-mtjade.dtb \
30 aspeed-bmc-arm-centriq2400-rep.dtb \
31 aspeed-bmc-arm-stardragon4800-rep2.dtb \
32 aspeed-bmc-bytedance-g220a.dtb \
33diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
34new file mode 100644
35index 000000000000..8f5ec22e51c2
36--- /dev/null
37+++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
38@@ -0,0 +1,558 @@
39+// SPDX-License-Identifier: GPL-2.0+
40+/dts-v1/;
41+#include "aspeed-g5.dtsi"
42+#include <dt-bindings/gpio/aspeed-gpio.h>
43+
44+/ {
45+ model = "Ampere Mt. Jade BMC";
46+ compatible = "ampere,mtjade-bmc", "aspeed,ast2500";
47+
48+ chosen {
49+ stdout-path = &uart5;
50+ bootargs = "console=ttyS4,115200 earlyprintk";
51+ };
52+
53+ memory@80000000 {
54+ reg = <0x80000000 0x20000000>;
55+ };
56+
57+ reserved-memory {
58+ #address-cells = <1>;
59+ #size-cells = <1>;
60+ ranges;
61+
62+ vga_memory: framebuffer@9f000000 {
63+ no-map;
64+ reg = <0x9f000000 0x01000000>; /* 16M */
65+ };
66+
67+ gfx_memory: framebuffer {
68+ size = <0x01000000>;
69+ alignment = <0x01000000>;
70+ compatible = "shared-dma-pool";
71+ reusable;
72+ };
73+
74+ video_engine_memory: jpegbuffer {
75+ size = <0x02000000>; /* 32M */
76+ alignment = <0x01000000>;
77+ compatible = "shared-dma-pool";
78+ reusable;
79+ };
80+ };
81+
82+ leds {
83+ compatible = "gpio-leds";
84+
85+ fault {
86+ gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_HIGH>;
87+ };
88+
89+ identify {
90+ gpios = <&gpio ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
91+ };
92+ };
93+
94+ gpio-keys {
95+ compatible = "gpio-keys";
96+
97+ shutdown_ack {
98+ label = "SHUTDOWN_ACK";
99+ gpios = <&gpio ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>;
100+ linux,code = <ASPEED_GPIO(G, 2)>;
101+ };
102+
103+ reboot_ack {
104+ label = "REBOOT_ACK";
105+ gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>;
106+ linux,code = <ASPEED_GPIO(J, 3)>;
107+ };
108+
109+ S0_overtemp {
110+ label = "S0_OVERTEMP";
111+ gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>;
112+ linux,code = <ASPEED_GPIO(G, 3)>;
113+ };
114+
115+ S0_hightemp {
116+ label = "S0_HIGHTEMP";
117+ gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
118+ linux,code = <ASPEED_GPIO(J, 0)>;
119+ };
120+
121+ S0_cpu_fault {
122+ label = "S0_CPU_FAULT";
123+ gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>;
124+ linux,code = <ASPEED_GPIO(J, 1)>;
125+ };
126+
127+ S1_overtemp {
128+ label = "S1_OVERTEMP";
129+ gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>;
130+ linux,code = <ASPEED_GPIO(Z, 6)>;
131+ };
132+
133+ S1_hightemp {
134+ label = "S1_HIGHTEMP";
135+ gpios = <&gpio ASPEED_GPIO(AB, 0) GPIO_ACTIVE_LOW>;
136+ linux,code = <ASPEED_GPIO(AB, 0)>;
137+ };
138+
139+ S1_cpu_fault {
140+ label = "S1_CPU_FAULT";
141+ gpios = <&gpio ASPEED_GPIO(Z, 1) GPIO_ACTIVE_HIGH>;
142+ linux,code = <ASPEED_GPIO(Z, 1)>;
143+ };
144+
145+ id_button {
146+ label = "ID_BUTTON";
147+ gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
148+ linux,code = <ASPEED_GPIO(Q, 5)>;
149+ };
150+
151+ };
152+
153+ gpioA0mux: mux-controller {
154+ compatible = "gpio-mux";
155+ #mux-control-cells = <0>;
156+ mux-gpios = <&gpio ASPEED_GPIO(A, 0) GPIO_ACTIVE_LOW>;
157+ };
158+
159+ adc0mux: adc0mux {
160+ compatible = "io-channel-mux";
161+ io-channels = <&adc 0>;
162+ #io-channel-cells = <1>;
163+ io-channel-names = "parent";
164+ mux-controls = <&gpioA0mux>;
165+ channels = "s0", "s1";
166+ };
167+
168+ adc1mux: adc1mux {
169+ compatible = "io-channel-mux";
170+ io-channels = <&adc 1>;
171+ #io-channel-cells = <1>;
172+ io-channel-names = "parent";
173+ mux-controls = <&gpioA0mux>;
174+ channels = "s0", "s1";
175+ };
176+
177+ adc2mux: adc2mux {
178+ compatible = "io-channel-mux";
179+ io-channels = <&adc 2>;
180+ #io-channel-cells = <1>;
181+ io-channel-names = "parent";
182+ mux-controls = <&gpioA0mux>;
183+ channels = "s0", "s1";
184+ };
185+
186+ adc3mux: adc3mux {
187+ compatible = "io-channel-mux";
188+ io-channels = <&adc 3>;
189+ #io-channel-cells = <1>;
190+ io-channel-names = "parent";
191+ mux-controls = <&gpioA0mux>;
192+ channels = "s0", "s1";
193+ };
194+
195+ adc4mux: adc4mux {
196+ compatible = "io-channel-mux";
197+ io-channels = <&adc 4>;
198+ #io-channel-cells = <1>;
199+ io-channel-names = "parent";
200+ mux-controls = <&gpioA0mux>;
201+ channels = "s0", "s1";
202+ };
203+
204+ adc5mux: adc5mux {
205+ compatible = "io-channel-mux";
206+ io-channels = <&adc 5>;
207+ #io-channel-cells = <1>;
208+ io-channel-names = "parent";
209+ mux-controls = <&gpioA0mux>;
210+ channels = "s0", "s1";
211+ };
212+
213+ adc6mux: adc6mux {
214+ compatible = "io-channel-mux";
215+ io-channels = <&adc 6>;
216+ #io-channel-cells = <1>;
217+ io-channel-names = "parent";
218+ mux-controls = <&gpioA0mux>;
219+ channels = "s0", "s1";
220+ };
221+
222+ adc7mux: adc7mux {
223+ compatible = "io-channel-mux";
224+ io-channels = <&adc 7>;
225+ #io-channel-cells = <1>;
226+ io-channel-names = "parent";
227+ mux-controls = <&gpioA0mux>;
228+ channels = "s0", "s1";
229+ };
230+
231+ adc8mux: adc8mux {
232+ compatible = "io-channel-mux";
233+ io-channels = <&adc 8>;
234+ #io-channel-cells = <1>;
235+ io-channel-names = "parent";
236+ mux-controls = <&gpioA0mux>;
237+ channels = "s0", "s1";
238+ };
239+
240+ adc9mux: adc9mux {
241+ compatible = "io-channel-mux";
242+ io-channels = <&adc 9>;
243+ #io-channel-cells = <1>;
244+ io-channel-names = "parent";
245+ mux-controls = <&gpioA0mux>;
246+ channels = "s0", "s1";
247+ };
248+
249+ adc10mux: adc10mux {
250+ compatible = "io-channel-mux";
251+ io-channels = <&adc 10>;
252+ #io-channel-cells = <1>;
253+ io-channel-names = "parent";
254+ mux-controls = <&gpioA0mux>;
255+ channels = "s0", "s1";
256+ };
257+
258+ adc11mux: adc11mux {
259+ compatible = "io-channel-mux";
260+ io-channels = <&adc 11>;
261+ #io-channel-cells = <1>;
262+ io-channel-names = "parent";
263+ mux-controls = <&gpioA0mux>;
264+ channels = "s0", "s1";
265+ };
266+
267+ adc12mux: adc12mux {
268+ compatible = "io-channel-mux";
269+ io-channels = <&adc 12>;
270+ #io-channel-cells = <1>;
271+ io-channel-names = "parent";
272+ mux-controls = <&gpioA0mux>;
273+ channels = "s0", "s1";
274+ };
275+
276+ adc13mux: adc13mux {
277+ compatible = "io-channel-mux";
278+ io-channels = <&adc 13>;
279+ #io-channel-cells = <1>;
280+ io-channel-names = "parent";
281+ mux-controls = <&gpioA0mux>;
282+ channels = "s0", "s1";
283+ };
284+
285+ iio-hwmon {
286+ compatible = "iio-hwmon";
287+ io-channels = <&adc0mux 0>, <&adc0mux 1>,
288+ <&adc1mux 0>, <&adc1mux 1>,
289+ <&adc2mux 0>, <&adc2mux 1>,
290+ <&adc3mux 0>, <&adc3mux 1>,
291+ <&adc4mux 0>, <&adc4mux 1>,
292+ <&adc5mux 0>, <&adc5mux 1>,
293+ <&adc6mux 0>, <&adc6mux 1>,
294+ <&adc7mux 0>, <&adc7mux 1>,
295+ <&adc8mux 0>, <&adc8mux 1>,
296+ <&adc9mux 0>, <&adc9mux 1>,
297+ <&adc10mux 0>, <&adc10mux 1>,
298+ <&adc11mux 0>, <&adc11mux 1>,
299+ <&adc12mux 0>, <&adc12mux 1>,
300+ <&adc13mux 0>, <&adc13mux 1>;
301+ };
302+
303+ iio-hwmon-adc14 {
304+ compatible = "iio-hwmon";
305+ io-channels = <&adc 14>;
306+ };
307+
308+ iio-hwmon-battery {
309+ compatible = "iio-hwmon";
310+ io-channels = <&adc 15>;
311+ };
312+};
313+
314+&fmc {
315+ status = "okay";
316+ flash@0 {
317+ status = "okay";
318+ m25p,fast-read;
319+ label = "bmc";
320+ /* spi-max-frequency = <50000000>; */
321+#include "openbmc-flash-layout.dtsi"
322+ };
323+};
324+
325+&spi1 {
326+ status = "okay";
327+ pinctrl-names = "default";
328+ pinctrl-0 = <&pinctrl_spi1_default>;
329+
330+ flash@0 {
331+ status = "okay";
332+ m25p,fast-read;
333+ label = "pnor";
334+ /* spi-max-frequency = <100000000>; */
335+ };
336+};
337+
338+&uart1 {
339+ status = "okay";
340+ pinctrl-names = "default";
341+ pinctrl-0 = <&pinctrl_txd1_default
342+ &pinctrl_rxd1_default
343+ &pinctrl_ncts1_default
344+ &pinctrl_nrts1_default>;
345+};
346+
347+&uart2 {
348+ status = "okay";
349+ pinctrl-names = "default";
350+ pinctrl-0 = <&pinctrl_txd2_default
351+ &pinctrl_rxd2_default>;
352+};
353+
354+&uart3 {
355+ status = "okay";
356+ pinctrl-names = "default";
357+ pinctrl-0 = <&pinctrl_txd3_default
358+ &pinctrl_rxd3_default>;
359+};
360+
361+&uart4 {
362+ status = "okay";
363+ pinctrl-names = "default";
364+ pinctrl-0 = <&pinctrl_txd4_default
365+ &pinctrl_rxd4_default>;
366+};
367+
368+/* The BMC's uart */
369+&uart5 {
370+ status = "okay";
371+};
372+
373+&mac1 {
374+ status = "okay";
375+ pinctrl-names = "default";
376+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
377+};
378+
379+&i2c0 {
380+ status = "okay";
381+};
382+
383+&i2c1 {
384+ status = "okay";
385+};
386+
387+&i2c2 {
388+ status = "okay";
389+};
390+
391+&i2c3 {
392+ status = "okay";
393+ eeprom@50 {
394+ compatible = "microchip,24c64", "atmel,24c64";
395+ reg = <0x50>;
396+ pagesize = <32>;
397+ };
398+
399+ inlet_mem2: tmp175@28 {
400+ compatible = "ti,tmp175";
401+ reg = <0x28>;
402+ };
403+
404+ inlet_cpu: tmp175@29 {
405+ compatible = "ti,tmp175";
406+ reg = <0x29>;
407+ };
408+
409+ inlet_mem1: tmp175@2a {
410+ compatible = "ti,tmp175";
411+ reg = <0x2a>;
412+ };
413+
414+ outlet_cpu: tmp175@2b {
415+ compatible = "ti,tmp175";
416+ reg = <0x2b>;
417+ };
418+
419+ outlet1: tmp175@2c {
420+ compatible = "ti,tmp175";
421+ reg = <0x2c>;
422+ };
423+
424+ outlet2: tmp175@2d {
425+ compatible = "ti,tmp175";
426+ reg = <0x2d>;
427+ };
428+};
429+
430+&i2c4 {
431+ status = "okay";
432+ rtc@51 {
433+ compatible = "nxp,pcf85063a";
434+ reg = <0x51>;
435+ };
436+};
437+
438+&i2c5 {
439+ status = "okay";
440+};
441+
442+&i2c6 {
443+ status = "okay";
444+ psu@58 {
445+ compatible = "pmbus";
446+ reg = <0x58>;
447+ };
448+
449+ psu@59 {
450+ compatible = "pmbus";
451+ reg = <0x59>;
452+ };
453+};
454+
455+&i2c7 {
456+ status = "okay";
457+};
458+
459+&i2c8 {
460+ status = "okay";
461+};
462+
463+&i2c9 {
464+ status = "okay";
465+};
466+
467+&gfx {
468+ status = "okay";
469+ memory-region = <&gfx_memory>;
470+};
471+
472+&pinctrl {
473+ aspeed,external-nodes = <&gfx &lhc>;
474+};
475+
476+&pwm_tacho {
477+ status = "okay";
478+ pinctrl-names = "default";
479+ pinctrl-0 = <&pinctrl_pwm2_default &pinctrl_pwm3_default
480+ &pinctrl_pwm4_default &pinctrl_pwm5_default
481+ &pinctrl_pwm6_default &pinctrl_pwm7_default>;
482+
483+ fan@0 {
484+ reg = <0x02>;
485+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
486+ };
487+
488+ fan@1 {
489+ reg = <0x02>;
490+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
491+ };
492+
493+ fan@2 {
494+ reg = <0x03>;
495+ aspeed,fan-tach-ch = /bits/ 8 <0x06>;
496+ };
497+
498+ fan@3 {
499+ reg = <0x03>;
500+ aspeed,fan-tach-ch = /bits/ 8 <0x07>;
501+ };
502+
503+ fan@4 {
504+ reg = <0x04>;
505+ aspeed,fan-tach-ch = /bits/ 8 <0x08>;
506+ };
507+
508+ fan@5 {
509+ reg = <0x04>;
510+ aspeed,fan-tach-ch = /bits/ 8 <0x09>;
511+ };
512+
513+ fan@6 {
514+ reg = <0x05>;
515+ aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
516+ };
517+
518+ fan@7 {
519+ reg = <0x05>;
520+ aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
521+ };
522+
523+ fan@8 {
524+ reg = <0x06>;
525+ aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
526+ };
527+
528+ fan@9 {
529+ reg = <0x06>;
530+ aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
531+ };
532+
533+ fan@10 {
534+ reg = <0x07>;
535+ aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
536+ };
537+
538+ fan@11 {
539+ reg = <0x07>;
540+ aspeed,fan-tach-ch = /bits/ 8 <0x0f>;
541+ };
542+
543+};
544+
545+&vhub {
546+ status = "okay";
547+};
548+
549+&adc {
550+ status = "okay";
551+};
552+
553+&video {
554+ status = "okay";
555+ memory-region = <&video_engine_memory>;
556+};
557+
558+&gpio {
559+ gpio-line-names =
560+ /*A0-A7*/ "","","","S0_BMC_SPECIAL_BOOT","","","","",
561+ /*B0-B7*/ "BMC_SELECT_EEPROM","","","",
562+ "POWER_BUTTON","","","",
563+ /*C0-C7*/ "","","","","","","","",
564+ /*D0-D7*/ "","","","","","","","",
565+ /*E0-E7*/ "","","","","","","","",
566+ /*F0-F7*/ "","","BMC_SYS_PSON_L","S0_DDR_SAVE","PGOOD",
567+ "S1_DDR_SAVE","","",
568+ /*G0-G7*/ "S0_FW_BOOT_OK","SHD_REQ_L","","S0_OVERTEMP_L","","",
569+ "","",
570+ /*H0-H7*/ "","","","","","","","",
571+ /*I0-I7*/ "","","S1_BMC_SPECIAL_BOOT","","","","","",
572+ /*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","",
573+ "","","","",
574+ /*K0-K7*/ "","","","","","","","",
575+ /*L0-L7*/ "","","","BMC_SYSRESET_L","SPI_AUTH_FAIL_L","","","",
576+ /*M0-M7*/ "","","","","","","","",
577+ /*N0-N7*/ "","","","","","","","",
578+ /*O0-O7*/ "","","","","","","","",
579+ /*P0-P7*/ "","","","","","","","",
580+ /*Q0-Q7*/ "","","","","","UID_BUTTON","","",
581+ /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","","","RESET_BUTTON","","",
582+ /*S0-S7*/ "","","","","","","","",
583+ /*T0-T7*/ "","","","","","","","",
584+ /*U0-U7*/ "","","","","","","","",
585+ /*V0-V7*/ "","","","","","","","",
586+ /*W0-W7*/ "","","","","","","","",
587+ /*X0-X7*/ "","","","","","","","",
588+ /*Y0-Y7*/ "","","","","","","","",
589+ /*Z0-Z7*/ "S0_BMC_PLIMIT","S1_FAULT_L","S1_FW_BOOT_OK","","",
590+ "S1_SCP_AUTH_FAIL_L","S1_OVERTEMP_L","",
591+ /*AA0-AA7*/ "","","","","","","","",
592+ /*AB0-AB7*/ "S1_HIGHTEMP_L","S1_BMC_PLIMIT","S0_BMC_DDR_ADDR",
593+ "S1_BMC_DDR_ADR","","","","",
594+ /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L",
595+ "BMC_OCP_PG";
596+};
597--
5982.28.0
599