| Andrew Geissler | eff2747 | 2021-10-29 15:35:00 -0500 | [diff] [blame] | 1 | Add RISCV32 support |
| 2 | |
| 3 | Upstream-Status: Pending |
| 4 | Signed-off-by: Khem Raj <raj.khem@gmail.com> |
| 5 | |
| 6 | --- a/build/moz.configure/init.configure |
| 7 | +++ b/build/moz.configure/init.configure |
| 8 | @@ -765,6 +765,9 @@ def split_triplet(triplet, allow_msvc=Fa |
| 9 | elif cpu.startswith("aarch64"): |
| 10 | canonical_cpu = "aarch64" |
| 11 | endianness = "little" |
| 12 | + elif cpu in ("riscv32", "riscv32gc"): |
| 13 | + canonical_cpu = "riscv32" |
| 14 | + endianness = "little" |
| 15 | elif cpu in ("riscv64", "riscv64gc"): |
| 16 | canonical_cpu = "riscv64" |
| 17 | endianness = "little" |
| 18 | --- a/python/mozbuild/mozbuild/configure/constants.py |
| 19 | +++ b/python/mozbuild/mozbuild/configure/constants.py |
| 20 | @@ -52,6 +52,7 @@ CPU_bitness = { |
| 21 | "mips64": 64, |
| 22 | "ppc": 32, |
| 23 | "ppc64": 64, |
| 24 | + 'riscv32': 32, |
| 25 | "riscv64": 64, |
| 26 | "s390": 32, |
| 27 | "s390x": 64, |
| 28 | @@ -94,6 +95,7 @@ CPU_preprocessor_checks = OrderedDict( |
| 29 | ("m68k", "__m68k__"), |
| 30 | ("mips64", "__mips64"), |
| 31 | ("mips32", "__mips__"), |
| 32 | + ("riscv32", "__riscv && __riscv_xlen == 32"), |
| 33 | ("riscv64", "__riscv && __riscv_xlen == 64"), |
| 34 | ("sh4", "__sh__"), |
| 35 | ("wasm32", "__wasm32__"), |
| 36 | --- a/python/mozbuild/mozbuild/test/configure/test_toolchain_configure.py |
| 37 | +++ b/python/mozbuild/mozbuild/test/configure/test_toolchain_configure.py |
| 38 | @@ -1186,6 +1186,7 @@ class LinuxCrossCompileToolchainTest(Bas |
| 39 | "m68k-unknown-linux-gnu": big_endian + {"__m68k__": 1}, |
| 40 | "mips64-unknown-linux-gnuabi64": big_endian + {"__mips64": 1, "__mips__": 1}, |
| 41 | "mips-unknown-linux-gnu": big_endian + {"__mips__": 1}, |
| 42 | + "riscv32-unknown-linux-gnu": little_endian + {"__riscv": 1, "__riscv_xlen": 32}, |
| 43 | "riscv64-unknown-linux-gnu": little_endian + {"__riscv": 1, "__riscv_xlen": 64}, |
| 44 | "sh4-unknown-linux-gnu": little_endian + {"__sh__": 1}, |
| 45 | } |