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Andrew Geisslera9ff2b32020-10-16 10:11:54 -05001From 90edf612331af9b7e99105112c2067a3f085daef Mon Sep 17 00:00:00 2001
Brad Bishop26bdd442019-08-16 17:08:17 -04002From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Tue, 9 Oct 2018 10:07:08 +0530
Andrew Geisslera9ff2b32020-10-16 10:11:54 -05004Subject: [PATCH 41/58] Fix various
Brad Bishop26bdd442019-08-16 17:08:17 -04005
Andrew Geisslera9ff2b32020-10-16 10:11:54 -05006-Added double arith instructions
7-Fixed prologue stack pointer decrement issue
Brad Bishop26bdd442019-08-16 17:08:17 -04008---
Andrew Geisslera9ff2b32020-10-16 10:11:54 -05009 gcc/config/microblaze/microblaze.md | 78 +++++++++++++++++++++++++----
10 gcc/config/microblaze/t-microblaze | 7 +++
Brad Bishop26bdd442019-08-16 17:08:17 -040011 2 files changed, 76 insertions(+), 9 deletions(-)
12
13diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
Andrew Geisslera9ff2b32020-10-16 10:11:54 -050014index 013c77651c3..645f48f2847 100644
Brad Bishop26bdd442019-08-16 17:08:17 -040015--- a/gcc/config/microblaze/microblaze.md
16+++ b/gcc/config/microblaze/microblaze.md
Andrew Geissler84ad7c52020-06-27 00:00:16 -050017@@ -527,6 +527,66 @@
Brad Bishop26bdd442019-08-16 17:08:17 -040018 (set_attr "mode" "SF")
19 (set_attr "length" "4")])
20
21+(define_insn "fix_truncsfsi2"
22+ [(set (match_operand:SI 0 "register_operand" "=d")
23+ (fix:SI (match_operand:SF 1 "register_operand" "d")))]
24+ "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
25+ "fint\t%0,%1"
26+ [(set_attr "type" "fint")
27+ (set_attr "mode" "SF")
28+ (set_attr "length" "4")])
29+
30+
31+(define_insn "adddf3"
32+ [(set (match_operand:DF 0 "register_operand" "=d")
33+ (plus:DF (match_operand:DF 1 "register_operand" "d")
34+ (match_operand:DF 2 "register_operand" "d")))]
35+ "TARGET_MB_64"
36+ "dadd\t%0,%1,%2"
37+ [(set_attr "type" "fadd")
38+ (set_attr "mode" "DF")
39+ (set_attr "length" "4")])
40+
41+(define_insn "subdf3"
42+ [(set (match_operand:DF 0 "register_operand" "=d")
43+ (minus:DF (match_operand:DF 1 "register_operand" "d")
44+ (match_operand:DF 2 "register_operand" "d")))]
45+ "TARGET_MB_64"
46+ "drsub\t%0,%2,%1"
47+ [(set_attr "type" "frsub")
48+ (set_attr "mode" "DF")
49+ (set_attr "length" "4")])
50+
51+(define_insn "muldf3"
52+ [(set (match_operand:DF 0 "register_operand" "=d")
53+ (mult:DF (match_operand:DF 1 "register_operand" "d")
54+ (match_operand:DF 2 "register_operand" "d")))]
55+ "TARGET_MB_64"
56+ "dmul\t%0,%1,%2"
57+ [(set_attr "type" "fmul")
58+ (set_attr "mode" "DF")
59+ (set_attr "length" "4")])
60+
61+(define_insn "divdf3"
62+ [(set (match_operand:DF 0 "register_operand" "=d")
63+ (div:DF (match_operand:DF 1 "register_operand" "d")
64+ (match_operand:DF 2 "register_operand" "d")))]
65+ "TARGET_MB_64"
66+ "ddiv\t%0,%2,%1"
67+ [(set_attr "type" "fdiv")
68+ (set_attr "mode" "DF")
69+ (set_attr "length" "4")])
70+
71+
72+(define_insn "sqrtdf2"
73+ [(set (match_operand:DF 0 "register_operand" "=d")
74+ (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
75+ "TARGET_MB_64"
76+ "dsqrt\t%0,%1"
77+ [(set_attr "type" "fsqrt")
78+ (set_attr "mode" "DF")
79+ (set_attr "length" "4")])
80+
81 (define_insn "floatdidf2"
82 [(set (match_operand:DF 0 "register_operand" "=d")
83 (float:DF (match_operand:DI 1 "register_operand" "d")))]
Andrew Geissler84ad7c52020-06-27 00:00:16 -050084@@ -536,13 +596,13 @@
Brad Bishop26bdd442019-08-16 17:08:17 -040085 (set_attr "mode" "DF")
86 (set_attr "length" "4")])
87
88-(define_insn "fix_truncsfsi2"
89- [(set (match_operand:SI 0 "register_operand" "=d")
90- (fix:SI (match_operand:SF 1 "register_operand" "d")))]
91- "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
92- "fint\t%0,%1"
93- [(set_attr "type" "fint")
94- (set_attr "mode" "SF")
95+(define_insn "floatdfdi2"
96+ [(set (match_operand:DI 0 "register_operand" "=d")
97+ (float:DI (match_operand:DF 1 "register_operand" "d")))]
98+ "TARGET_MB_64"
99+ "dlong\t%0,%1"
100+ [(set_attr "type" "fcvt")
101+ (set_attr "mode" "DI")
102 (set_attr "length" "4")])
103
104 ;;----------------------------------------------------------------
Andrew Geissler84ad7c52020-06-27 00:00:16 -0500105@@ -660,8 +720,8 @@
Brad Bishop26bdd442019-08-16 17:08:17 -0400106 "TARGET_MB_64"
107 "@
108 rsubl\t%0,%2,%1
109- addik\t%0,%z1,-%2
110- addik\t%0,%z1,-%2"
111+ addlik\t%0,%z1,-%2
112+ addlik\t%0,%z1,-%2"
113 [(set_attr "type" "arith,no_delay_arith,no_delay_arith")
114 (set_attr "mode" "DI")
115 (set_attr "length" "4,4,4")])
116diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
Andrew Geisslera9ff2b32020-10-16 10:11:54 -0500117index 35ab9654052..dfef45c268e 100644
Brad Bishop26bdd442019-08-16 17:08:17 -0400118--- a/gcc/config/microblaze/t-microblaze
119+++ b/gcc/config/microblaze/t-microblaze
120@@ -1,6 +1,13 @@
121 MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
122 MULTILIB_DIRNAMES = m64 bs le m mh
123 MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
124+MULTILIB_EXCEPTIONS += *m64
125+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift
126+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
127+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul
128+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
129+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high
130+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high
131 MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
132 MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
133 MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
134--
Andrew Geisslera9ff2b32020-10-16 10:11:54 -05001352.17.1
Brad Bishop26bdd442019-08-16 17:08:17 -0400136